Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337444 |
1 |
|
|
T3 |
3633 |
|
T4 |
1444 |
|
T14 |
1198 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
173240 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
122851 |
1 |
|
|
T3 |
97 |
|
T4 |
43 |
|
T14 |
1181 |
seven_bytes |
5918 |
1 |
|
|
T3 |
107 |
|
T4 |
30 |
|
T26 |
10 |
six_bytes |
5867 |
1 |
|
|
T3 |
100 |
|
T4 |
42 |
|
T26 |
12 |
five_bytes |
5861 |
1 |
|
|
T3 |
95 |
|
T4 |
24 |
|
T26 |
12 |
four_bytes |
5989 |
1 |
|
|
T3 |
94 |
|
T4 |
35 |
|
T26 |
15 |
three_bytes |
5897 |
1 |
|
|
T3 |
89 |
|
T4 |
34 |
|
T26 |
12 |
two_bytes |
5833 |
1 |
|
|
T3 |
109 |
|
T4 |
38 |
|
T26 |
15 |
one_byte |
5988 |
1 |
|
|
T3 |
80 |
|
T4 |
38 |
|
T26 |
11 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330918 |
1 |
|
|
T3 |
3589 |
|
T4 |
1426 |
|
T14 |
1164 |
auto[1] |
6526 |
1 |
|
|
T3 |
44 |
|
T4 |
18 |
|
T14 |
34 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337444 |
1 |
|
|
T3 |
3633 |
|
T4 |
1444 |
|
T14 |
1198 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337413 |
1 |
|
|
T3 |
3632 |
|
T4 |
1444 |
|
T14 |
1198 |
auto[1] |
31 |
1 |
|
|
T3 |
1 |
|
T100 |
2 |
|
T158 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2286 |
1 |
|
|
T3 |
4 |
|
T4 |
5 |
|
T14 |
17 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6526 |
1 |
|
|
T3 |
44 |
|
T4 |
18 |
|
T14 |
34 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174137 |
1 |
|
|
T3 |
727 |
|
T4 |
1041 |
|
T14 |
501 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
92474 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59526 |
1 |
|
|
T3 |
15 |
|
T4 |
24 |
|
T14 |
494 |
seven_bytes |
3228 |
1 |
|
|
T3 |
21 |
|
T4 |
30 |
|
T26 |
11 |
six_bytes |
3270 |
1 |
|
|
T3 |
16 |
|
T4 |
21 |
|
T26 |
13 |
five_bytes |
3170 |
1 |
|
|
T3 |
21 |
|
T4 |
25 |
|
T26 |
9 |
four_bytes |
3165 |
1 |
|
|
T3 |
21 |
|
T4 |
28 |
|
T26 |
10 |
three_bytes |
3100 |
1 |
|
|
T3 |
14 |
|
T4 |
20 |
|
T26 |
12 |
two_bytes |
3052 |
1 |
|
|
T3 |
17 |
|
T4 |
34 |
|
T26 |
9 |
one_byte |
3152 |
1 |
|
|
T3 |
17 |
|
T4 |
37 |
|
T26 |
13 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170894 |
1 |
|
|
T3 |
715 |
|
T4 |
1031 |
|
T14 |
487 |
auto[1] |
3243 |
1 |
|
|
T3 |
12 |
|
T4 |
10 |
|
T14 |
14 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174137 |
1 |
|
|
T3 |
727 |
|
T4 |
1041 |
|
T14 |
501 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174127 |
1 |
|
|
T3 |
727 |
|
T4 |
1041 |
|
T14 |
501 |
auto[1] |
10 |
1 |
|
|
T101 |
1 |
|
T44 |
1 |
|
T125 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1110 |
1 |
|
|
T3 |
1 |
|
T14 |
7 |
|
T16 |
7 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3243 |
1 |
|
|
T3 |
12 |
|
T4 |
10 |
|
T14 |
14 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169272 |
1 |
|
|
T3 |
1550 |
|
T4 |
360 |
|
T14 |
325 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86790 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61733 |
1 |
|
|
T3 |
32 |
|
T4 |
8 |
|
T14 |
319 |
seven_bytes |
3030 |
1 |
|
|
T3 |
49 |
|
T4 |
15 |
|
T42 |
24 |
six_bytes |
2833 |
1 |
|
|
T3 |
34 |
|
T4 |
9 |
|
T42 |
28 |
five_bytes |
3007 |
1 |
|
|
T3 |
43 |
|
T4 |
12 |
|
T42 |
23 |
four_bytes |
2974 |
1 |
|
|
T3 |
44 |
|
T4 |
4 |
|
T42 |
34 |
three_bytes |
2983 |
1 |
|
|
T3 |
33 |
|
T4 |
9 |
|
T42 |
19 |
two_bytes |
2981 |
1 |
|
|
T3 |
47 |
|
T4 |
15 |
|
T42 |
27 |
one_byte |
2941 |
1 |
|
|
T3 |
45 |
|
T4 |
10 |
|
T42 |
26 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165984 |
1 |
|
|
T3 |
1530 |
|
T4 |
352 |
|
T14 |
313 |
auto[1] |
3288 |
1 |
|
|
T3 |
20 |
|
T4 |
8 |
|
T14 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169272 |
1 |
|
|
T3 |
1550 |
|
T4 |
360 |
|
T14 |
325 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169257 |
1 |
|
|
T3 |
1550 |
|
T4 |
360 |
|
T14 |
325 |
auto[1] |
15 |
1 |
|
|
T24 |
1 |
|
T43 |
1 |
|
T123 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1146 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3288 |
1 |
|
|
T3 |
20 |
|
T4 |
8 |
|
T14 |
12 |