Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

154946987

1

T1

20

T2

545142

T3

225031

full_word

127520352

1

T1

6

T2

339446

T3

324576

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	282467039	1			T1	26		T2	884588		T3	549607
auto[TlIntgErrCmd]	111	1			T106	9		T107	3		T108	8
auto[TlIntgErrData]	100	1			T106	4		T107	5		T108	6
auto[TlIntgErrBoth]	89	1			T106	7		T107	2		T108	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148491283

1

T1

1

T2

451529

T3

299655

auto[1]

133976056

1

T1

25

T2

433059

T3

249952

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	93166258	1			T2	321890		T3	137150		T4	284108
auto[TlIntgErrNone]	partial	auto[1]	61780455	1			T1	20		T2	223252		T3	87881
auto[TlIntgErrNone]	full_word	auto[0]	55324914	1			T1	1		T2	129639		T3	162505
auto[TlIntgErrNone]	full_word	auto[1]	72195412	1			T1	5		T2	209807		T3	162071
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T106	4		T107	2		T108	4
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T106	5		T107	1		T108	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T108	1		T171	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T171	1		T172	1		T173	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T106	1		T107	1		T108	5
auto[TlIntgErrData]	partial	auto[1]	54	1			T106	3		T107	4		T108	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T169	1		T170	1		T174	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T173	1		T175	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	25	1			T106	1		T108	3		T169	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T106	5		T107	1		T108	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T176	1		T177	1		T178	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T106	1		T107	1		T108	1