Module Definition
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Module : prim_sec_anchor_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sec_anchor_0.1/rtl/prim_sec_anchor_buf.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_sha3.u_keccak.u_prim_sec_anchor_buf
tb.dut.u_app_intf.u_prim_buf_state_output_sel
tb.dut.u_app_intf.u_prim_buf_state_err_check
tb.dut.u_app_intf.u_prim_buf_state_kmac_sel
tb.dut.u_app_intf.u_prim_buf_state_output_valid
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[3].u_prim_buf



Module Instance : tb.dut.u_sha3.u_keccak.u_prim_sec_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.06 65.98 100.00 40.00 79.31 100.00 u_keccak


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_prim_buf_state_output_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.49 90.99 84.93 40.00 86.52 100.00 u_app_intf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_prim_buf_state_err_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.49 90.99 84.93 40.00 86.52 100.00 u_app_intf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_prim_buf_state_kmac_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.49 90.99 84.93 40.00 86.52 100.00 u_app_intf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_prim_buf_state_output_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.49 90.99 84.93 40.00 86.52 100.00 u_app_intf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_lc_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00