Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1428778082	80088	0	0
entropy_period_rd_A	1428778082	1358	0	0
intr_enable_rd_A	1428778082	1734	0	0
prefix_0_rd_A	1428778082	1140	0	0
prefix_10_rd_A	1428778082	1147	0	0
prefix_1_rd_A	1428778082	1096	0	0
prefix_2_rd_A	1428778082	1109	0	0
prefix_3_rd_A	1428778082	1048	0	0
prefix_4_rd_A	1428778082	1145	0	0
prefix_5_rd_A	1428778082	1284	0	0
prefix_6_rd_A	1428778082	1055	0	0
prefix_7_rd_A	1428778082	1061	0	0
prefix_8_rd_A	1428778082	1063	0	0
prefix_9_rd_A	1428778082	1099	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	80088	0	0
T30	259448	25989	0	0
T32	0	51172	0	0
T35	3709	0	0	0
T46	0	3	0	0
T104	0	62	0	0
T105	0	81	0	0
T106	0	3	0	0
T107	0	2	0	0
T109	0	144	0	0
T118	0	2	0	0
T119	0	1	0	0
T121	481703	0	0	0
T122	226484	0	0	0
T123	281659	0	0	0
T124	106938	0	0	0
T125	191751	0	0	0
T126	110152	0	0	0
T127	20976	0	0	0
T128	645362	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1358	0	0
T32	107312	110	0	0
T46	0	21	0	0
T89	0	10	0	0
T90	0	12	0	0
T118	0	15	0	0
T130	0	18	0	0
T142	0	3	0	0
T143	0	80	0	0
T144	0	9	0	0
T145	0	6	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1734	0	0
T32	107312	111	0	0
T46	0	32	0	0
T89	0	4	0	0
T112	0	21	0	0
T118	0	22	0	0
T142	0	18	0	0
T143	0	50	0	0
T144	0	1	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T155	0	12	0	0
T156	0	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1140	0	0
T32	107312	87	0	0
T46	0	27	0	0
T89	0	1	0	0
T90	0	23	0	0
T118	0	10	0	0
T130	0	17	0	0
T142	0	30	0	0
T143	0	32	0	0
T144	0	5	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1147	0	0
T32	107312	148	0	0
T46	0	9	0	0
T89	0	8	0	0
T90	0	27	0	0
T118	0	13	0	0
T130	0	17	0	0
T142	0	28	0	0
T143	0	64	0	0
T144	0	8	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	17	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1096	0	0
T32	107312	146	0	0
T46	0	15	0	0
T89	0	12	0	0
T90	0	22	0	0
T118	0	26	0	0
T130	0	9	0	0
T143	0	33	0	0
T144	0	6	0	0
T145	0	5	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1109	0	0
T32	107312	114	0	0
T46	0	8	0	0
T90	0	27	0	0
T118	0	12	0	0
T130	0	12	0	0
T142	0	4	0	0
T143	0	55	0	0
T144	0	7	0	0
T145	0	1	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	14	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1048	0	0
T32	107312	126	0	0
T46	0	21	0	0
T89	0	4	0	0
T90	0	22	0	0
T118	0	21	0	0
T130	0	25	0	0
T142	0	13	0	0
T143	0	50	0	0
T144	0	6	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1145	0	0
T32	107312	126	0	0
T46	0	12	0	0
T89	0	9	0	0
T90	0	24	0	0
T118	0	7	0	0
T130	0	12	0	0
T142	0	21	0	0
T143	0	70	0	0
T144	0	9	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	23	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1284	0	0
T32	107312	153	0	0
T46	0	15	0	0
T89	0	5	0	0
T90	0	23	0	0
T118	0	24	0	0
T130	0	13	0	0
T142	0	16	0	0
T143	0	42	0	0
T144	0	5	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1055	0	0
T32	107312	118	0	0
T46	0	20	0	0
T89	0	18	0	0
T90	0	25	0	0
T118	0	18	0	0
T130	0	25	0	0
T142	0	17	0	0
T143	0	39	0	0
T144	0	2	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1061	0	0
T32	107312	173	0	0
T46	0	15	0	0
T89	0	13	0	0
T90	0	2	0	0
T105	0	2	0	0
T118	0	20	0	0
T142	0	7	0	0
T143	0	18	0	0
T144	0	8	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	9	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1063	0	0
T32	107312	128	0	0
T46	0	20	0	0
T89	0	8	0	0
T90	0	24	0	0
T118	0	18	0	0
T130	0	13	0	0
T142	0	16	0	0
T143	0	18	0	0
T144	0	1	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0
T157	0	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428778082	1099	0	0
T32	107312	109	0	0
T46	0	18	0	0
T89	0	6	0	0
T90	0	20	0	0
T109	0	9	0	0
T118	0	27	0	0
T130	0	14	0	0
T142	0	4	0	0
T143	0	44	0	0
T144	0	7	0	0
T146	1509	0	0	0
T147	140876	0	0	0
T148	471481	0	0	0
T149	138932	0	0	0
T150	314494	0	0	0
T151	973731	0	0	0
T152	373600	0	0	0
T153	602538	0	0	0
T154	483933	0	0	0