Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	166542627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

135688436

1

T1

23756

T2

1425

T3

1398

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	158940579	1			T1	25617		T2	1113		T3	1085
values[0x0]	68899613	1			T1	5747		T2	485		T3	465
values[0x1]	74390871	1			T1	6393		T2	542		T3	530

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	129744692	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172486371

1

T1

26989

T2

1604

T3

1554

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	944632	1			T1	172		T2	12		T3	7
valid_sources[0x01]	949205	1			T1	164		T2	4		T3	3
valid_sources[0x02]	947443	1			T1	116		T2	9		T3	6
valid_sources[0x03]	938687	1			T1	177		T2	9		T3	10
valid_sources[0x04]	948598	1			T1	145		T2	7		T3	10
valid_sources[0x05]	1089801	1			T1	121		T2	13		T3	13
valid_sources[0x06]	941980	1			T1	180		T2	11		T3	10
valid_sources[0x07]	1080077	1			T1	191		T2	9		T3	7
valid_sources[0x08]	945821	1			T1	190		T2	9		T3	7
valid_sources[0x09]	2986962	1			T1	147		T2	8		T3	13
valid_sources[0x0a]	939851	1			T1	142		T2	4		T3	8
valid_sources[0x0b]	1136247	1			T1	164		T2	13		T3	8
valid_sources[0x0c]	1010889	1			T1	156		T2	10		T3	14
valid_sources[0x0d]	941505	1			T1	172		T2	5		T3	8
valid_sources[0x0e]	948138	1			T1	144		T2	7		T3	6
valid_sources[0x0f]	937022	1			T1	127		T2	9		T3	5
valid_sources[0x10]	937622	1			T1	206		T2	11		T3	2
valid_sources[0x11]	944447	1			T1	170		T2	17		T3	6
valid_sources[0x12]	940225	1			T1	113		T2	2		T3	9
valid_sources[0x13]	944716	1			T1	203		T2	7		T3	10
valid_sources[0x14]	947359	1			T1	171		T2	17		T3	10
valid_sources[0x15]	941214	1			T1	136		T2	7		T3	11
valid_sources[0x16]	940838	1			T1	137		T2	7		T3	7
valid_sources[0x17]	940890	1			T1	170		T2	6		T3	9
valid_sources[0x18]	2981317	1			T1	226		T2	8		T3	8
valid_sources[0x19]	996662	1			T1	184		T2	5		T3	7
valid_sources[0x1a]	952975	1			T1	123		T2	24		T3	8
valid_sources[0x1b]	3663652	1			T1	141		T2	13		T3	7
valid_sources[0x1c]	946675	1			T1	169		T2	10		T3	7
valid_sources[0x1d]	940386	1			T1	134		T2	6		T3	6
valid_sources[0x1e]	1031126	1			T1	135		T2	7		T3	14
valid_sources[0x1f]	944940	1			T1	126		T2	7		T3	4
valid_sources[0x20]	1412890	1			T1	166		T2	11		T3	5
valid_sources[0x21]	946170	1			T1	122		T2	10		T3	7
valid_sources[0x22]	998508	1			T1	186		T2	7		T3	9
valid_sources[0x23]	957392	1			T1	172		T2	7		T3	5
valid_sources[0x24]	933263	1			T1	140		T2	8		T3	7
valid_sources[0x25]	1117207	1			T1	119		T2	16		T3	4
valid_sources[0x26]	943959	1			T1	186		T2	8		T3	2
valid_sources[0x27]	943118	1			T1	160		T2	13		T3	9
valid_sources[0x28]	2525144	1			T1	89		T2	8		T3	9
valid_sources[0x29]	980030	1			T1	167		T2	10		T3	6
valid_sources[0x2a]	1659780	1			T1	138		T2	2		T3	11
valid_sources[0x2b]	941164	1			T1	95		T2	12		T3	11
valid_sources[0x2c]	944247	1			T1	216		T2	4		T3	7
valid_sources[0x2d]	3031743	1			T1	99		T2	8		T3	16
valid_sources[0x2e]	1593008	1			T1	122		T2	7		T3	9
valid_sources[0x2f]	978719	1			T1	128		T2	10		T3	7
valid_sources[0x30]	2972886	1			T1	127		T2	5		T3	4
valid_sources[0x31]	942009	1			T1	117		T2	8		T3	7
valid_sources[0x32]	1133851	1			T1	115		T2	10		T3	5
valid_sources[0x33]	1818880	1			T1	109		T2	10		T3	7
valid_sources[0x34]	949881	1			T1	157		T2	6		T3	6
valid_sources[0x35]	961147	1			T1	112		T2	13		T3	10
valid_sources[0x36]	971723	1			T1	134		T2	3		T3	3
valid_sources[0x37]	944138	1			T1	197		T2	10		T3	4
valid_sources[0x38]	1847514	1			T1	168		T2	4		T3	5
valid_sources[0x39]	1632570	1			T1	163		T2	14		T3	12
valid_sources[0x3a]	940983	1			T1	145		T2	6		T3	8
valid_sources[0x3b]	1610419	1			T1	160		T2	8		T3	9
valid_sources[0x3c]	937582	1			T1	102		T2	7		T3	6
valid_sources[0x3d]	942230	1			T1	152		T2	5		T3	5
valid_sources[0x3e]	949313	1			T1	80		T2	3		T3	7
valid_sources[0x3f]	981576	1			T1	100		T2	6		T3	13
valid_sources[0x40]	948666	1			T1	163		T2	8		T3	8
valid_sources[0x41]	951857	1			T1	211		T2	6		T3	8
valid_sources[0x42]	950358	1			T1	172		T2	2		T3	9
valid_sources[0x43]	968089	1			T1	142		T2	10		T3	9
valid_sources[0x44]	946712	1			T1	169		T2	3		T3	4
valid_sources[0x45]	1113788	1			T1	169		T2	8		T3	2
valid_sources[0x46]	937753	1			T1	118		T2	11		T3	8
valid_sources[0x47]	2977052	1			T1	170		T2	12		T3	1
valid_sources[0x48]	988498	1			T1	157		T2	7		T3	10
valid_sources[0x49]	942128	1			T1	108		T2	3		T3	2
valid_sources[0x4a]	945313	1			T1	164		T2	6		T3	11
valid_sources[0x4b]	2257652	1			T1	149		T2	12		T3	5
valid_sources[0x4c]	1112097	1			T1	110		T2	5		T3	7
valid_sources[0x4d]	986312	1			T1	165		T2	11		T3	7
valid_sources[0x4e]	1033595	1			T1	107		T2	5		T3	8
valid_sources[0x4f]	1144418	1			T1	176		T2	13		T3	9
valid_sources[0x50]	1861938	1			T1	208		T2	7		T3	6
valid_sources[0x51]	941190	1			T1	136		T2	4		T3	6
valid_sources[0x52]	942580	1			T1	161		T2	3		T3	8
valid_sources[0x53]	946744	1			T1	128		T2	7		T3	2
valid_sources[0x54]	938258	1			T1	156		T2	6		T3	4
valid_sources[0x55]	1017476	1			T1	126		T2	9		T3	2
valid_sources[0x56]	945791	1			T1	105		T2	8		T3	7
valid_sources[0x57]	941201	1			T1	145		T2	5		T3	14
valid_sources[0x58]	939815	1			T1	124		T2	8		T3	15
valid_sources[0x59]	1408868	1			T1	121		T2	13		T3	8
valid_sources[0x5a]	952607	1			T1	117		T2	10		T3	8
valid_sources[0x5b]	941361	1			T1	100		T2	5		T3	16
valid_sources[0x5c]	1186628	1			T1	175		T2	12		T3	14
valid_sources[0x5d]	946068	1			T1	149		T2	11		T3	7
valid_sources[0x5e]	1017617	1			T1	93		T2	11		T3	11
valid_sources[0x5f]	1853471	1			T1	167		T2	5		T3	11
valid_sources[0x60]	1609113	1			T1	179		T2	6		T3	21
valid_sources[0x61]	941865	1			T1	164		T2	4		T3	2
valid_sources[0x62]	1601565	1			T1	137		T2	9		T3	2
valid_sources[0x63]	1055939	1			T1	142		T2	10		T3	9
valid_sources[0x64]	936402	1			T1	166		T2	9		T3	3
valid_sources[0x65]	951470	1			T1	148		T2	6		T3	4
valid_sources[0x66]	1050079	1			T1	94		T2	8		T3	3
valid_sources[0x67]	941133	1			T1	137		T2	4		T3	2
valid_sources[0x68]	971662	1			T1	145		T2	12		T3	6
valid_sources[0x69]	949588	1			T1	88		T2	11		T3	14
valid_sources[0x6a]	939508	1			T1	164		T2	13		T3	7
valid_sources[0x6b]	1598900	1			T1	186		T2	7		T3	13
valid_sources[0x6c]	1072863	1			T1	162		T2	6		T3	8
valid_sources[0x6d]	944251	1			T1	129		T2	7		T3	12
valid_sources[0x6e]	939762	1			T1	121		T2	7		T3	5
valid_sources[0x6f]	937571	1			T1	135		T2	11		T3	8
valid_sources[0x70]	942624	1			T1	153		T2	14		T3	10
valid_sources[0x71]	943723	1			T1	151		T2	4		T3	4
valid_sources[0x72]	943088	1			T1	144		T2	12		T3	13
valid_sources[0x73]	941572	1			T1	143		T2	6		T3	9
valid_sources[0x74]	943738	1			T1	130		T2	6		T3	9
valid_sources[0x75]	955345	1			T1	154		T2	8		T3	13
valid_sources[0x76]	940998	1			T1	181		T2	10		T3	10
valid_sources[0x77]	939490	1			T1	135		T2	3		T3	17
valid_sources[0x78]	956174	1			T1	144		T2	8		T3	4
valid_sources[0x79]	947981	1			T1	147		T2	6		T3	5
valid_sources[0x7a]	982358	1			T1	149		T2	9		T3	16
valid_sources[0x7b]	940443	1			T1	178		T2	9		T3	10
valid_sources[0x7c]	975210	1			T1	138		T2	5		T3	9
valid_sources[0x7d]	972032	1			T1	156		T2	13		T3	11
valid_sources[0x7e]	943236	1			T1	191		T2	13		T3	11
valid_sources[0x7f]	1079608	1			T1	104		T2	11		T3	11
valid_sources[0x80]	940984	1			T1	144		T2	4		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58683381

1

T1

17269

T2

704

T3

689

values[0x0]

all_enables

biggest_size

41285680

1

T1

3443

T2

352

T3

356

values[0x1]

all_enables

biggest_size

35719375

1

T1

3044

T2

369

T3

353