Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

167648182

1

T1

14001

T2

715

T3

682

full_word

135757255

1

T1

23756

T2

1425

T3

1398

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	303405147	1			T1	37757		T2	2140		T3	2080
auto[TlIntgErrCmd]	112	1			T102	2		T103	4		T104	6
auto[TlIntgErrData]	90	1			T102	5		T103	3		T104	2
auto[TlIntgErrBoth]	88	1			T102	3		T103	3		T104	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159196683

1

T1

25617

T2

1113

T3

1085

auto[1]

144208754

1

T1

12140

T2

1027

T3

995

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	100493825	1			T1	8348		T2	409		T3	396
auto[TlIntgErrNone]	partial	auto[1]	67154093	1			T1	5653		T2	306		T3	286
auto[TlIntgErrNone]	full_word	auto[0]	58702726	1			T1	17269		T2	704		T3	689
auto[TlIntgErrNone]	full_word	auto[1]	77054503	1			T1	6487		T2	721		T3	709
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T102	2		T103	1		T104	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T103	3		T104	1		T150	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T104	2		T154	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T150	1		T151	1		T153	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T102	4		T103	1		T150	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T102	1		T103	2		T104	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T104	1		T151	1		T155	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T154	1		T156	1		T157	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T102	1		T103	1		T104	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T102	2		T103	2		T150	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T158	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T153	1		T159	1		-	-