Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1387029828	198405	0	0
RunThenComplete_M	1387029828	2200622	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1387029828	198405	0	0
T1	263676	33	0	0
T2	16465	9	0	0
T3	5924	9	0	0
T13	166746	71	0	0
T14	304974	81	0	0
T15	466880	47	0	0
T16	6248	9	0	0
T17	615764	374	0	0
T18	82292	16	0	0
T19	168654	17	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1387029828	2200622	0	0
T1	263676	178	0	0
T2	16465	31	0	0
T3	5924	31	0	0
T13	166746	332	0	0
T14	304974	469	0	0
T15	466880	273	0	0
T16	6248	31	0	0
T17	615764	5526	0	0
T18	82292	48	0	0
T19	168654	75	0	0