Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1388408575	195880	0	0
entropy_period_rd_A	1388408575	2562	0	0
intr_enable_rd_A	1388408575	3244	0	0
prefix_0_rd_A	1388408575	2319	0	0
prefix_10_rd_A	1388408575	2311	0	0
prefix_1_rd_A	1388408575	2455	0	0
prefix_2_rd_A	1388408575	2266	0	0
prefix_3_rd_A	1388408575	2322	0	0
prefix_4_rd_A	1388408575	2348	0	0
prefix_5_rd_A	1388408575	2080	0	0
prefix_6_rd_A	1388408575	2278	0	0
prefix_7_rd_A	1388408575	2308	0	0
prefix_8_rd_A	1388408575	2224	0	0
prefix_9_rd_A	1388408575	2320	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	195880	0	0
T9	4130	0	0	0
T51	580609	78838	0	0
T52	0	61196	0	0
T53	0	53241	0	0
T108	0	192	0	0
T109	0	5	0	0
T111	0	3	0	0
T112	0	239	0	0
T113	0	194	0	0
T114	4730	0	0	0
T115	236568	0	0	0
T116	963620	0	0	0
T117	29241	0	0	0
T118	791425	0	0	0
T119	174662	0	0	0
T120	538445	0	0	0
T121	2712	0	0	0
T122	0	6	0	0
T133	0	9	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2562	0	0
T88	5682	41	0	0
T102	11957	58	0	0
T109	7904	30	0	0
T110	4689	12	0	0
T122	6825	10	0	0
T134	1689	2	0	0
T135	26683	175	0	0
T136	3316	13	0	0
T137	2855	2	0	0
T138	3012	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	3244	0	0
T88	5682	68	0	0
T102	11957	86	0	0
T105	1303	14	0	0
T106	1557	17	0	0
T107	2163	13	0	0
T109	7904	17	0	0
T110	4689	12	0	0
T135	26683	223	0	0
T139	2673	13	0	0
T140	2251	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2319	0	0
T88	5682	25	0	0
T98	2433	4	0	0
T102	11957	62	0	0
T109	7904	10	0	0
T110	4689	7	0	0
T122	6825	2	0	0
T135	26683	183	0	0
T136	3316	7	0	0
T137	2855	2	0	0
T138	3012	12	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2311	0	0
T88	5682	32	0	0
T98	2433	9	0	0
T102	11957	48	0	0
T109	7904	13	0	0
T110	4689	11	0	0
T122	6825	6	0	0
T134	1689	1	0	0
T135	26683	198	0	0
T136	3316	3	0	0
T138	3012	10	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2455	0	0
T88	5682	34	0	0
T98	2433	7	0	0
T102	11957	49	0	0
T109	7904	18	0	0
T110	4689	11	0	0
T122	6825	10	0	0
T135	26683	218	0	0
T136	3316	8	0	0
T137	2855	7	0	0
T138	3012	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2266	0	0
T88	5682	33	0	0
T98	2433	3	0	0
T102	11957	50	0	0
T109	7904	14	0	0
T110	4689	6	0	0
T122	6825	7	0	0
T135	26683	203	0	0
T136	3316	7	0	0
T137	2855	1	0	0
T138	3012	14	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2322	0	0
T88	5682	29	0	0
T98	2433	6	0	0
T102	11957	43	0	0
T109	7904	18	0	0
T110	4689	4	0	0
T122	6825	3	0	0
T135	26683	190	0	0
T136	3316	6	0	0
T138	3012	7	0	0
T141	7590	48	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2348	0	0
T88	5682	28	0	0
T98	2433	3	0	0
T102	11957	35	0	0
T109	7904	29	0	0
T110	4689	2	0	0
T122	6825	17	0	0
T134	1689	7	0	0
T135	26683	200	0	0
T136	3316	7	0	0
T138	3012	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2080	0	0
T88	5682	11	0	0
T102	11957	34	0	0
T109	7904	10	0	0
T110	4689	11	0	0
T122	6825	11	0	0
T134	1689	1	0	0
T135	26683	188	0	0
T136	3316	10	0	0
T137	2855	4	0	0
T138	3012	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2278	0	0
T88	5682	28	0	0
T98	2433	3	0	0
T102	11957	52	0	0
T109	7904	15	0	0
T110	4689	15	0	0
T122	6825	8	0	0
T135	26683	198	0	0
T136	3316	11	0	0
T137	2855	11	0	0
T141	7590	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2308	0	0
T88	5682	34	0	0
T102	11957	35	0	0
T109	7904	19	0	0
T110	4689	17	0	0
T122	6825	3	0	0
T134	1689	3	0	0
T135	26683	214	0	0
T136	3316	8	0	0
T138	3012	9	0	0
T141	7590	28	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2224	0	0
T88	5682	25	0	0
T102	11957	60	0	0
T109	7904	13	0	0
T110	4689	12	0	0
T122	6825	4	0	0
T134	1689	7	0	0
T135	26683	238	0	0
T136	3316	7	0	0
T137	2855	3	0	0
T138	3012	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388408575	2320	0	0
T88	5682	33	0	0
T102	11957	29	0	0
T109	7904	17	0	0
T110	4689	8	0	0
T122	6825	16	0	0
T134	1689	4	0	0
T135	26683	188	0	0
T136	3316	8	0	0
T137	2855	11	0	0
T138	3012	2	0	0