Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	80769242	1			T1	1359		T2	162516		T3	2838
all_values[1]	80769242	1			T1	1359		T2	162516		T3	2838
all_values[2]	80769242	1			T1	1359		T2	162516		T3	2838

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

512084

1

T1

45

T2

23

T3

68

auto[1]

241795642

1

T1

4032

T2

487525

T3

8446

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241085028

1

T1

3441

T2

486111

T3

7698

auto[1]

1222698

1

T1

636

T2

1437

T3

816

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	187139	1			T1	27		T3	52		T15	1
all_values[0]	auto[0]	auto[1]	2083	1			T1	6		T3	8		T15	2
all_values[0]	auto[1]	auto[0]	80174537	1			T1	1120		T2	162037		T3	2514
all_values[0]	auto[1]	auto[1]	405483	1			T1	206		T2	479		T3	264
all_values[1]	auto[0]	auto[0]	168370	1			T1	10		T2	4		T12	7
all_values[1]	auto[0]	auto[1]	1496	1			T1	2		T2	3		T12	1
all_values[1]	auto[1]	auto[0]	80193306	1			T1	1137		T2	162033		T3	2566
all_values[1]	auto[1]	auto[1]	406070	1			T1	210		T2	476		T3	272
all_values[2]	auto[0]	auto[0]	151414	1			T2	10		T3	6		T13	7
all_values[2]	auto[0]	auto[1]	1582	1			T2	6		T3	2		T13	4
all_values[2]	auto[1]	auto[0]	80210262	1			T1	1147		T2	162027		T3	2560
all_values[2]	auto[1]	auto[1]	405984	1			T1	212		T2	473		T3	270