Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 290704 | 1 |  |  | T1 | 266 |  | T2 | 2 |  | T3 | 356 | 
| auto[1] | 268450 | 1 |  |  | T2 | 618 |  | T12 | 16 |  | T14 | 16 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 140287 | 1 |  |  | T1 | 66 |  | T2 | 150 |  | T3 | 88 | 
| lower_val | 138209 | 1 |  |  | T1 | 62 |  | T2 | 142 |  | T3 | 88 | 
| zero_val | 1689 | 1 |  |  | T1 | 1 |  | T2 | 1 |  | T3 | 1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 279902 | 1 |  |  | T1 | 136 |  | T2 | 302 |  | T3 | 164 | 
| lower_val | 279244 | 1 |  |  | T1 | 130 |  | T2 | 318 |  | T3 | 192 | 
| zero_val | 8 | 1 |  |  | T166 | 2 |  | T167 | 2 |  | T168 | 2 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 18 | 4 | 14 | 77.78 | 4 | 
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| [zero_val] | [zero_val] | * | -- | -- | 2 |  | 
Uncovered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| [higher_val] | [zero_val] | [auto[0]] | 0 | 1 | 1 |  | 
| [lower_val] | [zero_val] | [auto[1]] | 0 | 1 | 1 |  | 
Covered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | higher_val | auto[0] | 36347 | 1 |  |  | T1 | 26 |  | T3 | 37 |  | T12 | 1 | 
| higher_val | higher_val | auto[1] | 34111 | 1 |  |  | T2 | 70 |  | T12 | 3 |  | T14 | 3 | 
| higher_val | lower_val | auto[0] | 36427 | 1 |  |  | T1 | 40 |  | T2 | 1 |  | T3 | 51 | 
| higher_val | lower_val | auto[1] | 33400 | 1 |  |  | T2 | 79 |  | T14 | 2 |  | T18 | 521 | 
| higher_val | zero_val | auto[1] | 2 | 1 |  |  | T167 | 1 |  | T168 | 1 |  | - | - | 
| lower_val | higher_val | auto[0] | 35707 | 1 |  |  | T1 | 35 |  | T3 | 40 |  | T13 | 84 | 
| lower_val | higher_val | auto[1] | 33174 | 1 |  |  | T2 | 66 |  | T12 | 2 |  | T14 | 1 | 
| lower_val | lower_val | auto[0] | 35969 | 1 |  |  | T1 | 27 |  | T3 | 48 |  | T13 | 80 | 
| lower_val | lower_val | auto[1] | 33358 | 1 |  |  | T2 | 76 |  | T12 | 2 |  | T18 | 572 | 
| lower_val | zero_val | auto[0] | 1 | 1 |  |  | T166 | 1 |  | - | - |  | - | - | 
| zero_val | higher_val | auto[0] | 642 | 1 |  |  | T12 | 1 |  | T13 | 1 |  | T14 | 1 | 
| zero_val | higher_val | auto[1] | 209 | 1 |  |  | T18 | 5 |  | T70 | 1 |  | T169 | 1 | 
| zero_val | lower_val | auto[0] | 635 | 1 |  |  | T1 | 1 |  | T2 | 1 |  | T3 | 1 | 
| zero_val | lower_val | auto[1] | 203 | 1 |  |  | T18 | 1 |  | T32 | 1 |  | T70 | 1 |