Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	80769242	1			T1	1359		T2	162516		T3	2838
all_pins[1]	80769242	1			T1	1359		T2	162516		T3	2838
all_pins[2]	80769242	1			T1	1359		T2	162516		T3	2838

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	241588475	1			T1	3871		T2	487069		T3	8250
values[0x1]	719251	1			T1	206		T2	479		T3	264
transitions[0x0=>0x1]	717278	1			T1	206		T2	479		T3	264
transitions[0x1=>0x0]	717300	1			T1	206		T2	479		T3	264

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80363759	1			T1	1153		T2	162037		T3	2574
all_pins[0]	values[0x1]	405483	1			T1	206		T2	479		T3	264
all_pins[0]	transitions[0x0=>0x1]	405472	1			T1	206		T2	479		T3	264
all_pins[0]	transitions[0x1=>0x0]	45	1			T185	4		T186	2		T187	2
all_pins[1]	values[0x0]	80769186	1			T1	1359		T2	162516		T3	2838
all_pins[1]	values[0x1]	56	1			T185	4		T186	2		T187	2
all_pins[1]	transitions[0x0=>0x1]	41	1			T185	4		T186	2		T187	2
all_pins[1]	transitions[0x1=>0x0]	313697	1			T16	227		T25	11877		T26	4526
all_pins[2]	values[0x0]	80455530	1			T1	1359		T2	162516		T3	2838
all_pins[2]	values[0x1]	313712	1			T16	227		T25	11877		T26	4526
all_pins[2]	transitions[0x0=>0x1]	311765	1			T16	227		T25	11793		T26	4495
all_pins[2]	transitions[0x1=>0x0]	403558	1			T1	206		T2	479		T3	264