Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	623	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5072	1			T3	35		T23	3		T42	19
len_601_800	11481	1			T3	56		T16	6		T23	5
len_401_600	7639	1			T3	42		T23	6		T42	33
len_201_400	16002	1			T3	21		T16	2		T17	251
len_65_200	54499	1			T1	69		T3	13		T17	680
len_min_for_xof_require_squeeze	744	1			T1	1		T3	1		T17	10
len_keccak_block_sizes[72]	528	1			T1	1		T3	1		T17	5
len_keccak_block_sizes[104]	510	1			T17	5		T18	5		T32	1
len_keccak_block_sizes[136]	507	1			T1	2		T17	5		T18	5
len_keccak_block_sizes[144]	273	1			T1	1		T3	1		T17	5
len_keccak_block_sizes[168]	277	1			T1	1		T3	1		T17	5
len_datapath_width	13761	1			T1	8		T3	1		T12	3
len_2_63	169516	1			T1	56		T2	310		T3	8
len_1	51	1			T42	1		T55	1		T77	1