Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
275829 |
1 |
|
|
T1 |
132 |
|
T2 |
300 |
|
T3 |
175 |
auto[1] |
3806 |
1 |
|
|
T16 |
1 |
|
T23 |
7 |
|
T20 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
243911 |
1 |
|
|
T1 |
46 |
|
T2 |
300 |
|
T3 |
56 |
auto[1] |
35724 |
1 |
|
|
T1 |
86 |
|
T3 |
119 |
|
T12 |
9 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
265755 |
1 |
|
|
T1 |
132 |
|
T2 |
300 |
|
T3 |
175 |
auto[1] |
13880 |
1 |
|
|
T16 |
4 |
|
T23 |
11 |
|
T20 |
1 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13880 |
1 |
|
|
T16 |
4 |
|
T23 |
11 |
|
T20 |
1 |
sw_kmac_invalid_sideload |
265755 |
1 |
|
|
T1 |
132 |
|
T2 |
300 |
|
T3 |
175 |
app_valid_sideload |
13880 |
1 |
|
|
T16 |
4 |
|
T23 |
11 |
|
T20 |
1 |
app_invalid_sideload |
265755 |
1 |
|
|
T1 |
132 |
|
T2 |
300 |
|
T3 |
175 |