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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.29 95.89 92.30 100.00 68.60 94.11 98.84 96.29


Total test records in report: 1209
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T99 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1353695993 Aug 08 05:40:59 PM PDT 24 Aug 08 05:41:02 PM PDT 24 1260616606 ps
T122 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.126766286 Aug 08 05:41:14 PM PDT 24 Aug 08 05:41:17 PM PDT 24 94214682 ps
T100 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2091810326 Aug 08 05:41:27 PM PDT 24 Aug 08 05:41:28 PM PDT 24 101175545 ps
T1047 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.484901025 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:13 PM PDT 24 25972066 ps
T123 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1313518649 Aug 08 05:41:33 PM PDT 24 Aug 08 05:41:37 PM PDT 24 356322381 ps
T163 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.46123703 Aug 08 05:41:03 PM PDT 24 Aug 08 05:41:04 PM PDT 24 63480085 ps
T127 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2129076366 Aug 08 05:41:01 PM PDT 24 Aug 08 05:41:03 PM PDT 24 25744987 ps
T128 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3222783704 Aug 08 05:41:35 PM PDT 24 Aug 08 05:41:37 PM PDT 24 81993060 ps
T1048 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3336502854 Aug 08 05:41:30 PM PDT 24 Aug 08 05:41:31 PM PDT 24 924631370 ps
T142 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2881050209 Aug 08 05:41:14 PM PDT 24 Aug 08 05:41:15 PM PDT 24 47480365 ps
T1049 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.907049968 Aug 08 05:41:03 PM PDT 24 Aug 08 05:41:04 PM PDT 24 13511019 ps
T101 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3522890156 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:28 PM PDT 24 143429357 ps
T1050 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3593727198 Aug 08 05:41:14 PM PDT 24 Aug 08 05:41:15 PM PDT 24 16284428 ps
T1051 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3326030337 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:19 PM PDT 24 25819333 ps
T103 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.702688668 Aug 08 05:41:06 PM PDT 24 Aug 08 05:41:08 PM PDT 24 30965382 ps
T102 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1068549128 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:26 PM PDT 24 58128443 ps
T107 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3520091319 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:20 PM PDT 24 555208407 ps
T104 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1896020506 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:14 PM PDT 24 34359150 ps
T108 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3652590841 Aug 08 05:41:05 PM PDT 24 Aug 08 05:41:06 PM PDT 24 28390859 ps
T174 /workspace/coverage/cover_reg_top/14.kmac_intr_test.1672362082 Aug 08 05:41:28 PM PDT 24 Aug 08 05:41:29 PM PDT 24 12638976 ps
T129 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1481978483 Aug 08 05:41:14 PM PDT 24 Aug 08 05:41:17 PM PDT 24 67744188 ps
T109 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3563579592 Aug 08 05:41:01 PM PDT 24 Aug 08 05:41:03 PM PDT 24 106148729 ps
T149 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.4263938648 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:26 PM PDT 24 61961527 ps
T110 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.53644397 Aug 08 05:41:25 PM PDT 24 Aug 08 05:41:26 PM PDT 24 25842236 ps
T130 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1626875965 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:25 PM PDT 24 21906132 ps
T1052 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.17845427 Aug 08 05:41:14 PM PDT 24 Aug 08 05:41:22 PM PDT 24 554399115 ps
T131 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2982568909 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:02 PM PDT 24 80737842 ps
T164 /workspace/coverage/cover_reg_top/4.kmac_intr_test.515905853 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:14 PM PDT 24 20037475 ps
T1053 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.4135278467 Aug 08 05:40:59 PM PDT 24 Aug 08 05:41:00 PM PDT 24 176111771 ps
T1054 /workspace/coverage/cover_reg_top/48.kmac_intr_test.62533099 Aug 08 05:41:45 PM PDT 24 Aug 08 05:41:46 PM PDT 24 31329336 ps
T111 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.612509826 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:19 PM PDT 24 186347102 ps
T165 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.56194924 Aug 08 05:41:33 PM PDT 24 Aug 08 05:41:34 PM PDT 24 118149370 ps
T1055 /workspace/coverage/cover_reg_top/8.kmac_intr_test.3089950916 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:16 PM PDT 24 38259377 ps
T181 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.662416949 Aug 08 05:41:23 PM PDT 24 Aug 08 05:41:26 PM PDT 24 167995749 ps
T141 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2813805159 Aug 08 05:41:30 PM PDT 24 Aug 08 05:41:33 PM PDT 24 385120818 ps
T1056 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2296745199 Aug 08 05:41:22 PM PDT 24 Aug 08 05:41:23 PM PDT 24 148693669 ps
T150 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.80579057 Aug 08 05:41:27 PM PDT 24 Aug 08 05:41:30 PM PDT 24 97955920 ps
T1057 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3192813053 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:20 PM PDT 24 275768434 ps
T175 /workspace/coverage/cover_reg_top/0.kmac_intr_test.579332399 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:01 PM PDT 24 42816221 ps
T151 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3672074929 Aug 08 05:41:30 PM PDT 24 Aug 08 05:41:33 PM PDT 24 506363610 ps
T152 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2033384140 Aug 08 05:41:16 PM PDT 24 Aug 08 05:41:18 PM PDT 24 141762532 ps
T1058 /workspace/coverage/cover_reg_top/45.kmac_intr_test.855678181 Aug 08 05:41:45 PM PDT 24 Aug 08 05:41:46 PM PDT 24 13982801 ps
T1059 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3814730193 Aug 08 05:41:03 PM PDT 24 Aug 08 05:41:05 PM PDT 24 44727421 ps
T1060 /workspace/coverage/cover_reg_top/47.kmac_intr_test.897220953 Aug 08 05:41:47 PM PDT 24 Aug 08 05:41:48 PM PDT 24 15721454 ps
T1061 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1789497045 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:14 PM PDT 24 34363467 ps
T1062 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.2552596439 Aug 08 05:41:05 PM PDT 24 Aug 08 05:41:06 PM PDT 24 70998227 ps
T1063 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.324846189 Aug 08 05:41:33 PM PDT 24 Aug 08 05:41:35 PM PDT 24 158797287 ps
T1064 /workspace/coverage/cover_reg_top/13.kmac_intr_test.304765534 Aug 08 05:41:26 PM PDT 24 Aug 08 05:41:27 PM PDT 24 11979296 ps
T1065 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2115681079 Aug 08 05:40:59 PM PDT 24 Aug 08 05:41:00 PM PDT 24 15931975 ps
T1066 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4020482173 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:16 PM PDT 24 389645192 ps
T1067 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2857955294 Aug 08 05:41:02 PM PDT 24 Aug 08 05:41:04 PM PDT 24 251173018 ps
T179 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2521007738 Aug 08 05:41:18 PM PDT 24 Aug 08 05:41:22 PM PDT 24 99007399 ps
T1068 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.4129789459 Aug 08 05:41:14 PM PDT 24 Aug 08 05:41:15 PM PDT 24 36548843 ps
T1069 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1014613170 Aug 08 05:41:26 PM PDT 24 Aug 08 05:41:29 PM PDT 24 159207243 ps
T176 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1009799167 Aug 08 05:41:29 PM PDT 24 Aug 08 05:41:32 PM PDT 24 1622635263 ps
T1070 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2976441851 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:19 PM PDT 24 91766752 ps
T1071 /workspace/coverage/cover_reg_top/9.kmac_intr_test.2199722512 Aug 08 05:41:18 PM PDT 24 Aug 08 05:41:19 PM PDT 24 34320936 ps
T1072 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.105809184 Aug 08 05:41:26 PM PDT 24 Aug 08 05:41:28 PM PDT 24 124219426 ps
T1073 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3531406132 Aug 08 05:41:04 PM PDT 24 Aug 08 05:41:05 PM PDT 24 66858193 ps
T1074 /workspace/coverage/cover_reg_top/22.kmac_intr_test.1325310688 Aug 08 05:41:35 PM PDT 24 Aug 08 05:41:36 PM PDT 24 16529458 ps
T1075 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.4220456333 Aug 08 05:40:59 PM PDT 24 Aug 08 05:41:01 PM PDT 24 37256988 ps
T1076 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.815580656 Aug 08 05:41:31 PM PDT 24 Aug 08 05:41:32 PM PDT 24 17355854 ps
T1077 /workspace/coverage/cover_reg_top/49.kmac_intr_test.2563883653 Aug 08 05:41:46 PM PDT 24 Aug 08 05:41:46 PM PDT 24 15454192 ps
T1078 /workspace/coverage/cover_reg_top/12.kmac_intr_test.3302753317 Aug 08 05:41:28 PM PDT 24 Aug 08 05:41:29 PM PDT 24 32112027 ps
T105 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.143889316 Aug 08 05:41:29 PM PDT 24 Aug 08 05:41:31 PM PDT 24 138373434 ps
T1079 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.67471221 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:19 PM PDT 24 110313887 ps
T1080 /workspace/coverage/cover_reg_top/11.kmac_intr_test.1438271521 Aug 08 05:41:22 PM PDT 24 Aug 08 05:41:23 PM PDT 24 23200256 ps
T1081 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1272763783 Aug 08 05:41:01 PM PDT 24 Aug 08 05:41:03 PM PDT 24 170392998 ps
T1082 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1911866449 Aug 08 05:41:03 PM PDT 24 Aug 08 05:41:11 PM PDT 24 149893769 ps
T1083 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2266358890 Aug 08 05:41:29 PM PDT 24 Aug 08 05:41:32 PM PDT 24 95766268 ps
T1084 /workspace/coverage/cover_reg_top/39.kmac_intr_test.1556050521 Aug 08 05:41:45 PM PDT 24 Aug 08 05:41:46 PM PDT 24 206969939 ps
T1085 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2399245700 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:16 PM PDT 24 84078978 ps
T1086 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3124240732 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:26 PM PDT 24 26073019 ps
T106 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2949889050 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:14 PM PDT 24 86171185 ps
T112 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.545220884 Aug 08 05:41:28 PM PDT 24 Aug 08 05:41:30 PM PDT 24 221717700 ps
T1087 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3397334970 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:26 PM PDT 24 132535568 ps
T1088 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2727497364 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:16 PM PDT 24 18978562 ps
T1089 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1383299689 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:11 PM PDT 24 524540518 ps
T1090 /workspace/coverage/cover_reg_top/18.kmac_intr_test.3106415339 Aug 08 05:41:32 PM PDT 24 Aug 08 05:41:33 PM PDT 24 34369245 ps
T1091 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.891470756 Aug 08 05:41:16 PM PDT 24 Aug 08 05:41:19 PM PDT 24 223923896 ps
T1092 /workspace/coverage/cover_reg_top/20.kmac_intr_test.3862978007 Aug 08 05:41:35 PM PDT 24 Aug 08 05:41:36 PM PDT 24 11229121 ps
T1093 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3951868240 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:09 PM PDT 24 455324495 ps
T1094 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3014477495 Aug 08 05:41:23 PM PDT 24 Aug 08 05:41:24 PM PDT 24 70789519 ps
T1095 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.857177999 Aug 08 05:41:26 PM PDT 24 Aug 08 05:41:28 PM PDT 24 48959205 ps
T1096 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1858729834 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:18 PM PDT 24 34843211 ps
T1097 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1881061766 Aug 08 05:41:32 PM PDT 24 Aug 08 05:41:36 PM PDT 24 707131365 ps
T1098 /workspace/coverage/cover_reg_top/43.kmac_intr_test.696695061 Aug 08 05:41:41 PM PDT 24 Aug 08 05:41:42 PM PDT 24 21196717 ps
T1099 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.4152082606 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:20 PM PDT 24 146712616 ps
T1100 /workspace/coverage/cover_reg_top/1.kmac_intr_test.569314582 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:01 PM PDT 24 42485276 ps
T183 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3287918261 Aug 08 05:41:25 PM PDT 24 Aug 08 05:41:30 PM PDT 24 747129363 ps
T1101 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2997664417 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:14 PM PDT 24 589765592 ps
T1102 /workspace/coverage/cover_reg_top/21.kmac_intr_test.2086731979 Aug 08 05:41:34 PM PDT 24 Aug 08 05:41:34 PM PDT 24 31081878 ps
T1103 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.497058818 Aug 08 05:41:02 PM PDT 24 Aug 08 05:41:03 PM PDT 24 20044285 ps
T1104 /workspace/coverage/cover_reg_top/41.kmac_intr_test.1098833488 Aug 08 05:41:47 PM PDT 24 Aug 08 05:41:48 PM PDT 24 63220839 ps
T1105 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1537489444 Aug 08 05:41:29 PM PDT 24 Aug 08 05:41:31 PM PDT 24 54315459 ps
T1106 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1193308736 Aug 08 05:41:35 PM PDT 24 Aug 08 05:41:36 PM PDT 24 27918834 ps
T1107 /workspace/coverage/cover_reg_top/29.kmac_intr_test.2910650413 Aug 08 05:41:39 PM PDT 24 Aug 08 05:41:40 PM PDT 24 30623922 ps
T1108 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3495233918 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:26 PM PDT 24 39995102 ps
T1109 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1926822135 Aug 08 05:41:27 PM PDT 24 Aug 08 05:41:30 PM PDT 24 197269758 ps
T1110 /workspace/coverage/cover_reg_top/38.kmac_intr_test.3304399555 Aug 08 05:41:46 PM PDT 24 Aug 08 05:41:47 PM PDT 24 28905676 ps
T1111 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2704431338 Aug 08 05:41:25 PM PDT 24 Aug 08 05:41:27 PM PDT 24 473930954 ps
T1112 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.603381742 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:14 PM PDT 24 35565594 ps
T1113 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4227283464 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:33 PM PDT 24 4978790101 ps
T1114 /workspace/coverage/cover_reg_top/35.kmac_intr_test.3183696464 Aug 08 05:41:43 PM PDT 24 Aug 08 05:41:44 PM PDT 24 15073858 ps
T1115 /workspace/coverage/cover_reg_top/15.kmac_intr_test.91156554 Aug 08 05:41:28 PM PDT 24 Aug 08 05:41:29 PM PDT 24 38755175 ps
T1116 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.790622834 Aug 08 05:41:23 PM PDT 24 Aug 08 05:41:25 PM PDT 24 1073408182 ps
T188 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2259359794 Aug 08 05:41:11 PM PDT 24 Aug 08 05:41:14 PM PDT 24 135006291 ps
T1117 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3376220771 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:14 PM PDT 24 81878741 ps
T1118 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1076779602 Aug 08 05:41:28 PM PDT 24 Aug 08 05:41:30 PM PDT 24 233281958 ps
T1119 /workspace/coverage/cover_reg_top/28.kmac_intr_test.2764992516 Aug 08 05:41:40 PM PDT 24 Aug 08 05:41:41 PM PDT 24 27587712 ps
T143 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2029484222 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:02 PM PDT 24 35640664 ps
T1120 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2549727112 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:27 PM PDT 24 264012694 ps
T1121 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.951786798 Aug 08 05:41:29 PM PDT 24 Aug 08 05:41:30 PM PDT 24 21347845 ps
T1122 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.82022094 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:15 PM PDT 24 281409476 ps
T1123 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.65037409 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:17 PM PDT 24 454858945 ps
T1124 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3139203332 Aug 08 05:41:16 PM PDT 24 Aug 08 05:41:18 PM PDT 24 127040485 ps
T1125 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2008026173 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:15 PM PDT 24 203804190 ps
T1126 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3006214832 Aug 08 05:41:25 PM PDT 24 Aug 08 05:41:28 PM PDT 24 411058333 ps
T1127 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.896870605 Aug 08 05:41:28 PM PDT 24 Aug 08 05:41:30 PM PDT 24 35886928 ps
T1128 /workspace/coverage/cover_reg_top/30.kmac_intr_test.1497671470 Aug 08 05:41:41 PM PDT 24 Aug 08 05:41:42 PM PDT 24 14746370 ps
T144 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.95795989 Aug 08 05:41:03 PM PDT 24 Aug 08 05:41:05 PM PDT 24 179685917 ps
T1129 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2002325561 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:20 PM PDT 24 120795788 ps
T1130 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2175832894 Aug 08 05:41:19 PM PDT 24 Aug 08 05:41:20 PM PDT 24 170907727 ps
T1131 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3300205522 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:14 PM PDT 24 46028694 ps
T184 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2702147565 Aug 08 05:41:29 PM PDT 24 Aug 08 05:41:32 PM PDT 24 56275712 ps
T1132 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.4150203832 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:15 PM PDT 24 38701781 ps
T1133 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1380765947 Aug 08 05:41:01 PM PDT 24 Aug 08 05:41:20 PM PDT 24 1002897034 ps
T1134 /workspace/coverage/cover_reg_top/6.kmac_intr_test.263305198 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:18 PM PDT 24 37646841 ps
T189 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1014634226 Aug 08 05:41:03 PM PDT 24 Aug 08 05:41:05 PM PDT 24 52670737 ps
T1135 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.763456938 Aug 08 05:41:01 PM PDT 24 Aug 08 05:41:02 PM PDT 24 51270392 ps
T1136 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.585644360 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:26 PM PDT 24 50802933 ps
T1137 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1610669482 Aug 08 05:41:14 PM PDT 24 Aug 08 05:41:15 PM PDT 24 47643360 ps
T1138 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1742017226 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:19 PM PDT 24 538296254 ps
T1139 /workspace/coverage/cover_reg_top/17.kmac_intr_test.78875752 Aug 08 05:41:30 PM PDT 24 Aug 08 05:41:30 PM PDT 24 50765566 ps
T1140 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3133203816 Aug 08 05:41:16 PM PDT 24 Aug 08 05:41:17 PM PDT 24 139177303 ps
T1141 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.420035269 Aug 08 05:41:31 PM PDT 24 Aug 08 05:41:33 PM PDT 24 101403952 ps
T1142 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2046832398 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:14 PM PDT 24 120514007 ps
T1143 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.550109868 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:22 PM PDT 24 816670339 ps
T1144 /workspace/coverage/cover_reg_top/19.kmac_intr_test.2610472507 Aug 08 05:41:34 PM PDT 24 Aug 08 05:41:35 PM PDT 24 22077636 ps
T1145 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3759183501 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:02 PM PDT 24 31275793 ps
T1146 /workspace/coverage/cover_reg_top/24.kmac_intr_test.30071555 Aug 08 05:41:40 PM PDT 24 Aug 08 05:41:41 PM PDT 24 201075073 ps
T1147 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1704214860 Aug 08 05:41:16 PM PDT 24 Aug 08 05:41:17 PM PDT 24 106016902 ps
T1148 /workspace/coverage/cover_reg_top/26.kmac_intr_test.2276458144 Aug 08 05:41:34 PM PDT 24 Aug 08 05:41:35 PM PDT 24 80457107 ps
T180 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.8439163 Aug 08 05:41:31 PM PDT 24 Aug 08 05:41:36 PM PDT 24 368991822 ps
T1149 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3572557248 Aug 08 05:41:18 PM PDT 24 Aug 08 05:41:21 PM PDT 24 178033453 ps
T1150 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3818723178 Aug 08 05:41:19 PM PDT 24 Aug 08 05:41:21 PM PDT 24 59085039 ps
T1151 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3018720040 Aug 08 05:41:27 PM PDT 24 Aug 08 05:41:29 PM PDT 24 49177292 ps
T1152 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1457948592 Aug 08 05:40:59 PM PDT 24 Aug 08 05:41:00 PM PDT 24 22721007 ps
T1153 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3835050250 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:17 PM PDT 24 303537361 ps
T1154 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1856844695 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:14 PM PDT 24 94214792 ps
T1155 /workspace/coverage/cover_reg_top/10.kmac_intr_test.3439978789 Aug 08 05:41:18 PM PDT 24 Aug 08 05:41:19 PM PDT 24 27481367 ps
T1156 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1687305979 Aug 08 05:41:28 PM PDT 24 Aug 08 05:41:29 PM PDT 24 98823192 ps
T1157 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.411096402 Aug 08 05:41:35 PM PDT 24 Aug 08 05:41:38 PM PDT 24 295727135 ps
T1158 /workspace/coverage/cover_reg_top/40.kmac_intr_test.1638189655 Aug 08 05:41:45 PM PDT 24 Aug 08 05:41:46 PM PDT 24 15965488 ps
T1159 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.700817983 Aug 08 05:41:10 PM PDT 24 Aug 08 05:41:12 PM PDT 24 62764066 ps
T1160 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3316529042 Aug 08 05:41:02 PM PDT 24 Aug 08 05:41:05 PM PDT 24 47804931 ps
T1161 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2895508030 Aug 08 05:41:06 PM PDT 24 Aug 08 05:41:07 PM PDT 24 25004732 ps
T1162 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2347045720 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:19 PM PDT 24 81510166 ps
T1163 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1089913790 Aug 08 05:41:26 PM PDT 24 Aug 08 05:41:27 PM PDT 24 157930835 ps
T1164 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2147118631 Aug 08 05:41:26 PM PDT 24 Aug 08 05:41:28 PM PDT 24 71738297 ps
T1165 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3100800975 Aug 08 05:41:19 PM PDT 24 Aug 08 05:41:20 PM PDT 24 69930721 ps
T1166 /workspace/coverage/cover_reg_top/34.kmac_intr_test.56513241 Aug 08 05:41:39 PM PDT 24 Aug 08 05:41:40 PM PDT 24 43555805 ps
T1167 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1376355632 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:20 PM PDT 24 465482699 ps
T177 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.131247011 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:18 PM PDT 24 242061546 ps
T1168 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4204413703 Aug 08 05:41:18 PM PDT 24 Aug 08 05:41:21 PM PDT 24 138836225 ps
T1169 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.565605209 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:16 PM PDT 24 157003281 ps
T1170 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.257532572 Aug 08 05:41:26 PM PDT 24 Aug 08 05:41:28 PM PDT 24 151219747 ps
T145 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3271798499 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:16 PM PDT 24 32320387 ps
T1171 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2660184506 Aug 08 05:41:31 PM PDT 24 Aug 08 05:41:33 PM PDT 24 81987821 ps
T1172 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2723379985 Aug 08 05:41:16 PM PDT 24 Aug 08 05:41:18 PM PDT 24 57562268 ps
T1173 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2403378139 Aug 08 05:41:32 PM PDT 24 Aug 08 05:41:33 PM PDT 24 137527354 ps
T182 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.673740971 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:03 PM PDT 24 117313064 ps
T1174 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1016080761 Aug 08 05:41:16 PM PDT 24 Aug 08 05:41:18 PM PDT 24 93447775 ps
T1175 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1229892049 Aug 08 05:41:30 PM PDT 24 Aug 08 05:41:32 PM PDT 24 64646884 ps
T1176 /workspace/coverage/cover_reg_top/25.kmac_intr_test.2875959933 Aug 08 05:41:39 PM PDT 24 Aug 08 05:41:40 PM PDT 24 28714721 ps
T1177 /workspace/coverage/cover_reg_top/31.kmac_intr_test.402861801 Aug 08 05:41:41 PM PDT 24 Aug 08 05:41:42 PM PDT 24 77909332 ps
T1178 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2139370576 Aug 08 05:41:35 PM PDT 24 Aug 08 05:41:36 PM PDT 24 21694681 ps
T1179 /workspace/coverage/cover_reg_top/37.kmac_intr_test.863713433 Aug 08 05:41:45 PM PDT 24 Aug 08 05:41:46 PM PDT 24 13963577 ps
T1180 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.4134079580 Aug 08 05:41:06 PM PDT 24 Aug 08 05:41:21 PM PDT 24 1178220215 ps
T1181 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2081420789 Aug 08 05:41:34 PM PDT 24 Aug 08 05:41:36 PM PDT 24 48324640 ps
T1182 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1592031680 Aug 08 05:41:30 PM PDT 24 Aug 08 05:41:33 PM PDT 24 63476127 ps
T178 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2068271476 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:18 PM PDT 24 107835095 ps
T1183 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1711246899 Aug 08 05:41:25 PM PDT 24 Aug 08 05:41:27 PM PDT 24 41373329 ps
T1184 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.623312874 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:01 PM PDT 24 17576303 ps
T1185 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1420458850 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:17 PM PDT 24 38982829 ps
T1186 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1778737658 Aug 08 05:41:27 PM PDT 24 Aug 08 05:41:28 PM PDT 24 58307313 ps
T1187 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1736305653 Aug 08 05:41:44 PM PDT 24 Aug 08 05:41:45 PM PDT 24 11526228 ps
T1188 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.4132193995 Aug 08 05:41:13 PM PDT 24 Aug 08 05:41:17 PM PDT 24 506451495 ps
T1189 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1853530545 Aug 08 05:41:02 PM PDT 24 Aug 08 05:41:10 PM PDT 24 549163856 ps
T1190 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1746017182 Aug 08 05:41:01 PM PDT 24 Aug 08 05:41:02 PM PDT 24 144082152 ps
T1191 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2269015535 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:26 PM PDT 24 202823769 ps
T1192 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2649445937 Aug 08 05:41:00 PM PDT 24 Aug 08 05:41:03 PM PDT 24 705650640 ps
T1193 /workspace/coverage/cover_reg_top/7.kmac_intr_test.1760642190 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:13 PM PDT 24 46525610 ps
T1194 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2227476564 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:17 PM PDT 24 32494323 ps
T1195 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.4001978993 Aug 08 05:41:12 PM PDT 24 Aug 08 05:41:15 PM PDT 24 267377044 ps
T1196 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1711010338 Aug 08 05:41:16 PM PDT 24 Aug 08 05:41:17 PM PDT 24 100213731 ps
T1197 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1025918017 Aug 08 05:41:29 PM PDT 24 Aug 08 05:41:30 PM PDT 24 93106061 ps
T1198 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3034041418 Aug 08 05:41:26 PM PDT 24 Aug 08 05:41:27 PM PDT 24 77957005 ps
T1199 /workspace/coverage/cover_reg_top/32.kmac_intr_test.1877886306 Aug 08 05:41:33 PM PDT 24 Aug 08 05:41:34 PM PDT 24 54348686 ps
T1200 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.511817637 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:17 PM PDT 24 55978264 ps
T1201 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.4294323314 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:18 PM PDT 24 125538260 ps
T1202 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2470378571 Aug 08 05:41:19 PM PDT 24 Aug 08 05:41:21 PM PDT 24 155006155 ps
T1203 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2618898666 Aug 08 05:41:24 PM PDT 24 Aug 08 05:41:28 PM PDT 24 335928756 ps
T1204 /workspace/coverage/cover_reg_top/5.kmac_intr_test.3331845121 Aug 08 05:41:15 PM PDT 24 Aug 08 05:41:16 PM PDT 24 24462869 ps
T1205 /workspace/coverage/cover_reg_top/46.kmac_intr_test.1768316395 Aug 08 05:41:45 PM PDT 24 Aug 08 05:41:46 PM PDT 24 38383714 ps
T1206 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.95868737 Aug 08 05:41:18 PM PDT 24 Aug 08 05:41:22 PM PDT 24 251276839 ps
T1207 /workspace/coverage/cover_reg_top/33.kmac_intr_test.1204368724 Aug 08 05:41:40 PM PDT 24 Aug 08 05:41:41 PM PDT 24 162409638 ps
T1208 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2666443150 Aug 08 05:41:27 PM PDT 24 Aug 08 05:41:29 PM PDT 24 58394801 ps
T1209 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.994576135 Aug 08 05:41:17 PM PDT 24 Aug 08 05:41:19 PM PDT 24 76012541 ps

Test location /workspace/coverage/default/29.kmac_error.4121234594
Short name T16
Test name
Test status
Simulation time 622547978 ps
CPU time 16.22 seconds
Started Aug 08 06:24:35 PM PDT 24
Finished Aug 08 06:24:51 PM PDT 24
Peak memory 238380 kb
Host smart-a53ee5f4-0693-443e-9eb2-cc2520b6bcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121234594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.4121234594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.3190400166
Short name T28
Test name
Test status
Simulation time 10280175205 ps
CPU time 256.95 seconds
Started Aug 08 06:24:07 PM PDT 24
Finished Aug 08 06:28:24 PM PDT 24
Peak memory 457300 kb
Host smart-d1f1fe31-1835-4974-99f2-aae55a3abdb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190400166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3
190400166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1313518649
Short name T123
Test name
Test status
Simulation time 356322381 ps
CPU time 3.77 seconds
Started Aug 08 05:41:33 PM PDT 24
Finished Aug 08 05:41:37 PM PDT 24
Peak memory 215376 kb
Host smart-a210ee50-05ff-4f12-9a3c-ff893ec71bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313518649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1313
518649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.3899769804
Short name T6
Test name
Test status
Simulation time 9330102272 ps
CPU time 34.13 seconds
Started Aug 08 06:23:32 PM PDT 24
Finished Aug 08 06:24:06 PM PDT 24
Peak memory 253832 kb
Host smart-e0884ecd-dc00-452d-82ed-dab54f6e7c0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899769804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3899769804 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.1381925061
Short name T37
Test name
Test status
Simulation time 232501970709 ps
CPU time 555.71 seconds
Started Aug 08 06:22:58 PM PDT 24
Finished Aug 08 06:32:14 PM PDT 24
Peak memory 296788 kb
Host smart-1bf0b47d-b5e1-4c31-a118-cb895ef1144d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381925061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.1381925061 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.kmac_key_error.3525021728
Short name T22
Test name
Test status
Simulation time 614484767 ps
CPU time 3.92 seconds
Started Aug 08 06:23:47 PM PDT 24
Finished Aug 08 06:23:51 PM PDT 24
Peak memory 217644 kb
Host smart-bb6cb206-34dc-449e-93da-f7593998b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525021728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3525021728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.3706977675
Short name T18
Test name
Test status
Simulation time 958045829646 ps
CPU time 10116.4 seconds
Started Aug 08 06:24:18 PM PDT 24
Finished Aug 08 09:12:56 PM PDT 24
Peak memory 6521832 kb
Host smart-08f7c05e-e69e-49ec-934a-aef84d46a505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3706977675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3706977675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1410597008
Short name T97
Test name
Test status
Simulation time 166033178 ps
CPU time 1.85 seconds
Started Aug 08 06:23:25 PM PDT 24
Finished Aug 08 06:23:27 PM PDT 24
Peak memory 223864 kb
Host smart-432bc7ab-da33-4faf-9b07-8229f1b180cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410597008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1410597008 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.1363804008
Short name T7
Test name
Test status
Simulation time 44131549 ps
CPU time 1.32 seconds
Started Aug 08 06:23:15 PM PDT 24
Finished Aug 08 06:23:16 PM PDT 24
Peak memory 223836 kb
Host smart-83754dd9-1d14-4940-b594-f49c4242e914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363804008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1363804008 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.105809184
Short name T1072
Test name
Test status
Simulation time 124219426 ps
CPU time 2.26 seconds
Started Aug 08 05:41:26 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 223152 kb
Host smart-ea2d47c3-981b-4690-8908-b539a382c4c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105809184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac
_shadow_reg_errors_with_csr_rw.105809184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.2812163237
Short name T5
Test name
Test status
Simulation time 429499457 ps
CPU time 7.34 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:23:57 PM PDT 24
Peak memory 226472 kb
Host smart-0d828821-d386-4fdb-a405-da2108cc895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812163237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2812163237 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.1672362082
Short name T174
Test name
Test status
Simulation time 12638976 ps
CPU time 0.79 seconds
Started Aug 08 05:41:28 PM PDT 24
Finished Aug 08 05:41:29 PM PDT 24
Peak memory 206792 kb
Host smart-78bca61b-2a6b-4474-9acc-2c4c97d2be50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672362082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1672362082 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/default/0.kmac_stress_all.1432079326
Short name T26
Test name
Test status
Simulation time 46939423493 ps
CPU time 719.78 seconds
Started Aug 08 06:23:08 PM PDT 24
Finished Aug 08 06:35:07 PM PDT 24
Peak memory 436960 kb
Host smart-072f361f-93c0-4858-a246-aeab4fcde5c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1432079326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.1432079326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_error.2946615257
Short name T33
Test name
Test status
Simulation time 29499765934 ps
CPU time 490.07 seconds
Started Aug 08 06:25:35 PM PDT 24
Finished Aug 08 06:33:45 PM PDT 24
Peak memory 628964 kb
Host smart-24fd13dd-ce7b-4259-85f0-cdd9b1a12142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946615257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2946615257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_burst_write.2008322785
Short name T42
Test name
Test status
Simulation time 17475862655 ps
CPU time 657.87 seconds
Started Aug 08 06:24:58 PM PDT 24
Finished Aug 08 06:35:56 PM PDT 24
Peak memory 247956 kb
Host smart-155f5d8b-5df2-4ee2-930e-c7306d6a4213
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008322785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.200832278
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3522890156
Short name T101
Test name
Test status
Simulation time 143429357 ps
CPU time 3.08 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 223316 kb
Host smart-86bdad57-756f-4938-9432-3bc8bbc86bff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522890156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.3522890156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.kmac_alert_test.1176775767
Short name T76
Test name
Test status
Simulation time 77065205 ps
CPU time 0.75 seconds
Started Aug 08 06:23:10 PM PDT 24
Finished Aug 08 06:23:11 PM PDT 24
Peak memory 204092 kb
Host smart-7f0ebad0-15f1-47dd-8902-8962decfdca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176775767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1176775767 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2881050209
Short name T142
Test name
Test status
Simulation time 47480365 ps
CPU time 1.59 seconds
Started Aug 08 05:41:14 PM PDT 24
Finished Aug 08 05:41:15 PM PDT 24
Peak memory 215144 kb
Host smart-59d7df18-4c14-4138-90d5-5f8f57aad6d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881050209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.2881050209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.3545383184
Short name T83
Test name
Test status
Simulation time 50739278 ps
CPU time 1.94 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:23:37 PM PDT 24
Peak memory 218220 kb
Host smart-3f5cc85b-5832-4c4b-985d-6de11d9a5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545383184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3545383184 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.3562075799
Short name T60
Test name
Test status
Simulation time 525412163 ps
CPU time 1.34 seconds
Started Aug 08 06:24:12 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 219108 kb
Host smart-47d879d1-ae39-4a12-b874-7e69ecb60c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562075799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3562075799 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.2515538216
Short name T56
Test name
Test status
Simulation time 105535712801 ps
CPU time 2709.67 seconds
Started Aug 08 06:23:43 PM PDT 24
Finished Aug 08 07:08:54 PM PDT 24
Peak memory 599956 kb
Host smart-93a406c1-ecd4-4601-9b62-b9170b24c4d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515538216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.2515538216 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.kmac_smoke.789951981
Short name T1
Test name
Test status
Simulation time 1869161336 ps
CPU time 41.3 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:24:32 PM PDT 24
Peak memory 223992 kb
Host smart-6df4b49a-58ca-44c8-a3b2-4d7206d24ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789951981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.789951981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1068549128
Short name T102
Test name
Test status
Simulation time 58128443 ps
CPU time 0.93 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215344 kb
Host smart-9ff96773-f131-4de6-a75e-7d8fbc145667
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068549128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.1068549128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.579332399
Short name T175
Test name
Test status
Simulation time 42816221 ps
CPU time 0.76 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:01 PM PDT 24
Peak memory 206676 kb
Host smart-c50cc38e-cd9c-4c59-a730-749b9705a795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579332399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.579332399 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3185163455
Short name T45
Test name
Test status
Simulation time 17517945453 ps
CPU time 64.31 seconds
Started Aug 08 06:23:32 PM PDT 24
Finished Aug 08 06:24:36 PM PDT 24
Peak memory 219116 kb
Host smart-8d89076a-7217-4b9b-9be7-513aa518a77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185163455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3185163455 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.4005174397
Short name T168
Test name
Test status
Simulation time 429139206204 ps
CPU time 9491.56 seconds
Started Aug 08 06:25:24 PM PDT 24
Finished Aug 08 09:03:37 PM PDT 24
Peak memory 6324680 kb
Host smart-8a0dab69-fc67-42b0-8870-05a4ce80de02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4005174397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.4005174397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2521007738
Short name T179
Test name
Test status
Simulation time 99007399 ps
CPU time 3.83 seconds
Started Aug 08 05:41:18 PM PDT 24
Finished Aug 08 05:41:22 PM PDT 24
Peak memory 223456 kb
Host smart-a9d7f187-b731-4743-ac8b-2d99462aee8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521007738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2521
007738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2702147565
Short name T184
Test name
Test status
Simulation time 56275712 ps
CPU time 2.48 seconds
Started Aug 08 05:41:29 PM PDT 24
Finished Aug 08 05:41:32 PM PDT 24
Peak memory 215288 kb
Host smart-75cff5d7-03a6-4222-b561-6a95eba01847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702147565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2702
147565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1009799167
Short name T176
Test name
Test status
Simulation time 1622635263 ps
CPU time 2.67 seconds
Started Aug 08 05:41:29 PM PDT 24
Finished Aug 08 05:41:32 PM PDT 24
Peak memory 215232 kb
Host smart-7683a035-b00f-4a24-bf9f-70813af857b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009799167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1009
799167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.1307788313
Short name T166
Test name
Test status
Simulation time 50202543189 ps
CPU time 5452.38 seconds
Started Aug 08 06:23:27 PM PDT 24
Finished Aug 08 07:54:20 PM PDT 24
Peak memory 2649736 kb
Host smart-0fd2e40b-da26-4a5c-bd2b-05eee683e389
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1307788313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1307788313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_app.3086013985
Short name T116
Test name
Test status
Simulation time 4291381712 ps
CPU time 71.24 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:25:00 PM PDT 24
Peak memory 249212 kb
Host smart-16d990f3-6ec9-466e-ac90-3149fc0a9ee5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086013985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3086013985 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.41029622
Short name T592
Test name
Test status
Simulation time 8066833127 ps
CPU time 684.91 seconds
Started Aug 08 06:23:51 PM PDT 24
Finished Aug 08 06:35:16 PM PDT 24
Peak memory 238636 kb
Host smart-c06ca7a7-1554-4adb-b337-fb81c31fe2b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.41029622 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1620730758
Short name T27
Test name
Test status
Simulation time 21915304279 ps
CPU time 507.55 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 06:31:50 PM PDT 24
Peak memory 485904 kb
Host smart-9f40c976-5db0-4fca-953b-6d0a406f4b66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1620730758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1620730758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3951868240
Short name T1093
Test name
Test status
Simulation time 455324495 ps
CPU time 8.93 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:09 PM PDT 24
Peak memory 207064 kb
Host smart-998409a0-e16e-468b-a5ae-4ab7343f40ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951868240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3951868
240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1380765947
Short name T1133
Test name
Test status
Simulation time 1002897034 ps
CPU time 19.66 seconds
Started Aug 08 05:41:01 PM PDT 24
Finished Aug 08 05:41:20 PM PDT 24
Peak memory 207020 kb
Host smart-99881b61-97a4-4dcc-94b2-383ffdbb7e97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380765947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1380765
947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1746017182
Short name T1190
Test name
Test status
Simulation time 144082152 ps
CPU time 1.11 seconds
Started Aug 08 05:41:01 PM PDT 24
Finished Aug 08 05:41:02 PM PDT 24
Peak memory 206776 kb
Host smart-f111f4cb-7c3f-4799-9fe7-137039ca4eeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746017182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1746017
182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2129076366
Short name T127
Test name
Test status
Simulation time 25744987 ps
CPU time 1.7 seconds
Started Aug 08 05:41:01 PM PDT 24
Finished Aug 08 05:41:03 PM PDT 24
Peak memory 215708 kb
Host smart-3cbe2e4e-45b7-4803-ab94-7370659fa00c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129076366 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2129076366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.4135278467
Short name T1053
Test name
Test status
Simulation time 176111771 ps
CPU time 1.16 seconds
Started Aug 08 05:40:59 PM PDT 24
Finished Aug 08 05:41:00 PM PDT 24
Peak memory 207012 kb
Host smart-ef85a31e-a8e0-4c8c-8ac6-939beace4b77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135278467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.4135278467 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2029484222
Short name T143
Test name
Test status
Simulation time 35640664 ps
CPU time 1.61 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:02 PM PDT 24
Peak memory 215260 kb
Host smart-39a4adcf-caad-4241-8b83-205fd53cf399
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029484222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.2029484222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2115681079
Short name T1065
Test name
Test status
Simulation time 15931975 ps
CPU time 0.72 seconds
Started Aug 08 05:40:59 PM PDT 24
Finished Aug 08 05:41:00 PM PDT 24
Peak memory 206804 kb
Host smart-47b46582-22fb-4846-8176-9af27006e19b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115681079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2115681079
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2857955294
Short name T1067
Test name
Test status
Simulation time 251173018 ps
CPU time 1.57 seconds
Started Aug 08 05:41:02 PM PDT 24
Finished Aug 08 05:41:04 PM PDT 24
Peak memory 215320 kb
Host smart-2bfa41b6-e0fa-4df3-8756-332df5f0347a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857955294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.2857955294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3652590841
Short name T108
Test name
Test status
Simulation time 28390859 ps
CPU time 0.89 seconds
Started Aug 08 05:41:05 PM PDT 24
Finished Aug 08 05:41:06 PM PDT 24
Peak memory 206864 kb
Host smart-57dfa904-7b71-409e-806f-ccd5a5edbf87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652590841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.3652590841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3814730193
Short name T1059
Test name
Test status
Simulation time 44727421 ps
CPU time 1.65 seconds
Started Aug 08 05:41:03 PM PDT 24
Finished Aug 08 05:41:05 PM PDT 24
Peak memory 215608 kb
Host smart-88ac79b0-2a1e-4df9-aa4b-e4ee7bf38b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814730193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.3814730193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2982568909
Short name T131
Test name
Test status
Simulation time 80737842 ps
CPU time 2.64 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:02 PM PDT 24
Peak memory 215324 kb
Host smart-54d01628-9c76-4809-954d-1712b23506ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982568909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2982568909 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.673740971
Short name T182
Test name
Test status
Simulation time 117313064 ps
CPU time 2.9 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:03 PM PDT 24
Peak memory 217884 kb
Host smart-89f43198-6f8e-4147-9c65-ba858ee89ff2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673740971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.673740
971 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1383299689
Short name T1089
Test name
Test status
Simulation time 524540518 ps
CPU time 10.58 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:11 PM PDT 24
Peak memory 207052 kb
Host smart-2b9b9e49-8ea0-4647-9c3e-0b067681c2d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383299689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1383299
689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.4134079580
Short name T1180
Test name
Test status
Simulation time 1178220215 ps
CPU time 14.85 seconds
Started Aug 08 05:41:06 PM PDT 24
Finished Aug 08 05:41:21 PM PDT 24
Peak memory 206972 kb
Host smart-323bd657-c4a8-45c7-85b7-1251ff028999
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134079580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.4134079
580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3531406132
Short name T1073
Test name
Test status
Simulation time 66858193 ps
CPU time 1.13 seconds
Started Aug 08 05:41:04 PM PDT 24
Finished Aug 08 05:41:05 PM PDT 24
Peak memory 207036 kb
Host smart-c7e69218-ebf1-47fa-abd8-1ebea716731d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531406132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3531406
132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1272763783
Short name T1081
Test name
Test status
Simulation time 170392998 ps
CPU time 1.71 seconds
Started Aug 08 05:41:01 PM PDT 24
Finished Aug 08 05:41:03 PM PDT 24
Peak memory 223544 kb
Host smart-6b9b5412-a4ab-4a1f-b7c4-1db3c54bb221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272763783 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1272763783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.763456938
Short name T1135
Test name
Test status
Simulation time 51270392 ps
CPU time 1.18 seconds
Started Aug 08 05:41:01 PM PDT 24
Finished Aug 08 05:41:02 PM PDT 24
Peak memory 207044 kb
Host smart-ebb95414-1f61-4bb8-a410-9d1b1a71875e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763456938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.763456938 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.569314582
Short name T1100
Test name
Test status
Simulation time 42485276 ps
CPU time 0.78 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:01 PM PDT 24
Peak memory 206756 kb
Host smart-361d0e98-874f-4c0e-aa18-3821e9bada62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569314582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.569314582 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.4220456333
Short name T1075
Test name
Test status
Simulation time 37256988 ps
CPU time 1.42 seconds
Started Aug 08 05:40:59 PM PDT 24
Finished Aug 08 05:41:01 PM PDT 24
Peak memory 215232 kb
Host smart-db55af89-8e4e-4a5f-9668-f688d220c7fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220456333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.4220456333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.907049968
Short name T1049
Test name
Test status
Simulation time 13511019 ps
CPU time 0.73 seconds
Started Aug 08 05:41:03 PM PDT 24
Finished Aug 08 05:41:04 PM PDT 24
Peak memory 206820 kb
Host smart-0d5c8513-d101-44b8-b52e-718c04e068f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907049968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.907049968 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.46123703
Short name T163
Test name
Test status
Simulation time 63480085 ps
CPU time 1.59 seconds
Started Aug 08 05:41:03 PM PDT 24
Finished Aug 08 05:41:04 PM PDT 24
Peak memory 215348 kb
Host smart-7f6417b2-f755-4705-bc9b-e2e2368627f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46123703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_o
utstanding.46123703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.702688668
Short name T103
Test name
Test status
Simulation time 30965382 ps
CPU time 1.21 seconds
Started Aug 08 05:41:06 PM PDT 24
Finished Aug 08 05:41:08 PM PDT 24
Peak memory 215548 kb
Host smart-e783d45a-4b1d-4611-ab21-4f5e3de8d70f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702688668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e
rrors.702688668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3563579592
Short name T109
Test name
Test status
Simulation time 106148729 ps
CPU time 2.6 seconds
Started Aug 08 05:41:01 PM PDT 24
Finished Aug 08 05:41:03 PM PDT 24
Peak memory 215592 kb
Host smart-c27ffac7-2391-4d51-ab9c-25bd7ef24c3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563579592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3563579592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3316529042
Short name T1160
Test name
Test status
Simulation time 47804931 ps
CPU time 2.94 seconds
Started Aug 08 05:41:02 PM PDT 24
Finished Aug 08 05:41:05 PM PDT 24
Peak memory 215308 kb
Host smart-36a0efe1-c96f-473b-a27c-37a309eb6687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316529042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3316529042 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2649445937
Short name T1192
Test name
Test status
Simulation time 705650640 ps
CPU time 2.91 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:03 PM PDT 24
Peak memory 215300 kb
Host smart-2344ec0c-5c18-465c-9fe3-9e0f28be48de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649445937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.26494
45937 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1858729834
Short name T1096
Test name
Test status
Simulation time 34843211 ps
CPU time 2.44 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 216772 kb
Host smart-89760a65-0d1c-423b-b389-c38d020fabbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858729834 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1858729834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.603381742
Short name T1112
Test name
Test status
Simulation time 35565594 ps
CPU time 1.18 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 215172 kb
Host smart-6ce8fcdb-f22d-42ff-8f74-a90009bba301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603381742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.603381742 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.3439978789
Short name T1155
Test name
Test status
Simulation time 27481367 ps
CPU time 0.8 seconds
Started Aug 08 05:41:18 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 206776 kb
Host smart-0df3513d-47d7-405d-80dd-5ced3da7e788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439978789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3439978789 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3572557248
Short name T1149
Test name
Test status
Simulation time 178033453 ps
CPU time 2.47 seconds
Started Aug 08 05:41:18 PM PDT 24
Finished Aug 08 05:41:21 PM PDT 24
Peak memory 215748 kb
Host smart-7b9fd427-3e19-4249-920d-6376ae4ece6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572557248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3572557248 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2227476564
Short name T1194
Test name
Test status
Simulation time 32494323 ps
CPU time 1.29 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 215504 kb
Host smart-02f39f68-b675-4676-bc93-d2da8566bcae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227476564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.2227476564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1376355632
Short name T1167
Test name
Test status
Simulation time 465482699 ps
CPU time 2.99 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:20 PM PDT 24
Peak memory 215736 kb
Host smart-0c19466e-ca8e-48d2-8bcf-6ed08f1d7dd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376355632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.1376355632 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.2723379985
Short name T1172
Test name
Test status
Simulation time 57562268 ps
CPU time 1.74 seconds
Started Aug 08 05:41:16 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 215224 kb
Host smart-ea82fdaa-a4f3-43e2-ace1-b628a3ff1ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723379985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2723379985 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.790622834
Short name T1116
Test name
Test status
Simulation time 1073408182 ps
CPU time 2.35 seconds
Started Aug 08 05:41:23 PM PDT 24
Finished Aug 08 05:41:25 PM PDT 24
Peak memory 216880 kb
Host smart-7d9b4315-0d33-4328-baa1-657db83ff14b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790622834 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.790622834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2296745199
Short name T1056
Test name
Test status
Simulation time 148693669 ps
CPU time 1.11 seconds
Started Aug 08 05:41:22 PM PDT 24
Finished Aug 08 05:41:23 PM PDT 24
Peak memory 206960 kb
Host smart-bc395964-3440-47f5-89bb-edcfc362d8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296745199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2296745199 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.1438271521
Short name T1080
Test name
Test status
Simulation time 23200256 ps
CPU time 0.79 seconds
Started Aug 08 05:41:22 PM PDT 24
Finished Aug 08 05:41:23 PM PDT 24
Peak memory 206748 kb
Host smart-ed50b21e-837d-41ad-b08c-8c36a633a7f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438271521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1438271521 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.4263938648
Short name T149
Test name
Test status
Simulation time 61961527 ps
CPU time 1.6 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215544 kb
Host smart-2408489d-a2fa-4dcc-8477-1e06221dc801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263938648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.4263938648 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3014477495
Short name T1094
Test name
Test status
Simulation time 70789519 ps
CPU time 1.21 seconds
Started Aug 08 05:41:23 PM PDT 24
Finished Aug 08 05:41:24 PM PDT 24
Peak memory 215736 kb
Host smart-4f5c76c6-2f64-4008-a96e-76afad27b62e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014477495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.3014477495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.545220884
Short name T112
Test name
Test status
Simulation time 221717700 ps
CPU time 1.95 seconds
Started Aug 08 05:41:28 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 215672 kb
Host smart-25800ce4-5902-4a7a-86d6-e4741e9b7420
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545220884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac
_shadow_reg_errors_with_csr_rw.545220884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.585644360
Short name T1136
Test name
Test status
Simulation time 50802933 ps
CPU time 1.83 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215228 kb
Host smart-893c5ca2-de61-42be-909b-b6fa0bbda966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585644360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.585644360 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2269015535
Short name T1191
Test name
Test status
Simulation time 202823769 ps
CPU time 2.48 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215348 kb
Host smart-960b6f14-560f-497e-8989-faf006e6fb97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269015535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2269
015535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1626875965
Short name T130
Test name
Test status
Simulation time 21906132 ps
CPU time 1.46 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:25 PM PDT 24
Peak memory 215292 kb
Host smart-0589048f-5a39-4678-bb8d-5bdccc97f052
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626875965 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1626875965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.985451733
Short name T190
Test name
Test status
Simulation time 56084734 ps
CPU time 0.95 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:25 PM PDT 24
Peak memory 206752 kb
Host smart-827be5f6-862c-470f-bb19-0dc058d447e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985451733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.985451733 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.3302753317
Short name T1078
Test name
Test status
Simulation time 32112027 ps
CPU time 0.78 seconds
Started Aug 08 05:41:28 PM PDT 24
Finished Aug 08 05:41:29 PM PDT 24
Peak memory 206788 kb
Host smart-6bf32fcf-52fd-43fc-a972-a16e38e1789a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302753317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3302753317 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3495233918
Short name T1108
Test name
Test status
Simulation time 39995102 ps
CPU time 2.3 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215724 kb
Host smart-aa88c102-7b71-4dda-ae13-21fb125627fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495233918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3495233918 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3397334970
Short name T1087
Test name
Test status
Simulation time 132535568 ps
CPU time 1.2 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215576 kb
Host smart-8e222faf-58ba-4761-94ab-45b01c896785
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397334970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.3397334970 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2618898666
Short name T1203
Test name
Test status
Simulation time 335928756 ps
CPU time 3.3 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 223464 kb
Host smart-2438afc2-1eb2-437d-8c49-37ed20b06dab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618898666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2618898666 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.662416949
Short name T181
Test name
Test status
Simulation time 167995749 ps
CPU time 2.7 seconds
Started Aug 08 05:41:23 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215276 kb
Host smart-b076d683-dce1-4f02-a3c2-17f70ffb9ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662416949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.66241
6949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.857177999
Short name T1095
Test name
Test status
Simulation time 48959205 ps
CPU time 1.58 seconds
Started Aug 08 05:41:26 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 223432 kb
Host smart-c9f539e9-c1a4-4b28-a27d-0b86391391b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857177999 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.857177999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1687305979
Short name T1156
Test name
Test status
Simulation time 98823192 ps
CPU time 1.12 seconds
Started Aug 08 05:41:28 PM PDT 24
Finished Aug 08 05:41:29 PM PDT 24
Peak memory 207064 kb
Host smart-7f80ef3a-5f9d-4fe8-9a39-312bb01f3f47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687305979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1687305979 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.304765534
Short name T1064
Test name
Test status
Simulation time 11979296 ps
CPU time 0.77 seconds
Started Aug 08 05:41:26 PM PDT 24
Finished Aug 08 05:41:27 PM PDT 24
Peak memory 206716 kb
Host smart-085c887b-c12f-480f-8a68-ad8471734961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304765534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.304765534 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3124240732
Short name T1086
Test name
Test status
Simulation time 26073019 ps
CPU time 1.41 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215220 kb
Host smart-638090de-dd3f-42a7-8b71-64f054b6be1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124240732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3124240732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.53644397
Short name T110
Test name
Test status
Simulation time 25842236 ps
CPU time 1.08 seconds
Started Aug 08 05:41:25 PM PDT 24
Finished Aug 08 05:41:26 PM PDT 24
Peak memory 215564 kb
Host smart-58864179-a51d-42d2-b8c0-cf416e2b2228
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53644397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_e
rrors.53644397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2549727112
Short name T1120
Test name
Test status
Simulation time 264012694 ps
CPU time 2.47 seconds
Started Aug 08 05:41:24 PM PDT 24
Finished Aug 08 05:41:27 PM PDT 24
Peak memory 223832 kb
Host smart-9624f1a6-6030-4d96-9274-ff536c85b5a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549727112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2549727112 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2704431338
Short name T1111
Test name
Test status
Simulation time 473930954 ps
CPU time 1.89 seconds
Started Aug 08 05:41:25 PM PDT 24
Finished Aug 08 05:41:27 PM PDT 24
Peak memory 215384 kb
Host smart-5287392f-142c-40f3-a055-dc4f85ea51cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704431338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2704431338 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3287918261
Short name T183
Test name
Test status
Simulation time 747129363 ps
CPU time 4.73 seconds
Started Aug 08 05:41:25 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 207148 kb
Host smart-f23ed4c5-e5f4-4b70-b76e-25ea2c402856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287918261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3287
918261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.257532572
Short name T1170
Test name
Test status
Simulation time 151219747 ps
CPU time 1.71 seconds
Started Aug 08 05:41:26 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 215356 kb
Host smart-15c820af-56d8-418a-8c81-39e0d3e624ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257532572 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.257532572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1711246899
Short name T1183
Test name
Test status
Simulation time 41373329 ps
CPU time 0.89 seconds
Started Aug 08 05:41:25 PM PDT 24
Finished Aug 08 05:41:27 PM PDT 24
Peak memory 206724 kb
Host smart-ff26d24c-1985-4cbd-8f86-c8143277e2bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711246899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1711246899 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1089913790
Short name T1163
Test name
Test status
Simulation time 157930835 ps
CPU time 1.47 seconds
Started Aug 08 05:41:26 PM PDT 24
Finished Aug 08 05:41:27 PM PDT 24
Peak memory 215664 kb
Host smart-fc31201a-5a4a-478c-b436-96de6e3ca26f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089913790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.1089913790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3018720040
Short name T1151
Test name
Test status
Simulation time 49177292 ps
CPU time 1.61 seconds
Started Aug 08 05:41:27 PM PDT 24
Finished Aug 08 05:41:29 PM PDT 24
Peak memory 215600 kb
Host smart-1398229a-e8de-4014-83a4-db63ed177f81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018720040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.3018720040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1926822135
Short name T1109
Test name
Test status
Simulation time 197269758 ps
CPU time 2.74 seconds
Started Aug 08 05:41:27 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 215220 kb
Host smart-93c5b35d-bab7-4255-b46e-fd3532067a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926822135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1926822135 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3006214832
Short name T1126
Test name
Test status
Simulation time 411058333 ps
CPU time 2.72 seconds
Started Aug 08 05:41:25 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 215268 kb
Host smart-b4129245-5e87-4563-86e0-afe9f0363355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006214832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3006
214832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1229892049
Short name T1175
Test name
Test status
Simulation time 64646884 ps
CPU time 2.19 seconds
Started Aug 08 05:41:30 PM PDT 24
Finished Aug 08 05:41:32 PM PDT 24
Peak memory 215400 kb
Host smart-4f5517f4-a39d-44e5-b02d-5c05ca1f3f72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229892049 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1229892049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1778737658
Short name T1186
Test name
Test status
Simulation time 58307313 ps
CPU time 1.17 seconds
Started Aug 08 05:41:27 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 207080 kb
Host smart-cbde4bf2-effd-4843-a7fb-85175bd257e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778737658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1778737658 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.91156554
Short name T1115
Test name
Test status
Simulation time 38755175 ps
CPU time 0.78 seconds
Started Aug 08 05:41:28 PM PDT 24
Finished Aug 08 05:41:29 PM PDT 24
Peak memory 206776 kb
Host smart-b2292f00-48c1-4f8a-9645-9fc65e3cd722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91156554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.91156554 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3672074929
Short name T151
Test name
Test status
Simulation time 506363610 ps
CPU time 2.52 seconds
Started Aug 08 05:41:30 PM PDT 24
Finished Aug 08 05:41:33 PM PDT 24
Peak memory 215540 kb
Host smart-a9138d38-2134-4ba1-97f1-09830198aa91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672074929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.3672074929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3034041418
Short name T1198
Test name
Test status
Simulation time 77957005 ps
CPU time 0.9 seconds
Started Aug 08 05:41:26 PM PDT 24
Finished Aug 08 05:41:27 PM PDT 24
Peak memory 206940 kb
Host smart-9e7dd32f-a5fa-42cd-9fd9-0bc20e17d9a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034041418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.3034041418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.2666443150
Short name T1208
Test name
Test status
Simulation time 58394801 ps
CPU time 1.99 seconds
Started Aug 08 05:41:27 PM PDT 24
Finished Aug 08 05:41:29 PM PDT 24
Peak memory 215236 kb
Host smart-32d81eea-e159-4e8f-811c-97537ea36149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666443150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2666443150 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.80579057
Short name T150
Test name
Test status
Simulation time 97955920 ps
CPU time 2.74 seconds
Started Aug 08 05:41:27 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 223488 kb
Host smart-aaf34806-4618-4676-8111-be4e9f8e8665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80579057 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.80579057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.951786798
Short name T1121
Test name
Test status
Simulation time 21347845 ps
CPU time 1.01 seconds
Started Aug 08 05:41:29 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 206780 kb
Host smart-7cc9997a-8bbb-4add-868f-fad717085b6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951786798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.951786798 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.20036512
Short name T162
Test name
Test status
Simulation time 57940448 ps
CPU time 0.76 seconds
Started Aug 08 05:41:28 PM PDT 24
Finished Aug 08 05:41:29 PM PDT 24
Peak memory 206784 kb
Host smart-89dd7698-6003-46f6-b835-13cc7e211a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20036512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.20036512 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3336502854
Short name T1048
Test name
Test status
Simulation time 924631370 ps
CPU time 1.56 seconds
Started Aug 08 05:41:30 PM PDT 24
Finished Aug 08 05:41:31 PM PDT 24
Peak memory 215208 kb
Host smart-df34ed21-ac23-49d7-aa00-3c8e3dde59c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336502854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.3336502854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2091810326
Short name T100
Test name
Test status
Simulation time 101175545 ps
CPU time 1.09 seconds
Started Aug 08 05:41:27 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 215584 kb
Host smart-41fc82a1-2245-45c7-81fc-6bb99a3c2084
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091810326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2091810326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2147118631
Short name T1164
Test name
Test status
Simulation time 71738297 ps
CPU time 2.02 seconds
Started Aug 08 05:41:26 PM PDT 24
Finished Aug 08 05:41:28 PM PDT 24
Peak memory 223396 kb
Host smart-2984279e-00dc-4c81-8723-141c7c5da7cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147118631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.2147118631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2813805159
Short name T141
Test name
Test status
Simulation time 385120818 ps
CPU time 2.88 seconds
Started Aug 08 05:41:30 PM PDT 24
Finished Aug 08 05:41:33 PM PDT 24
Peak memory 215300 kb
Host smart-a68431dd-05f8-4dea-a3af-5787e22b0e49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813805159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2813805159 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1014613170
Short name T1069
Test name
Test status
Simulation time 159207243 ps
CPU time 2.82 seconds
Started Aug 08 05:41:26 PM PDT 24
Finished Aug 08 05:41:29 PM PDT 24
Peak memory 207164 kb
Host smart-3a79b53d-aac2-4e1e-a01e-74902849d671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014613170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1014
613170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1076779602
Short name T1118
Test name
Test status
Simulation time 233281958 ps
CPU time 2.11 seconds
Started Aug 08 05:41:28 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 215912 kb
Host smart-5468ba5a-3859-4961-a8ef-e918e560ce4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076779602 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1076779602 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.815580656
Short name T1076
Test name
Test status
Simulation time 17355854 ps
CPU time 1.1 seconds
Started Aug 08 05:41:31 PM PDT 24
Finished Aug 08 05:41:32 PM PDT 24
Peak memory 206964 kb
Host smart-fdb51f80-de8c-4271-b9bf-2b090aa074dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815580656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.815580656 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.78875752
Short name T1139
Test name
Test status
Simulation time 50765566 ps
CPU time 0.75 seconds
Started Aug 08 05:41:30 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 206736 kb
Host smart-7658ce63-a27e-474a-869f-84ec89572dd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78875752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.78875752 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2266358890
Short name T1083
Test name
Test status
Simulation time 95766268 ps
CPU time 2.28 seconds
Started Aug 08 05:41:29 PM PDT 24
Finished Aug 08 05:41:32 PM PDT 24
Peak memory 215884 kb
Host smart-573040f7-5365-4d3d-a99d-e575828e9a8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266358890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.2266358890 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.143889316
Short name T105
Test name
Test status
Simulation time 138373434 ps
CPU time 1.08 seconds
Started Aug 08 05:41:29 PM PDT 24
Finished Aug 08 05:41:31 PM PDT 24
Peak memory 207324 kb
Host smart-a5ca0ac6-37b7-4981-bf22-e620f61d1540
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143889316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_
errors.143889316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1592031680
Short name T1182
Test name
Test status
Simulation time 63476127 ps
CPU time 1.82 seconds
Started Aug 08 05:41:30 PM PDT 24
Finished Aug 08 05:41:33 PM PDT 24
Peak memory 215648 kb
Host smart-70983807-1719-455c-8590-686cc5594a08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592031680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.1592031680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.896870605
Short name T1127
Test name
Test status
Simulation time 35886928 ps
CPU time 2.08 seconds
Started Aug 08 05:41:28 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 223324 kb
Host smart-d6c70bb9-ccf9-4b16-b771-42509c17df12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896870605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.896870605 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.411096402
Short name T1157
Test name
Test status
Simulation time 295727135 ps
CPU time 2.37 seconds
Started Aug 08 05:41:35 PM PDT 24
Finished Aug 08 05:41:38 PM PDT 24
Peak memory 216896 kb
Host smart-0841d3b0-3e38-4745-bfc3-289ddc6e6b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411096402 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.411096402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.420035269
Short name T1141
Test name
Test status
Simulation time 101403952 ps
CPU time 1.14 seconds
Started Aug 08 05:41:31 PM PDT 24
Finished Aug 08 05:41:33 PM PDT 24
Peak memory 207260 kb
Host smart-3098abbb-605e-4cee-ae9a-e4958b9ca7c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420035269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.420035269 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.3106415339
Short name T1090
Test name
Test status
Simulation time 34369245 ps
CPU time 0.74 seconds
Started Aug 08 05:41:32 PM PDT 24
Finished Aug 08 05:41:33 PM PDT 24
Peak memory 206828 kb
Host smart-a6c5744a-b1ed-4275-a5fb-67df21ec922c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106415339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3106415339 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.56194924
Short name T165
Test name
Test status
Simulation time 118149370 ps
CPU time 1.57 seconds
Started Aug 08 05:41:33 PM PDT 24
Finished Aug 08 05:41:34 PM PDT 24
Peak memory 215340 kb
Host smart-98881c00-8d00-42a0-aba3-f8b2c02ad568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56194924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_
outstanding.56194924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1025918017
Short name T1197
Test name
Test status
Simulation time 93106061 ps
CPU time 1.01 seconds
Started Aug 08 05:41:29 PM PDT 24
Finished Aug 08 05:41:30 PM PDT 24
Peak memory 215628 kb
Host smart-83e02fe3-7e5a-481d-ac29-a7990ef0f186
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025918017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1025918017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1537489444
Short name T1105
Test name
Test status
Simulation time 54315459 ps
CPU time 1.57 seconds
Started Aug 08 05:41:29 PM PDT 24
Finished Aug 08 05:41:31 PM PDT 24
Peak memory 207164 kb
Host smart-7829092a-3b61-48d9-973d-d6069777cc4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537489444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.1537489444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.324846189
Short name T1063
Test name
Test status
Simulation time 158797287 ps
CPU time 2.47 seconds
Started Aug 08 05:41:33 PM PDT 24
Finished Aug 08 05:41:35 PM PDT 24
Peak memory 215248 kb
Host smart-c54c7099-2e31-4f1d-bac0-dd4964eca48e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324846189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.324846189 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3222783704
Short name T128
Test name
Test status
Simulation time 81993060 ps
CPU time 2.21 seconds
Started Aug 08 05:41:35 PM PDT 24
Finished Aug 08 05:41:37 PM PDT 24
Peak memory 223448 kb
Host smart-1a0a4b49-cfac-45e8-ab1f-ffb99cf5c44b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222783704 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3222783704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1193308736
Short name T1106
Test name
Test status
Simulation time 27918834 ps
CPU time 1.08 seconds
Started Aug 08 05:41:35 PM PDT 24
Finished Aug 08 05:41:36 PM PDT 24
Peak memory 206996 kb
Host smart-7709528b-66eb-4bfc-9e3d-c9aa917f7d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193308736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1193308736 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.2610472507
Short name T1144
Test name
Test status
Simulation time 22077636 ps
CPU time 0.79 seconds
Started Aug 08 05:41:34 PM PDT 24
Finished Aug 08 05:41:35 PM PDT 24
Peak memory 206808 kb
Host smart-6170c4ce-4e43-466d-9ec8-5881da6e948a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610472507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2610472507 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2081420789
Short name T1181
Test name
Test status
Simulation time 48324640 ps
CPU time 1.47 seconds
Started Aug 08 05:41:34 PM PDT 24
Finished Aug 08 05:41:36 PM PDT 24
Peak memory 215344 kb
Host smart-ec4c1cbd-e2a3-40b0-a802-3535ac096f36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081420789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.2081420789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2403378139
Short name T1173
Test name
Test status
Simulation time 137527354 ps
CPU time 1.06 seconds
Started Aug 08 05:41:32 PM PDT 24
Finished Aug 08 05:41:33 PM PDT 24
Peak memory 215528 kb
Host smart-10deedec-7666-4ca8-88a7-ac74d4c3400d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403378139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.2403378139 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2660184506
Short name T1171
Test name
Test status
Simulation time 81987821 ps
CPU time 2.07 seconds
Started Aug 08 05:41:31 PM PDT 24
Finished Aug 08 05:41:33 PM PDT 24
Peak memory 215628 kb
Host smart-50992220-7121-49f2-8f9b-297bedda6ad4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660184506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.2660184506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1881061766
Short name T1097
Test name
Test status
Simulation time 707131365 ps
CPU time 4.07 seconds
Started Aug 08 05:41:32 PM PDT 24
Finished Aug 08 05:41:36 PM PDT 24
Peak memory 215228 kb
Host smart-63d9a7ac-11a7-4a0f-b8c5-df6c8feaae44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881061766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1881061766 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.8439163
Short name T180
Test name
Test status
Simulation time 368991822 ps
CPU time 4.73 seconds
Started Aug 08 05:41:31 PM PDT 24
Finished Aug 08 05:41:36 PM PDT 24
Peak memory 214396 kb
Host smart-ebcf7bce-d25f-44e8-8f0c-af686d62a640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8439163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.8439163
+enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1853530545
Short name T1189
Test name
Test status
Simulation time 549163856 ps
CPU time 7.76 seconds
Started Aug 08 05:41:02 PM PDT 24
Finished Aug 08 05:41:10 PM PDT 24
Peak memory 215216 kb
Host smart-0af586a8-0b64-4a79-8fa3-9a9bdc2eb4b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853530545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1853530
545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1911866449
Short name T1082
Test name
Test status
Simulation time 149893769 ps
CPU time 7.76 seconds
Started Aug 08 05:41:03 PM PDT 24
Finished Aug 08 05:41:11 PM PDT 24
Peak memory 207020 kb
Host smart-46797640-8380-4472-9a49-fa81e194acde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911866449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1911866
449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.497058818
Short name T1103
Test name
Test status
Simulation time 20044285 ps
CPU time 1.02 seconds
Started Aug 08 05:41:02 PM PDT 24
Finished Aug 08 05:41:03 PM PDT 24
Peak memory 206812 kb
Host smart-92f76480-9baf-4f01-9002-0444c23770c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497058818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.49705881
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1481978483
Short name T129
Test name
Test status
Simulation time 67744188 ps
CPU time 2.27 seconds
Started Aug 08 05:41:14 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 223380 kb
Host smart-b7fc4dfa-f025-47f7-a4d1-603fa21a54ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481978483 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.1481978483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.2552596439
Short name T1062
Test name
Test status
Simulation time 70998227 ps
CPU time 0.94 seconds
Started Aug 08 05:41:05 PM PDT 24
Finished Aug 08 05:41:06 PM PDT 24
Peak memory 206772 kb
Host smart-a33958b5-34b6-4df0-8f5a-bab770f28c4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552596439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2552596439 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2895508030
Short name T1161
Test name
Test status
Simulation time 25004732 ps
CPU time 0.79 seconds
Started Aug 08 05:41:06 PM PDT 24
Finished Aug 08 05:41:07 PM PDT 24
Peak memory 206656 kb
Host smart-5c85e503-dc15-43b8-90e4-160c00387631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895508030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2895508030 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.95795989
Short name T144
Test name
Test status
Simulation time 179685917 ps
CPU time 1.41 seconds
Started Aug 08 05:41:03 PM PDT 24
Finished Aug 08 05:41:05 PM PDT 24
Peak memory 215256 kb
Host smart-4990eb4d-7cae-4f53-acf4-02ed1e62957f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95795989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_
access.95795989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.623312874
Short name T1184
Test name
Test status
Simulation time 17576303 ps
CPU time 0.72 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:01 PM PDT 24
Peak memory 206764 kb
Host smart-2a2fceb0-a498-4085-ab25-c3ee2e955083
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623312874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.623312874 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1420458850
Short name T1185
Test name
Test status
Simulation time 38982829 ps
CPU time 2.25 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 215720 kb
Host smart-3bd647d7-6c39-44ad-9445-c458592a89c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420458850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.1420458850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1457948592
Short name T1152
Test name
Test status
Simulation time 22721007 ps
CPU time 1.11 seconds
Started Aug 08 05:40:59 PM PDT 24
Finished Aug 08 05:41:00 PM PDT 24
Peak memory 215664 kb
Host smart-a05912dd-2311-420c-8938-52bf62c70219
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457948592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.1457948592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1353695993
Short name T99
Test name
Test status
Simulation time 1260616606 ps
CPU time 2.28 seconds
Started Aug 08 05:40:59 PM PDT 24
Finished Aug 08 05:41:02 PM PDT 24
Peak memory 215368 kb
Host smart-4c41c863-22da-4ae5-8b15-89217eadde5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353695993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.1353695993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3759183501
Short name T1145
Test name
Test status
Simulation time 31275793 ps
CPU time 1.81 seconds
Started Aug 08 05:41:00 PM PDT 24
Finished Aug 08 05:41:02 PM PDT 24
Peak memory 215260 kb
Host smart-97451cde-d4d6-4c15-b275-193ef6202dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759183501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.3759183501 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1014634226
Short name T189
Test name
Test status
Simulation time 52670737 ps
CPU time 2.46 seconds
Started Aug 08 05:41:03 PM PDT 24
Finished Aug 08 05:41:05 PM PDT 24
Peak memory 215288 kb
Host smart-081ecefc-7f55-4625-b31d-4249a6c68286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014634226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.10146
34226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.3862978007
Short name T1092
Test name
Test status
Simulation time 11229121 ps
CPU time 0.75 seconds
Started Aug 08 05:41:35 PM PDT 24
Finished Aug 08 05:41:36 PM PDT 24
Peak memory 206772 kb
Host smart-8c0efeda-3a41-4dcd-955c-a34f86943303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862978007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3862978007 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.2086731979
Short name T1102
Test name
Test status
Simulation time 31081878 ps
CPU time 0.81 seconds
Started Aug 08 05:41:34 PM PDT 24
Finished Aug 08 05:41:34 PM PDT 24
Peak memory 206724 kb
Host smart-434cedac-5ee5-4848-8bdd-aa73353a4209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086731979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2086731979 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1325310688
Short name T1074
Test name
Test status
Simulation time 16529458 ps
CPU time 0.8 seconds
Started Aug 08 05:41:35 PM PDT 24
Finished Aug 08 05:41:36 PM PDT 24
Peak memory 206772 kb
Host smart-9023323d-9ab2-47cf-a0b3-fa17dfcd6654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325310688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1325310688 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2139370576
Short name T1178
Test name
Test status
Simulation time 21694681 ps
CPU time 0.76 seconds
Started Aug 08 05:41:35 PM PDT 24
Finished Aug 08 05:41:36 PM PDT 24
Peak memory 206772 kb
Host smart-4302bc78-3e89-45c8-a795-55616b48d914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139370576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2139370576 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.30071555
Short name T1146
Test name
Test status
Simulation time 201075073 ps
CPU time 0.78 seconds
Started Aug 08 05:41:40 PM PDT 24
Finished Aug 08 05:41:41 PM PDT 24
Peak memory 206708 kb
Host smart-40d5fa6a-e85f-48a2-907f-f3b91e15baa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30071555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.30071555 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.2875959933
Short name T1176
Test name
Test status
Simulation time 28714721 ps
CPU time 0.75 seconds
Started Aug 08 05:41:39 PM PDT 24
Finished Aug 08 05:41:40 PM PDT 24
Peak memory 206716 kb
Host smart-99791f5c-65a2-4bf4-a2e6-5e3476ed2af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875959933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2875959933 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2276458144
Short name T1148
Test name
Test status
Simulation time 80457107 ps
CPU time 0.76 seconds
Started Aug 08 05:41:34 PM PDT 24
Finished Aug 08 05:41:35 PM PDT 24
Peak memory 206812 kb
Host smart-568a02b2-a378-44c4-ab9b-ef268a0187d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276458144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2276458144 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2013790928
Short name T126
Test name
Test status
Simulation time 48566694 ps
CPU time 0.76 seconds
Started Aug 08 05:41:39 PM PDT 24
Finished Aug 08 05:41:40 PM PDT 24
Peak memory 206808 kb
Host smart-40255ffa-6aa5-4c28-8268-4dd007a8512a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013790928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2013790928 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.2764992516
Short name T1119
Test name
Test status
Simulation time 27587712 ps
CPU time 0.82 seconds
Started Aug 08 05:41:40 PM PDT 24
Finished Aug 08 05:41:41 PM PDT 24
Peak memory 206760 kb
Host smart-82d5bdb0-0b23-4f17-8442-a7c54ad921a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764992516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2764992516 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.2910650413
Short name T1107
Test name
Test status
Simulation time 30623922 ps
CPU time 0.74 seconds
Started Aug 08 05:41:39 PM PDT 24
Finished Aug 08 05:41:40 PM PDT 24
Peak memory 206800 kb
Host smart-1f21c4d8-b613-4989-8fa8-72b5da38516e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910650413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2910650413 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.550109868
Short name T1143
Test name
Test status
Simulation time 816670339 ps
CPU time 5.01 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:22 PM PDT 24
Peak memory 215440 kb
Host smart-156c9d17-2ee5-4912-9c24-074885559ae2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550109868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.55010986
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4227283464
Short name T1113
Test name
Test status
Simulation time 4978790101 ps
CPU time 20.79 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:33 PM PDT 24
Peak memory 207060 kb
Host smart-8bac553d-1a64-42f7-911c-c3d778d58949
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227283464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.4227283
464 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.4129789459
Short name T1068
Test name
Test status
Simulation time 36548843 ps
CPU time 0.98 seconds
Started Aug 08 05:41:14 PM PDT 24
Finished Aug 08 05:41:15 PM PDT 24
Peak memory 206776 kb
Host smart-d06c9f4e-af48-453a-b352-1077215d29d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129789459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.4129789
459 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.82022094
Short name T1122
Test name
Test status
Simulation time 281409476 ps
CPU time 2.33 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:15 PM PDT 24
Peak memory 216444 kb
Host smart-e8ba6ed2-e153-4910-8f3a-d596fef15102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82022094 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.82022094 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3300205522
Short name T1131
Test name
Test status
Simulation time 46028694 ps
CPU time 0.93 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 206712 kb
Host smart-782c5bfb-b851-479f-a24e-df6694167519
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300205522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3300205522 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1789497045
Short name T1061
Test name
Test status
Simulation time 34363467 ps
CPU time 0.74 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 206704 kb
Host smart-620d914f-f0a7-4b68-a158-0afde146d88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789497045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1789497045 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3271798499
Short name T145
Test name
Test status
Simulation time 32320387 ps
CPU time 1.27 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:16 PM PDT 24
Peak memory 215168 kb
Host smart-3e583d77-7029-4db9-8a0c-851939afa630
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271798499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.3271798499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1610669482
Short name T1137
Test name
Test status
Simulation time 47643360 ps
CPU time 0.71 seconds
Started Aug 08 05:41:14 PM PDT 24
Finished Aug 08 05:41:15 PM PDT 24
Peak memory 206720 kb
Host smart-1ee0bb0c-ed6a-4f4c-94af-f1262aabb8ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610669482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1610669482
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.700817983
Short name T1159
Test name
Test status
Simulation time 62764066 ps
CPU time 1.61 seconds
Started Aug 08 05:41:10 PM PDT 24
Finished Aug 08 05:41:12 PM PDT 24
Peak memory 215972 kb
Host smart-d6680d7e-35f9-47cb-bafc-ca5dc2dd6619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700817983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_
outstanding.700817983 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1896020506
Short name T104
Test name
Test status
Simulation time 34359150 ps
CPU time 1.17 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 215624 kb
Host smart-0bc77802-fc80-4368-95fc-7978c7bb4e5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896020506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.1896020506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3818723178
Short name T1150
Test name
Test status
Simulation time 59085039 ps
CPU time 2.64 seconds
Started Aug 08 05:41:19 PM PDT 24
Finished Aug 08 05:41:21 PM PDT 24
Peak memory 215576 kb
Host smart-73e9abc2-fd5b-48fb-895a-3291cb71768e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818723178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.3818723178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.65037409
Short name T1123
Test name
Test status
Simulation time 454858945 ps
CPU time 3.32 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 215348 kb
Host smart-6aa3d2cf-c922-4c71-b2af-bb5a392ed7cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65037409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.65037409 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2259359794
Short name T188
Test name
Test status
Simulation time 135006291 ps
CPU time 2.84 seconds
Started Aug 08 05:41:11 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 207028 kb
Host smart-207dbb3c-cc07-4e08-8146-36dcf291e2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259359794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.22593
59794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.1497671470
Short name T1128
Test name
Test status
Simulation time 14746370 ps
CPU time 0.79 seconds
Started Aug 08 05:41:41 PM PDT 24
Finished Aug 08 05:41:42 PM PDT 24
Peak memory 206732 kb
Host smart-d45da47a-8dea-442e-bd58-d70c31d794cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497671470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1497671470 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.402861801
Short name T1177
Test name
Test status
Simulation time 77909332 ps
CPU time 0.77 seconds
Started Aug 08 05:41:41 PM PDT 24
Finished Aug 08 05:41:42 PM PDT 24
Peak memory 206788 kb
Host smart-cd780ead-0435-479d-9fda-dbd3ea6f1848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402861801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.402861801 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.1877886306
Short name T1199
Test name
Test status
Simulation time 54348686 ps
CPU time 0.79 seconds
Started Aug 08 05:41:33 PM PDT 24
Finished Aug 08 05:41:34 PM PDT 24
Peak memory 206772 kb
Host smart-80b76fb9-c010-4b2a-94a7-67f129d6df8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877886306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1877886306 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.1204368724
Short name T1207
Test name
Test status
Simulation time 162409638 ps
CPU time 0.82 seconds
Started Aug 08 05:41:40 PM PDT 24
Finished Aug 08 05:41:41 PM PDT 24
Peak memory 206768 kb
Host smart-a75e59b2-5407-4281-bf11-4929d8898418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204368724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1204368724 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.56513241
Short name T1166
Test name
Test status
Simulation time 43555805 ps
CPU time 0.78 seconds
Started Aug 08 05:41:39 PM PDT 24
Finished Aug 08 05:41:40 PM PDT 24
Peak memory 206788 kb
Host smart-ab149f8e-10cf-4711-8340-183cf93e923b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56513241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.56513241 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3183696464
Short name T1114
Test name
Test status
Simulation time 15073858 ps
CPU time 0.75 seconds
Started Aug 08 05:41:43 PM PDT 24
Finished Aug 08 05:41:44 PM PDT 24
Peak memory 206660 kb
Host smart-724fdee2-2e46-4a8f-b852-a46a4f23a5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183696464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3183696464 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.2837463529
Short name T124
Test name
Test status
Simulation time 13977505 ps
CPU time 0.78 seconds
Started Aug 08 05:41:45 PM PDT 24
Finished Aug 08 05:41:45 PM PDT 24
Peak memory 206792 kb
Host smart-dbd292df-4633-463c-96fe-96a912d0f659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837463529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2837463529 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.863713433
Short name T1179
Test name
Test status
Simulation time 13963577 ps
CPU time 0.75 seconds
Started Aug 08 05:41:45 PM PDT 24
Finished Aug 08 05:41:46 PM PDT 24
Peak memory 206824 kb
Host smart-38f8f83e-f373-4ded-9e70-68c46f17e916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863713433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.863713433 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.3304399555
Short name T1110
Test name
Test status
Simulation time 28905676 ps
CPU time 0.82 seconds
Started Aug 08 05:41:46 PM PDT 24
Finished Aug 08 05:41:47 PM PDT 24
Peak memory 206820 kb
Host smart-8ecd5672-8dbc-4b48-9587-93a49d41d797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304399555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3304399555 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1556050521
Short name T1084
Test name
Test status
Simulation time 206969939 ps
CPU time 0.86 seconds
Started Aug 08 05:41:45 PM PDT 24
Finished Aug 08 05:41:46 PM PDT 24
Peak memory 206832 kb
Host smart-06991753-7844-43ec-a6ff-53f50bbcc729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556050521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1556050521 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1742017226
Short name T1138
Test name
Test status
Simulation time 538296254 ps
CPU time 5.58 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 207036 kb
Host smart-226e33fa-2034-4a3d-bf1f-f917092eb5b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742017226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1742017
226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.17845427
Short name T1052
Test name
Test status
Simulation time 554399115 ps
CPU time 8.26 seconds
Started Aug 08 05:41:14 PM PDT 24
Finished Aug 08 05:41:22 PM PDT 24
Peak memory 207092 kb
Host smart-490cd01f-9656-4d03-89be-e4667e018c15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17845427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.17845427
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3100800975
Short name T1165
Test name
Test status
Simulation time 69930721 ps
CPU time 0.94 seconds
Started Aug 08 05:41:19 PM PDT 24
Finished Aug 08 05:41:20 PM PDT 24
Peak memory 206828 kb
Host smart-5d8c5852-b1f6-4616-8879-a46642378892
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100800975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3100800
975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.4150203832
Short name T1132
Test name
Test status
Simulation time 38701781 ps
CPU time 1.63 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:15 PM PDT 24
Peak memory 215360 kb
Host smart-b180624b-900d-468b-b073-e60433f3d560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150203832 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.4150203832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1711010338
Short name T1196
Test name
Test status
Simulation time 100213731 ps
CPU time 1.2 seconds
Started Aug 08 05:41:16 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 207052 kb
Host smart-1b025fe7-883d-46a0-ad71-e03c6abbc868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711010338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1711010338 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.515905853
Short name T164
Test name
Test status
Simulation time 20037475 ps
CPU time 0.77 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 206788 kb
Host smart-fa774f7a-e1a4-4eb8-9b3d-f1b36f5c675b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515905853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.515905853 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.484901025
Short name T1047
Test name
Test status
Simulation time 25972066 ps
CPU time 0.71 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:13 PM PDT 24
Peak memory 206800 kb
Host smart-7a95d236-a7b7-49b9-9d49-46689c3fd3cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484901025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.484901025 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.4001978993
Short name T1195
Test name
Test status
Simulation time 267377044 ps
CPU time 2.31 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:15 PM PDT 24
Peak memory 215896 kb
Host smart-3af7bdd1-14c6-4a65-aa16-293f68f913b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001978993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.4001978993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3133203816
Short name T1140
Test name
Test status
Simulation time 139177303 ps
CPU time 0.84 seconds
Started Aug 08 05:41:16 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 206852 kb
Host smart-64801d8a-4b17-4d0b-8bbf-e0d2f0f8fa09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133203816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.3133203816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3520091319
Short name T107
Test name
Test status
Simulation time 555208407 ps
CPU time 2.11 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:20 PM PDT 24
Peak memory 215832 kb
Host smart-fbee70e1-9153-48c0-a762-a4aa00e6f12e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520091319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.3520091319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.4152082606
Short name T1099
Test name
Test status
Simulation time 146712616 ps
CPU time 3.51 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:20 PM PDT 24
Peak memory 215160 kb
Host smart-619dbe6b-3b32-408e-8815-399d199cad74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152082606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.4152082606 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4204413703
Short name T1168
Test name
Test status
Simulation time 138836225 ps
CPU time 2.42 seconds
Started Aug 08 05:41:18 PM PDT 24
Finished Aug 08 05:41:21 PM PDT 24
Peak memory 215348 kb
Host smart-b46a63f5-c638-4659-b9d2-2bfee3a55ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204413703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.42044
13703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.1638189655
Short name T1158
Test name
Test status
Simulation time 15965488 ps
CPU time 0.8 seconds
Started Aug 08 05:41:45 PM PDT 24
Finished Aug 08 05:41:46 PM PDT 24
Peak memory 206752 kb
Host smart-7cc17bfb-a081-4462-82d2-0f7d8352b2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638189655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1638189655 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.1098833488
Short name T1104
Test name
Test status
Simulation time 63220839 ps
CPU time 0.77 seconds
Started Aug 08 05:41:47 PM PDT 24
Finished Aug 08 05:41:48 PM PDT 24
Peak memory 206708 kb
Host smart-f41064ab-80f7-4a70-ace8-0a10d03930d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098833488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1098833488 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1736305653
Short name T1187
Test name
Test status
Simulation time 11526228 ps
CPU time 0.76 seconds
Started Aug 08 05:41:44 PM PDT 24
Finished Aug 08 05:41:45 PM PDT 24
Peak memory 206728 kb
Host smart-36ae4d0c-3a0f-4f24-b4c8-1ba23379b98b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736305653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1736305653 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.696695061
Short name T1098
Test name
Test status
Simulation time 21196717 ps
CPU time 0.79 seconds
Started Aug 08 05:41:41 PM PDT 24
Finished Aug 08 05:41:42 PM PDT 24
Peak memory 206816 kb
Host smart-5d970279-241e-4efc-8b0d-dcd20e81191b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696695061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.696695061 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.3818673697
Short name T125
Test name
Test status
Simulation time 14402340 ps
CPU time 0.75 seconds
Started Aug 08 05:41:47 PM PDT 24
Finished Aug 08 05:41:48 PM PDT 24
Peak memory 206704 kb
Host smart-aa58bac4-a40c-4f00-9b52-01553884ee10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818673697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3818673697 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.855678181
Short name T1058
Test name
Test status
Simulation time 13982801 ps
CPU time 0.79 seconds
Started Aug 08 05:41:45 PM PDT 24
Finished Aug 08 05:41:46 PM PDT 24
Peak memory 206792 kb
Host smart-ba910172-8715-4b5e-a20a-c562f5f25fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855678181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.855678181 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1768316395
Short name T1205
Test name
Test status
Simulation time 38383714 ps
CPU time 0.79 seconds
Started Aug 08 05:41:45 PM PDT 24
Finished Aug 08 05:41:46 PM PDT 24
Peak memory 206832 kb
Host smart-521e4baa-9419-48fc-b2c4-30c5f65fed05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768316395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1768316395 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.897220953
Short name T1060
Test name
Test status
Simulation time 15721454 ps
CPU time 0.78 seconds
Started Aug 08 05:41:47 PM PDT 24
Finished Aug 08 05:41:48 PM PDT 24
Peak memory 206708 kb
Host smart-e3538e37-e102-4cd0-bc21-3f3b929f5515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897220953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.897220953 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.62533099
Short name T1054
Test name
Test status
Simulation time 31329336 ps
CPU time 0.8 seconds
Started Aug 08 05:41:45 PM PDT 24
Finished Aug 08 05:41:46 PM PDT 24
Peak memory 206792 kb
Host smart-28e83eae-7dd5-4e82-aee8-780d65d9f85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62533099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.62533099 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.2563883653
Short name T1077
Test name
Test status
Simulation time 15454192 ps
CPU time 0.79 seconds
Started Aug 08 05:41:46 PM PDT 24
Finished Aug 08 05:41:46 PM PDT 24
Peak memory 206756 kb
Host smart-cc44e0ba-8fa2-4f71-b1e3-0c06fa56de02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563883653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2563883653 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2347045720
Short name T1162
Test name
Test status
Simulation time 81510166 ps
CPU time 2.6 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 216296 kb
Host smart-af4e203a-6fb8-4317-a522-8d68df35eb23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347045720 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.2347045720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.565605209
Short name T1169
Test name
Test status
Simulation time 157003281 ps
CPU time 1.19 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:16 PM PDT 24
Peak memory 206772 kb
Host smart-64e8613f-b39f-433b-83e6-12f8d47d01b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565605209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.565605209 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3331845121
Short name T1204
Test name
Test status
Simulation time 24462869 ps
CPU time 0.79 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:16 PM PDT 24
Peak memory 206680 kb
Host smart-ac3c67c0-9b92-4caf-8b8d-b1904a9d5e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331845121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3331845121 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.891470756
Short name T1091
Test name
Test status
Simulation time 223923896 ps
CPU time 2.6 seconds
Started Aug 08 05:41:16 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 215216 kb
Host smart-9bd44bbc-632d-41fc-b16d-11f159194d65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891470756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_
outstanding.891470756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.994576135
Short name T1209
Test name
Test status
Simulation time 76012541 ps
CPU time 1.06 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 215856 kb
Host smart-734e12f6-f160-46fe-a2bf-24d2cbbf69d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994576135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.994576135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3139203332
Short name T1124
Test name
Test status
Simulation time 127040485 ps
CPU time 2 seconds
Started Aug 08 05:41:16 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 215704 kb
Host smart-93df6083-9ea0-4e9a-96e5-4673049087f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139203332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.3139203332 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3192813053
Short name T1057
Test name
Test status
Simulation time 275768434 ps
CPU time 3.31 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:20 PM PDT 24
Peak memory 217428 kb
Host smart-57d2157f-709a-451d-b93c-220ea199f6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192813053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3192813053 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.4132193995
Short name T1188
Test name
Test status
Simulation time 506451495 ps
CPU time 3.05 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 207124 kb
Host smart-a1056599-c9cd-46c7-9e21-924be724793e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132193995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.41321
93995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2470378571
Short name T1202
Test name
Test status
Simulation time 155006155 ps
CPU time 2.25 seconds
Started Aug 08 05:41:19 PM PDT 24
Finished Aug 08 05:41:21 PM PDT 24
Peak memory 216056 kb
Host smart-8c2708f8-f754-40d2-a222-7d1b5e4eff2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470378571 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2470378571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3593727198
Short name T1050
Test name
Test status
Simulation time 16284428 ps
CPU time 1.07 seconds
Started Aug 08 05:41:14 PM PDT 24
Finished Aug 08 05:41:15 PM PDT 24
Peak memory 206964 kb
Host smart-cd4b67e2-4beb-4b93-9dc6-bae8555fe251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593727198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3593727198 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.263305198
Short name T1134
Test name
Test status
Simulation time 37646841 ps
CPU time 0.85 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 206768 kb
Host smart-5afbc403-f25e-4d71-ab8e-fa89d3dde98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263305198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.263305198 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4020482173
Short name T1066
Test name
Test status
Simulation time 389645192 ps
CPU time 2.73 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:16 PM PDT 24
Peak memory 215552 kb
Host smart-c52bcdf0-2de7-4ba5-9ab1-6bf67fd28fd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020482173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.4020482173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3376220771
Short name T1117
Test name
Test status
Simulation time 81878741 ps
CPU time 1.17 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 215596 kb
Host smart-d5a4d5ba-d0c6-4175-a8e1-5cb936b28f5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376220771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3376220771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2997664417
Short name T1101
Test name
Test status
Simulation time 589765592 ps
CPU time 1.65 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 215312 kb
Host smart-c386f855-a0cc-4dc0-a1b6-b1702efb7a1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997664417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2997664417 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.4294323314
Short name T1201
Test name
Test status
Simulation time 125538260 ps
CPU time 2.81 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 215300 kb
Host smart-8e771def-f7fe-4f23-9725-bc16162329b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294323314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.4294323314 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.131247011
Short name T177
Test name
Test status
Simulation time 242061546 ps
CPU time 2.65 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 214936 kb
Host smart-a5b027aa-2eb6-4576-8b68-1001c7861aad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131247011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.131247
011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2175832894
Short name T1130
Test name
Test status
Simulation time 170907727 ps
CPU time 1.47 seconds
Started Aug 08 05:41:19 PM PDT 24
Finished Aug 08 05:41:20 PM PDT 24
Peak memory 215332 kb
Host smart-d01de530-14bb-4224-ab75-caab36648e89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175832894 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.2175832894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2046832398
Short name T1142
Test name
Test status
Simulation time 120514007 ps
CPU time 1.2 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 207112 kb
Host smart-4699079c-4440-42de-8104-a6ee91e4bbc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046832398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2046832398 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1760642190
Short name T1193
Test name
Test status
Simulation time 46525610 ps
CPU time 0.73 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:13 PM PDT 24
Peak memory 206808 kb
Host smart-2f4be79e-60ae-4095-aaad-2334145176b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760642190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1760642190 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2008026173
Short name T1125
Test name
Test status
Simulation time 203804190 ps
CPU time 1.58 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:15 PM PDT 24
Peak memory 215312 kb
Host smart-4eb6ed95-0225-4c21-8078-8b751f964431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008026173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2008026173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2399245700
Short name T1085
Test name
Test status
Simulation time 84078978 ps
CPU time 1.01 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:16 PM PDT 24
Peak memory 207004 kb
Host smart-b7842f8e-7020-4443-b9f9-665b2d62586d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399245700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2399245700 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1016080761
Short name T1174
Test name
Test status
Simulation time 93447775 ps
CPU time 2.06 seconds
Started Aug 08 05:41:16 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 215676 kb
Host smart-baae8cd8-5c16-4310-8701-0dc6f1480ea1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016080761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1016080761 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1856844695
Short name T1154
Test name
Test status
Simulation time 94214792 ps
CPU time 2.32 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 215356 kb
Host smart-e096eafa-3f2e-4317-8f2f-6c8b52ec4787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856844695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1856844695 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.614958656
Short name T121
Test name
Test status
Simulation time 354982097 ps
CPU time 3.83 seconds
Started Aug 08 05:41:14 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 207208 kb
Host smart-23756563-8f92-4389-9658-81ac06c05a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614958656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.614958
656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2002325561
Short name T1129
Test name
Test status
Simulation time 120795788 ps
CPU time 2.48 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:20 PM PDT 24
Peak memory 216780 kb
Host smart-22f8cb73-a869-43c2-9569-88d2d5b8aa2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002325561 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2002325561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2727497364
Short name T1088
Test name
Test status
Simulation time 18978562 ps
CPU time 0.94 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:16 PM PDT 24
Peak memory 206808 kb
Host smart-6e170a1e-5f98-46fe-9119-b992cb5f11da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727497364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2727497364 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3089950916
Short name T1055
Test name
Test status
Simulation time 38259377 ps
CPU time 0.76 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:16 PM PDT 24
Peak memory 206784 kb
Host smart-e4dca12d-b794-4513-9066-c2f3d06db42f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089950916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3089950916 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2033384140
Short name T152
Test name
Test status
Simulation time 141762532 ps
CPU time 1.62 seconds
Started Aug 08 05:41:16 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 215452 kb
Host smart-980b6021-02db-463c-a490-93291a180807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033384140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.2033384140 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2949889050
Short name T106
Test name
Test status
Simulation time 86171185 ps
CPU time 1.15 seconds
Started Aug 08 05:41:12 PM PDT 24
Finished Aug 08 05:41:14 PM PDT 24
Peak memory 215644 kb
Host smart-41a5379c-1b72-4e86-a935-f615fb0b6f17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949889050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2949889050 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.67471221
Short name T1079
Test name
Test status
Simulation time 110313887 ps
CPU time 1.74 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 215592 kb
Host smart-16721ad8-eadb-47a6-bc0a-fab5ab3872ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67471221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_s
hadow_reg_errors_with_csr_rw.67471221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.95868737
Short name T1206
Test name
Test status
Simulation time 251276839 ps
CPU time 3.05 seconds
Started Aug 08 05:41:18 PM PDT 24
Finished Aug 08 05:41:22 PM PDT 24
Peak memory 219152 kb
Host smart-74a6fa95-8326-4abb-bb01-b514d2bf0a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95868737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.95868737 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.126766286
Short name T122
Test name
Test status
Simulation time 94214682 ps
CPU time 2.55 seconds
Started Aug 08 05:41:14 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 215384 kb
Host smart-74c4d137-5c04-4785-ba5e-5ea07a3a8fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126766286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.126766
286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3835050250
Short name T1153
Test name
Test status
Simulation time 303537361 ps
CPU time 2.11 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 216216 kb
Host smart-947900b6-abbe-4d08-a3f2-9e684b45f41c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835050250 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3835050250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3326030337
Short name T1051
Test name
Test status
Simulation time 25819333 ps
CPU time 0.96 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 206844 kb
Host smart-d47d79a7-228c-4e51-bcf4-56b8520ee367
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326030337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3326030337 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.2199722512
Short name T1071
Test name
Test status
Simulation time 34320936 ps
CPU time 0.73 seconds
Started Aug 08 05:41:18 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 206780 kb
Host smart-95db6dda-3b78-4372-83c5-e17f85bcec1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199722512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2199722512 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1704214860
Short name T1147
Test name
Test status
Simulation time 106016902 ps
CPU time 1.63 seconds
Started Aug 08 05:41:16 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 215276 kb
Host smart-de434028-6650-44e4-9a4a-3f28af5f485a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704214860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.1704214860 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.612509826
Short name T111
Test name
Test status
Simulation time 186347102 ps
CPU time 1.29 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 215548 kb
Host smart-197eb2a5-7f0f-4f76-a992-7e11b8342638
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612509826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.612509826 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2976441851
Short name T1070
Test name
Test status
Simulation time 91766752 ps
CPU time 2.43 seconds
Started Aug 08 05:41:17 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 223660 kb
Host smart-8e30f4bb-ec62-4a52-9ddc-20f5e3d914fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976441851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.2976441851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.511817637
Short name T1200
Test name
Test status
Simulation time 55978264 ps
CPU time 1.9 seconds
Started Aug 08 05:41:15 PM PDT 24
Finished Aug 08 05:41:17 PM PDT 24
Peak memory 215300 kb
Host smart-2a229228-81f1-4c54-898a-e31c0bb62847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511817637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.511817637 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2068271476
Short name T178
Test name
Test status
Simulation time 107835095 ps
CPU time 4.03 seconds
Started Aug 08 05:41:13 PM PDT 24
Finished Aug 08 05:41:18 PM PDT 24
Peak memory 215336 kb
Host smart-8153336e-4625-4b75-8b26-0f6d084686ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068271476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.20682
71476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.4003149355
Short name T842
Test name
Test status
Simulation time 53558627 ps
CPU time 0.77 seconds
Started Aug 08 06:23:05 PM PDT 24
Finished Aug 08 06:23:06 PM PDT 24
Peak memory 205220 kb
Host smart-0ef54bbd-a5a1-4385-b297-c0892eb96844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003149355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.4003149355 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.3057992884
Short name T23
Test name
Test status
Simulation time 1792305188 ps
CPU time 39.8 seconds
Started Aug 08 06:22:47 PM PDT 24
Finished Aug 08 06:23:27 PM PDT 24
Peak memory 252064 kb
Host smart-758e7173-91ec-4e63-97c0-221da102e58a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057992884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3057992884 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_burst_write.4090625140
Short name T804
Test name
Test status
Simulation time 83975066411 ps
CPU time 823.05 seconds
Started Aug 08 06:22:56 PM PDT 24
Finished Aug 08 06:36:44 PM PDT 24
Peak memory 253016 kb
Host smart-49c2a601-57f2-424c-81cc-c6d7e529c533
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090625140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.4090625140
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.123502627
Short name T651
Test name
Test status
Simulation time 1035034476 ps
CPU time 16.34 seconds
Started Aug 08 06:23:01 PM PDT 24
Finished Aug 08 06:23:18 PM PDT 24
Peak memory 221780 kb
Host smart-1ff6252a-d644-44fd-a9a8-270b682e882b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=123502627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.123502627 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.4173312180
Short name T719
Test name
Test status
Simulation time 4414270849 ps
CPU time 17.95 seconds
Started Aug 08 06:23:08 PM PDT 24
Finished Aug 08 06:23:26 PM PDT 24
Peak memory 223980 kb
Host smart-012dbf65-3135-42fa-8e6b-f452ccc91a95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4173312180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.4173312180 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.2882523851
Short name T486
Test name
Test status
Simulation time 20137508397 ps
CPU time 70.06 seconds
Started Aug 08 06:22:59 PM PDT 24
Finished Aug 08 06:24:09 PM PDT 24
Peak memory 218532 kb
Host smart-ef34a6ef-c98e-493c-a3f2-644ee36c2a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882523851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2882523851 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.2276400367
Short name T324
Test name
Test status
Simulation time 61524822096 ps
CPU time 384.33 seconds
Started Aug 08 06:22:59 PM PDT 24
Finished Aug 08 06:29:23 PM PDT 24
Peak memory 508868 kb
Host smart-74991311-d9b3-4853-8476-294258ba7912
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276400367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.22
76400367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.1477083490
Short name T1013
Test name
Test status
Simulation time 5696940715 ps
CPU time 116.71 seconds
Started Aug 08 06:22:44 PM PDT 24
Finished Aug 08 06:24:41 PM PDT 24
Peak memory 337280 kb
Host smart-79c58037-1d51-437d-8dfa-f52deef54264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477083490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1477083490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.1587949411
Short name T140
Test name
Test status
Simulation time 937573190 ps
CPU time 5.05 seconds
Started Aug 08 06:23:00 PM PDT 24
Finished Aug 08 06:23:06 PM PDT 24
Peak memory 218008 kb
Host smart-1719f5bc-cb1c-41cb-8b17-1bb08011ef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587949411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.1587949411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.216871341
Short name T40
Test name
Test status
Simulation time 44275303 ps
CPU time 1.32 seconds
Started Aug 08 06:23:01 PM PDT 24
Finished Aug 08 06:23:03 PM PDT 24
Peak memory 218640 kb
Host smart-e75eb57c-fbec-41db-b98c-3f2b05ed4573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216871341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.216871341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.1735046344
Short name T623
Test name
Test status
Simulation time 8550574669 ps
CPU time 219.03 seconds
Started Aug 08 06:23:03 PM PDT 24
Finished Aug 08 06:26:43 PM PDT 24
Peak memory 550524 kb
Host smart-1131f889-e35c-43c8-a4a2-a45328c9964a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735046344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.1735046344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.1243297404
Short name T1031
Test name
Test status
Simulation time 1676154586 ps
CPU time 44.63 seconds
Started Aug 08 06:23:07 PM PDT 24
Finished Aug 08 06:23:52 PM PDT 24
Peak memory 236788 kb
Host smart-46ff5cf2-f56d-4ae4-8dc0-81dc01be3a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243297404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1243297404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1909705104
Short name T11
Test name
Test status
Simulation time 12062848145 ps
CPU time 31.39 seconds
Started Aug 08 06:23:04 PM PDT 24
Finished Aug 08 06:23:35 PM PDT 24
Peak memory 248096 kb
Host smart-593d1d09-172d-491a-80ae-1a43aa56dd06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909705104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1909705104 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.1859055861
Short name T694
Test name
Test status
Simulation time 12600254145 ps
CPU time 180.03 seconds
Started Aug 08 06:23:12 PM PDT 24
Finished Aug 08 06:26:12 PM PDT 24
Peak memory 388576 kb
Host smart-ffa662ad-7699-49a4-934a-04f40b6c089a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859055861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1859055861 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.1782188308
Short name T718
Test name
Test status
Simulation time 4502716876 ps
CPU time 42.64 seconds
Started Aug 08 06:22:44 PM PDT 24
Finished Aug 08 06:23:26 PM PDT 24
Peak memory 217972 kb
Host smart-9a09eb1d-2484-4563-b8f1-3c07ea408824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782188308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1782188308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.1449316988
Short name T254
Test name
Test status
Simulation time 1018648324 ps
CPU time 5.5 seconds
Started Aug 08 06:23:05 PM PDT 24
Finished Aug 08 06:23:11 PM PDT 24
Peak memory 217996 kb
Host smart-98273da2-2512-45db-8f6e-67c748196747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449316988 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.1449316988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2244085869
Short name T233
Test name
Test status
Simulation time 220097796 ps
CPU time 4.07 seconds
Started Aug 08 06:23:05 PM PDT 24
Finished Aug 08 06:23:09 PM PDT 24
Peak memory 218060 kb
Host smart-a17734d6-8cd9-4eb1-8551-b2e0a86194b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244085869 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2244085869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.2349085784
Short name T194
Test name
Test status
Simulation time 36973582949 ps
CPU time 1873.61 seconds
Started Aug 08 06:22:58 PM PDT 24
Finished Aug 08 06:54:12 PM PDT 24
Peak memory 1197188 kb
Host smart-1febee65-be42-44e7-a03f-f7235c1c11ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2349085784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2349085784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.2603428910
Short name T558
Test name
Test status
Simulation time 78025564549 ps
CPU time 2680.53 seconds
Started Aug 08 06:23:07 PM PDT 24
Finished Aug 08 07:07:48 PM PDT 24
Peak memory 3005444 kb
Host smart-2ba5b334-b8cb-4957-8b4e-d9abb906e1c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2603428910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2603428910 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.2810617339
Short name T229
Test name
Test status
Simulation time 137632671270 ps
CPU time 1366.65 seconds
Started Aug 08 06:23:12 PM PDT 24
Finished Aug 08 06:45:59 PM PDT 24
Peak memory 928020 kb
Host smart-b13abd2b-cb48-491b-bad1-dccfa261ba7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2810617339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2810617339 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.3485296244
Short name T465
Test name
Test status
Simulation time 65010915248 ps
CPU time 1255.15 seconds
Started Aug 08 06:23:04 PM PDT 24
Finished Aug 08 06:43:59 PM PDT 24
Peak memory 1714816 kb
Host smart-51be466f-6ee3-47a8-ab32-03dc9eb64e12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3485296244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3485296244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.1872141300
Short name T817
Test name
Test status
Simulation time 222441356787 ps
CPU time 5777.35 seconds
Started Aug 08 06:22:56 PM PDT 24
Finished Aug 08 07:59:15 PM PDT 24
Peak memory 2713620 kb
Host smart-5e01f2ae-1c0a-4a3f-baf7-6c2e3f1e27c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1872141300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1872141300 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.1017536844
Short name T353
Test name
Test status
Simulation time 152693108261 ps
CPU time 8451.54 seconds
Started Aug 08 06:22:53 PM PDT 24
Finished Aug 08 08:43:46 PM PDT 24
Peak memory 6375820 kb
Host smart-a5c1e24e-6832-49d3-8d91-3667da18c30d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1017536844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1017536844 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_app.729374941
Short name T972
Test name
Test status
Simulation time 4323992460 ps
CPU time 51.46 seconds
Started Aug 08 06:23:09 PM PDT 24
Finished Aug 08 06:24:00 PM PDT 24
Peak memory 267704 kb
Host smart-ed18bd00-a206-4143-a00d-2f4ad83a3ec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729374941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.729374941 +enable_masking=0
+sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.1950802243
Short name T247
Test name
Test status
Simulation time 31913133751 ps
CPU time 219.44 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 06:27:02 PM PDT 24
Peak memory 300216 kb
Host smart-0a10aa41-5df0-4a9b-8bce-897d9307af39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950802243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.1950802243 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.2105753342
Short name T349
Test name
Test status
Simulation time 17873051169 ps
CPU time 390.39 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:29:45 PM PDT 24
Peak memory 235068 kb
Host smart-4f067533-a35c-41ed-91ff-c982215a9366
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105753342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2105753342
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3206184738
Short name T782
Test name
Test status
Simulation time 368097178 ps
CPU time 23.82 seconds
Started Aug 08 06:23:18 PM PDT 24
Finished Aug 08 06:23:42 PM PDT 24
Peak memory 223784 kb
Host smart-57b3649b-79e8-4306-8e24-0fe4e766572d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3206184738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3206184738 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1885626018
Short name T506
Test name
Test status
Simulation time 399609438 ps
CPU time 28.52 seconds
Started Aug 08 06:23:15 PM PDT 24
Finished Aug 08 06:23:44 PM PDT 24
Peak memory 223740 kb
Host smart-8d4bca86-a75b-4787-930d-2d06edb02955
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1885626018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1885626018 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.2082888391
Short name T514
Test name
Test status
Simulation time 11254501268 ps
CPU time 28.07 seconds
Started Aug 08 06:23:11 PM PDT 24
Finished Aug 08 06:23:39 PM PDT 24
Peak memory 218316 kb
Host smart-1d73849a-aa78-4b46-9b55-215d0299c0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082888391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2082888391 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.1660784498
Short name T1011
Test name
Test status
Simulation time 777885981 ps
CPU time 12.25 seconds
Started Aug 08 06:23:37 PM PDT 24
Finished Aug 08 06:23:50 PM PDT 24
Peak memory 223996 kb
Host smart-32a316ad-a9d1-421f-8f1d-6ca153a449c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660784498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.16
60784498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.491614079
Short name T878
Test name
Test status
Simulation time 13210844040 ps
CPU time 113.82 seconds
Started Aug 08 06:23:02 PM PDT 24
Finished Aug 08 06:24:56 PM PDT 24
Peak memory 325772 kb
Host smart-550e0eda-3602-43d7-8f27-cf7a4a70a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491614079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.491614079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.3698182816
Short name T69
Test name
Test status
Simulation time 1841577518 ps
CPU time 8.46 seconds
Started Aug 08 06:23:08 PM PDT 24
Finished Aug 08 06:23:16 PM PDT 24
Peak memory 218056 kb
Host smart-9948af18-d827-4096-839c-5df22c62ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698182816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3698182816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.2816193670
Short name T160
Test name
Test status
Simulation time 678202951 ps
CPU time 14.81 seconds
Started Aug 08 06:23:23 PM PDT 24
Finished Aug 08 06:23:38 PM PDT 24
Peak memory 235128 kb
Host smart-fe314091-7f57-46d1-ab77-514cee8aa962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816193670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2816193670 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1899899616
Short name T119
Test name
Test status
Simulation time 4519730819 ps
CPU time 145.32 seconds
Started Aug 08 06:23:11 PM PDT 24
Finished Aug 08 06:25:36 PM PDT 24
Peak memory 426472 kb
Host smart-8b3013d7-bd99-4788-b54d-01ab604e4785
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899899616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1899899616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.895262976
Short name T89
Test name
Test status
Simulation time 60425369047 ps
CPU time 349.89 seconds
Started Aug 08 06:23:15 PM PDT 24
Finished Aug 08 06:29:05 PM PDT 24
Peak memory 512192 kb
Host smart-ba23b7d5-e58c-4fc9-8e2a-c88793de4561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895262976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.895262976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.1233416259
Short name T72
Test name
Test status
Simulation time 1580869734 ps
CPU time 27.65 seconds
Started Aug 08 06:23:07 PM PDT 24
Finished Aug 08 06:23:35 PM PDT 24
Peak memory 241544 kb
Host smart-6090606d-0a9d-41d0-b42a-fef13ef3921a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233416259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1233416259 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.4010891854
Short name T681
Test name
Test status
Simulation time 2891221032 ps
CPU time 214.93 seconds
Started Aug 08 06:23:09 PM PDT 24
Finished Aug 08 06:26:44 PM PDT 24
Peak memory 322396 kb
Host smart-ea89a2f5-9a19-4b89-b315-cb4092911543
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010891854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.4010891854 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.1291001085
Short name T449
Test name
Test status
Simulation time 1006379062 ps
CPU time 5.29 seconds
Started Aug 08 06:23:03 PM PDT 24
Finished Aug 08 06:23:08 PM PDT 24
Peak memory 218208 kb
Host smart-b4e54548-9330-47bf-ae39-6d108a8105a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291001085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1291001085 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.2349610842
Short name T578
Test name
Test status
Simulation time 170253844 ps
CPU time 4.59 seconds
Started Aug 08 06:23:06 PM PDT 24
Finished Aug 08 06:23:11 PM PDT 24
Peak memory 217968 kb
Host smart-04dd2291-a9bb-419e-91e7-eff24ca27097
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349610842 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.2349610842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2878499220
Short name T704
Test name
Test status
Simulation time 263061784 ps
CPU time 4.14 seconds
Started Aug 08 06:23:01 PM PDT 24
Finished Aug 08 06:23:05 PM PDT 24
Peak memory 218052 kb
Host smart-83b75265-3a39-4563-86d6-f74660fb475d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878499220 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2878499220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.4127395613
Short name T525
Test name
Test status
Simulation time 19217332480 ps
CPU time 1998.15 seconds
Started Aug 08 06:23:17 PM PDT 24
Finished Aug 08 06:56:35 PM PDT 24
Peak memory 1207744 kb
Host smart-3e3e2a65-f29b-4377-9c6c-f2f110cf7e75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4127395613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.4127395613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.3443755669
Short name T387
Test name
Test status
Simulation time 17540460741 ps
CPU time 1762.96 seconds
Started Aug 08 06:23:10 PM PDT 24
Finished Aug 08 06:52:34 PM PDT 24
Peak memory 1121864 kb
Host smart-3ade0fe2-4f70-4868-8302-26f49f9e5b06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3443755669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3443755669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.1998807045
Short name T354
Test name
Test status
Simulation time 192797216482 ps
CPU time 2210.05 seconds
Started Aug 08 06:23:13 PM PDT 24
Finished Aug 08 07:00:03 PM PDT 24
Peak memory 2454964 kb
Host smart-1bf955e8-9d78-4cbc-aa79-502b23ed0376
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1998807045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1998807045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.369555870
Short name T447
Test name
Test status
Simulation time 541862434064 ps
CPU time 1258.22 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:44:12 PM PDT 24
Peak memory 1710152 kb
Host smart-52f02683-3fb5-44ee-b16d-0c0b986e4e99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=369555870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.369555870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.1289567069
Short name T17
Test name
Test status
Simulation time 612420360069 ps
CPU time 4783.13 seconds
Started Aug 08 06:23:05 PM PDT 24
Finished Aug 08 07:42:49 PM PDT 24
Peak memory 2193332 kb
Host smart-4791ea89-9498-4357-9f39-781f67be968d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1289567069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1289567069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.4258234335
Short name T943
Test name
Test status
Simulation time 12821095 ps
CPU time 0.77 seconds
Started Aug 08 06:23:38 PM PDT 24
Finished Aug 08 06:23:39 PM PDT 24
Peak memory 205172 kb
Host smart-2b3b3fa4-0408-4d4f-9823-c9e4869e6d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258234335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.4258234335 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.254684126
Short name T138
Test name
Test status
Simulation time 5571984203 ps
CPU time 93.27 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 06:25:09 PM PDT 24
Peak memory 298528 kb
Host smart-ace402d3-e41a-4619-9a45-8d7a569dd362
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254684126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.254684126 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.3841537802
Short name T535
Test name
Test status
Simulation time 24849628480 ps
CPU time 601.53 seconds
Started Aug 08 06:23:32 PM PDT 24
Finished Aug 08 06:33:34 PM PDT 24
Peak memory 237308 kb
Host smart-a1608e39-858e-4516-840c-53ca400b9be8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841537802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.384153780
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.2742581747
Short name T913
Test name
Test status
Simulation time 5868587158 ps
CPU time 28.88 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:24:22 PM PDT 24
Peak memory 223924 kb
Host smart-ab1f619d-165a-4905-b07b-375bd4add602
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2742581747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2742581747 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2244294495
Short name T223
Test name
Test status
Simulation time 1098284709 ps
CPU time 29.01 seconds
Started Aug 08 06:23:42 PM PDT 24
Finished Aug 08 06:24:12 PM PDT 24
Peak memory 223784 kb
Host smart-ec7d5a5f-170c-41f9-aa3b-ce679c800a36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2244294495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2244294495 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.2434026346
Short name T810
Test name
Test status
Simulation time 53085910932 ps
CPU time 365.55 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:29:40 PM PDT 24
Peak memory 516552 kb
Host smart-9a43a290-492b-4a14-8bad-7b0397ce062e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434026346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2
434026346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.871500011
Short name T330
Test name
Test status
Simulation time 295067630 ps
CPU time 2.2 seconds
Started Aug 08 06:23:40 PM PDT 24
Finished Aug 08 06:23:43 PM PDT 24
Peak memory 218384 kb
Host smart-ee10b5b0-7164-46e1-b47f-66bb05726c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871500011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.871500011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.896459834
Short name T981
Test name
Test status
Simulation time 4148765731 ps
CPU time 6.58 seconds
Started Aug 08 06:23:44 PM PDT 24
Finished Aug 08 06:23:50 PM PDT 24
Peak memory 219100 kb
Host smart-98e12d52-86de-446f-a52c-44398a892500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896459834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.896459834 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.4235164019
Short name T1045
Test name
Test status
Simulation time 629141499 ps
CPU time 26.05 seconds
Started Aug 08 06:23:47 PM PDT 24
Finished Aug 08 06:24:13 PM PDT 24
Peak memory 235396 kb
Host smart-d520fd84-ce30-4b8a-ad74-3cd67eeddec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235164019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.4235164019 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.1159952036
Short name T971
Test name
Test status
Simulation time 45521489263 ps
CPU time 474.57 seconds
Started Aug 08 06:23:26 PM PDT 24
Finished Aug 08 06:31:21 PM PDT 24
Peak memory 795192 kb
Host smart-f6eead18-1357-43de-ac5c-69559e921cc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159952036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.1159952036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.1670764066
Short name T927
Test name
Test status
Simulation time 7924698014 ps
CPU time 59.43 seconds
Started Aug 08 06:23:40 PM PDT 24
Finished Aug 08 06:24:40 PM PDT 24
Peak memory 269416 kb
Host smart-fb540de9-86ea-415f-a06d-256e4a16c1cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670764066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1670764066 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.1720075638
Short name T420
Test name
Test status
Simulation time 983675714 ps
CPU time 12.95 seconds
Started Aug 08 06:23:38 PM PDT 24
Finished Aug 08 06:23:51 PM PDT 24
Peak memory 219372 kb
Host smart-053df490-1a57-4a24-bcd7-9fd36fd16636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720075638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1720075638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.2883717029
Short name T768
Test name
Test status
Simulation time 11774727093 ps
CPU time 309.88 seconds
Started Aug 08 06:23:39 PM PDT 24
Finished Aug 08 06:28:49 PM PDT 24
Peak memory 516560 kb
Host smart-37d1c1f9-5de9-4f6d-869b-e3b586283428
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2883717029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2883717029 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.1192991547
Short name T636
Test name
Test status
Simulation time 753358178 ps
CPU time 4.64 seconds
Started Aug 08 06:23:41 PM PDT 24
Finished Aug 08 06:23:46 PM PDT 24
Peak memory 218092 kb
Host smart-5e31015e-8c99-41c6-a9c7-dd15fcc0956f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192991547 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.1192991547 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.968047764
Short name T332
Test name
Test status
Simulation time 246529934 ps
CPU time 3.93 seconds
Started Aug 08 06:23:39 PM PDT 24
Finished Aug 08 06:23:43 PM PDT 24
Peak memory 218056 kb
Host smart-53df225c-b8d0-4808-af52-ff3b3f38c0c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968047764 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.kmac_test_vectors_kmac_xof.968047764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.1201815909
Short name T75
Test name
Test status
Simulation time 75169296668 ps
CPU time 1806.16 seconds
Started Aug 08 06:23:52 PM PDT 24
Finished Aug 08 06:53:59 PM PDT 24
Peak memory 1192400 kb
Host smart-a0227109-8be6-48c8-bfff-6782e13f1ca7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1201815909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.1201815909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.3432083662
Short name T527
Test name
Test status
Simulation time 62544450116 ps
CPU time 2713.05 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 07:08:49 PM PDT 24
Peak memory 3028280 kb
Host smart-b4c70bab-5b52-4834-866a-1794dc852857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3432083662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.3432083662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.759022838
Short name T1018
Test name
Test status
Simulation time 27353156323 ps
CPU time 1363.56 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:46:15 PM PDT 24
Peak memory 922172 kb
Host smart-4a45e3d8-2520-4c0a-9fde-d15576e82726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=759022838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.759022838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.1694768324
Short name T246
Test name
Test status
Simulation time 32635854266 ps
CPU time 1254.85 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:44:27 PM PDT 24
Peak memory 1721812 kb
Host smart-1615dde2-9a11-48ac-a5e1-c6dbea197ed1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1694768324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1694768324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.3084681639
Short name T672
Test name
Test status
Simulation time 147303655911 ps
CPU time 8317.04 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 08:42:13 PM PDT 24
Peak memory 6422472 kb
Host smart-85bf2e30-4473-4d2f-8411-e52edbd16ba1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3084681639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.3084681639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.1805519362
Short name T640
Test name
Test status
Simulation time 41248427 ps
CPU time 0.78 seconds
Started Aug 08 06:23:48 PM PDT 24
Finished Aug 08 06:23:49 PM PDT 24
Peak memory 205432 kb
Host smart-64b33c43-8fd8-4b57-afbe-776027eae7ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805519362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1805519362 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.983926013
Short name T603
Test name
Test status
Simulation time 2372661108 ps
CPU time 104.95 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:25:42 PM PDT 24
Peak memory 265072 kb
Host smart-11327081-2ad7-4ffc-9b99-21b40ddcf23c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983926013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.983926013 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.2022976472
Short name T245
Test name
Test status
Simulation time 8598896095 ps
CPU time 163.98 seconds
Started Aug 08 06:23:48 PM PDT 24
Finished Aug 08 06:26:32 PM PDT 24
Peak memory 228208 kb
Host smart-f76a4171-da52-4e3a-a695-2af80449efeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022976472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.202297647
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.1773449343
Short name T509
Test name
Test status
Simulation time 399985859 ps
CPU time 10.43 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:23:41 PM PDT 24
Peak memory 220320 kb
Host smart-14198cc1-c056-4d5d-bae3-57d6ae7d3c64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1773449343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1773449343 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2590777527
Short name T433
Test name
Test status
Simulation time 99915792 ps
CPU time 1.66 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:23:36 PM PDT 24
Peak memory 215648 kb
Host smart-29212d72-085b-49ad-b940-328fee5be8cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590777527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2590777527 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.529143827
Short name T979
Test name
Test status
Simulation time 40530190991 ps
CPU time 144.99 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:26:18 PM PDT 24
Peak memory 339056 kb
Host smart-a116a536-3823-4469-9fdf-fe862a2bc804
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529143827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.52
9143827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.4137270005
Short name T978
Test name
Test status
Simulation time 53588119512 ps
CPU time 142.69 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:26:20 PM PDT 24
Peak memory 361104 kb
Host smart-80514cae-a0b6-404a-9436-b3a725539c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137270005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.4137270005 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.1988038901
Short name T480
Test name
Test status
Simulation time 111216947 ps
CPU time 1.65 seconds
Started Aug 08 06:23:37 PM PDT 24
Finished Aug 08 06:23:39 PM PDT 24
Peak memory 217144 kb
Host smart-885257c3-725c-472e-a722-36bf9a176910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988038901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1988038901 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.4076909177
Short name T1004
Test name
Test status
Simulation time 260507045368 ps
CPU time 596.95 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:33:48 PM PDT 24
Peak memory 958544 kb
Host smart-e75db964-86c5-4bab-bdcc-dd478bce0f04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076909177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.4076909177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2950143599
Short name T579
Test name
Test status
Simulation time 9377845347 ps
CPU time 68.74 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 06:24:33 PM PDT 24
Peak memory 284260 kb
Host smart-5db4d01d-8eab-4e9f-a158-404aa3591e61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950143599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2950143599 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.1255676509
Short name T252
Test name
Test status
Simulation time 1442699936 ps
CPU time 40.98 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:24:16 PM PDT 24
Peak memory 218148 kb
Host smart-c9917a9a-b0db-4843-ad5a-676c790cd989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255676509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1255676509 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.2202937774
Short name T397
Test name
Test status
Simulation time 102583035306 ps
CPU time 740.66 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:36:24 PM PDT 24
Peak memory 1000384 kb
Host smart-1292d420-53df-46ac-b05b-674f79727ade
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2202937774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2202937774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.2358184147
Short name T320
Test name
Test status
Simulation time 2414565417 ps
CPU time 4.97 seconds
Started Aug 08 06:23:30 PM PDT 24
Finished Aug 08 06:23:35 PM PDT 24
Peak memory 218092 kb
Host smart-aab12191-cca3-4158-9595-7ad7aa81dafe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358184147 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.2358184147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2988866073
Short name T239
Test name
Test status
Simulation time 232235731 ps
CPU time 4.22 seconds
Started Aug 08 06:23:30 PM PDT 24
Finished Aug 08 06:23:35 PM PDT 24
Peak memory 218072 kb
Host smart-156e7d1d-dc8a-4c8b-80c0-d55bad0cf332
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988866073 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2988866073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.1479550400
Short name T423
Test name
Test status
Simulation time 19022056345 ps
CPU time 1895.19 seconds
Started Aug 08 06:23:46 PM PDT 24
Finished Aug 08 06:55:21 PM PDT 24
Peak memory 1207440 kb
Host smart-30ca009c-10de-468b-ab4b-42b242cfeeee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1479550400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.1479550400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.3254402751
Short name T385
Test name
Test status
Simulation time 384510158457 ps
CPU time 3292.94 seconds
Started Aug 08 06:23:42 PM PDT 24
Finished Aug 08 07:18:35 PM PDT 24
Peak memory 3081748 kb
Host smart-0a7762cc-4c7d-47c0-ad67-ef05644e8b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3254402751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3254402751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.2006430781
Short name T210
Test name
Test status
Simulation time 1014153973409 ps
CPU time 2646.05 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 07:07:42 PM PDT 24
Peak memory 2416904 kb
Host smart-9d4f0924-53ad-4323-bd09-ae61bbe302ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2006430781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.2006430781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.3763903777
Short name T653
Test name
Test status
Simulation time 175124419209 ps
CPU time 1315.29 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:45:48 PM PDT 24
Peak memory 1708652 kb
Host smart-5a9ed835-87a7-4bae-a067-66c958ca650c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3763903777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3763903777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.1682265820
Short name T1043
Test name
Test status
Simulation time 43715259521 ps
CPU time 4710.1 seconds
Started Aug 08 06:23:38 PM PDT 24
Finished Aug 08 07:42:09 PM PDT 24
Peak memory 2249904 kb
Host smart-b3ccaad5-4eed-4470-a385-16f2440aa9e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1682265820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1682265820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.3916302777
Short name T158
Test name
Test status
Simulation time 17755892 ps
CPU time 0.79 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:23:35 PM PDT 24
Peak memory 205212 kb
Host smart-554896ab-1f0f-4f85-a6a9-ed59a16b2f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916302777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3916302777 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_burst_write.1013112914
Short name T568
Test name
Test status
Simulation time 55572622448 ps
CPU time 931.16 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:39:06 PM PDT 24
Peak memory 252908 kb
Host smart-a5ddc35c-1b7c-4f6b-95b6-2e75630f5bc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013112914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.101311291
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3832350340
Short name T1042
Test name
Test status
Simulation time 1573634858 ps
CPU time 32 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:24:07 PM PDT 24
Peak memory 223752 kb
Host smart-b549b2c3-21d5-4771-9cc1-a9bac4367005
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3832350340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3832350340 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.4112379946
Short name T670
Test name
Test status
Simulation time 516027458 ps
CPU time 37.66 seconds
Started Aug 08 06:23:38 PM PDT 24
Finished Aug 08 06:24:15 PM PDT 24
Peak memory 223780 kb
Host smart-6e1fc34d-953c-4ca6-9b00-024316cd6a80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4112379946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.4112379946 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.3981717517
Short name T665
Test name
Test status
Simulation time 15535777389 ps
CPU time 355.94 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:29:47 PM PDT 24
Peak memory 517900 kb
Host smart-ce3ab9e1-a387-40c0-ba49-6a17739851f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981717517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3
981717517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.4073230325
Short name T545
Test name
Test status
Simulation time 45402252345 ps
CPU time 284.56 seconds
Started Aug 08 06:23:45 PM PDT 24
Finished Aug 08 06:28:30 PM PDT 24
Peak memory 476904 kb
Host smart-cbc1d38c-ee2b-48c7-99a6-a6e2da66fa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073230325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.4073230325 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.4085143979
Short name T66
Test name
Test status
Simulation time 892527866 ps
CPU time 2.07 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:23:52 PM PDT 24
Peak memory 218128 kb
Host smart-ee0f53f0-8bde-46ac-ad43-d6efbe66c918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085143979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.4085143979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.217154370
Short name T907
Test name
Test status
Simulation time 120293182 ps
CPU time 1.25 seconds
Started Aug 08 06:23:54 PM PDT 24
Finished Aug 08 06:23:55 PM PDT 24
Peak memory 219128 kb
Host smart-2cfa4101-e6e7-4ebe-a42f-fb3dc41a39d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217154370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.217154370 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.2785393162
Short name T582
Test name
Test status
Simulation time 1135945377171 ps
CPU time 2647.57 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 07:07:42 PM PDT 24
Peak memory 2293764 kb
Host smart-88809cb8-fae3-4abc-8a0f-0f1870a7ae26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785393162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.2785393162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.2138865470
Short name T226
Test name
Test status
Simulation time 66291518676 ps
CPU time 453.35 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:31:07 PM PDT 24
Peak memory 627232 kb
Host smart-34918153-230c-47f3-a513-ccbc625397da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138865470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2138865470 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.3335604116
Short name T984
Test name
Test status
Simulation time 456373993 ps
CPU time 23.96 seconds
Started Aug 08 06:23:32 PM PDT 24
Finished Aug 08 06:23:56 PM PDT 24
Peak memory 218068 kb
Host smart-dc33323f-ff10-4781-924d-d4fb47d884a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335604116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3335604116 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.2734293177
Short name T159
Test name
Test status
Simulation time 41406292283 ps
CPU time 443.25 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:31:16 PM PDT 24
Peak memory 382208 kb
Host smart-d1248702-bb46-463d-ba3e-9f7a7d1098f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2734293177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2734293177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.1082576228
Short name T580
Test name
Test status
Simulation time 225039992 ps
CPU time 4.47 seconds
Started Aug 08 06:23:32 PM PDT 24
Finished Aug 08 06:23:37 PM PDT 24
Peak memory 218048 kb
Host smart-2e4dbf00-07f1-4f84-9c9a-887a55b3df57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082576228 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.1082576228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1023745197
Short name T554
Test name
Test status
Simulation time 346870142 ps
CPU time 3.95 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 06:23:40 PM PDT 24
Peak memory 218076 kb
Host smart-2d5a70be-bfb7-45ae-a389-823a13da7d4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023745197 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1023745197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.3336069486
Short name T829
Test name
Test status
Simulation time 67907834286 ps
CPU time 2049.35 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:57:45 PM PDT 24
Peak memory 1208568 kb
Host smart-5915dbc9-4ce3-4f90-8da1-749240c03354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3336069486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.3336069486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.601039057
Short name T270
Test name
Test status
Simulation time 32490523165 ps
CPU time 1714.9 seconds
Started Aug 08 06:23:58 PM PDT 24
Finished Aug 08 06:52:33 PM PDT 24
Peak memory 1143884 kb
Host smart-d714f2aa-9931-42f8-b3c3-34195e763440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=601039057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.601039057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.3261905148
Short name T832
Test name
Test status
Simulation time 216474064110 ps
CPU time 2058.51 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:57:54 PM PDT 24
Peak memory 2427108 kb
Host smart-dcdca275-e1bd-48a8-9882-d42d00c25914
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3261905148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.3261905148 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.2613805038
Short name T973
Test name
Test status
Simulation time 44291558403 ps
CPU time 1343.79 seconds
Started Aug 08 06:23:44 PM PDT 24
Finished Aug 08 06:46:08 PM PDT 24
Peak memory 1709864 kb
Host smart-d291f0b3-1d92-41f5-99a1-657b6b4a016b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2613805038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.2613805038 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.1034327221
Short name T604
Test name
Test status
Simulation time 228409626183 ps
CPU time 4563.23 seconds
Started Aug 08 06:23:42 PM PDT 24
Finished Aug 08 07:39:46 PM PDT 24
Peak memory 2229172 kb
Host smart-ad07707e-be79-4d1a-86f1-48b8a8f01243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1034327221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.1034327221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.842347907
Short name T858
Test name
Test status
Simulation time 18671138 ps
CPU time 0.87 seconds
Started Aug 08 06:23:51 PM PDT 24
Finished Aug 08 06:23:52 PM PDT 24
Peak memory 205236 kb
Host smart-3f0d6503-6855-417d-b741-1ad4684ae757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842347907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.842347907 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.2872180744
Short name T896
Test name
Test status
Simulation time 17148288959 ps
CPU time 62.75 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:24:52 PM PDT 24
Peak memory 276144 kb
Host smart-d052bc30-c096-4033-b570-da957f648ed0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872180744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2872180744 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.919806887
Short name T950
Test name
Test status
Simulation time 606367472 ps
CPU time 34.28 seconds
Started Aug 08 06:23:46 PM PDT 24
Finished Aug 08 06:24:21 PM PDT 24
Peak memory 223836 kb
Host smart-4727ad12-3349-43bf-bd50-1d67c778a25a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=919806887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.919806887 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.2039504096
Short name T567
Test name
Test status
Simulation time 9439556491 ps
CPU time 39 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 223916 kb
Host smart-81e265b1-68be-4bb4-8f3e-36aaaa83f4a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2039504096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2039504096 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.1434713760
Short name T784
Test name
Test status
Simulation time 45419099149 ps
CPU time 102.02 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:25:18 PM PDT 24
Peak memory 253920 kb
Host smart-0f1ca38c-2e0e-4f20-8c31-b0829adc50cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434713760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1
434713760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2457689273
Short name T137
Test name
Test status
Simulation time 7086085729 ps
CPU time 157.51 seconds
Started Aug 08 06:23:47 PM PDT 24
Finished Aug 08 06:26:25 PM PDT 24
Peak memory 367652 kb
Host smart-9aaded9f-48c9-49e3-888d-46f0bae3c116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457689273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2457689273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.786085869
Short name T411
Test name
Test status
Simulation time 2303774369 ps
CPU time 3.94 seconds
Started Aug 08 06:23:47 PM PDT 24
Finished Aug 08 06:23:51 PM PDT 24
Peak memory 217960 kb
Host smart-d254fd5c-95e1-4567-bb4f-e24dbd7d5053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786085869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.786085869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_sideload.4137334733
Short name T814
Test name
Test status
Simulation time 29356879153 ps
CPU time 154.47 seconds
Started Aug 08 06:23:37 PM PDT 24
Finished Aug 08 06:26:12 PM PDT 24
Peak memory 350176 kb
Host smart-2bcbc8a1-6804-459b-a8ff-cd47087b5750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137334733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.4137334733 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.2875967536
Short name T508
Test name
Test status
Simulation time 1234635667 ps
CPU time 33.64 seconds
Started Aug 08 06:23:32 PM PDT 24
Finished Aug 08 06:24:06 PM PDT 24
Peak memory 218208 kb
Host smart-bfa7d672-7882-4136-8eee-d9382c824a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875967536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2875967536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.3393377313
Short name T617
Test name
Test status
Simulation time 7937087868 ps
CPU time 586.05 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:33:22 PM PDT 24
Peak memory 603732 kb
Host smart-a66efb44-f94e-411f-b046-77c632502d31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3393377313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.3393377313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3409462985
Short name T930
Test name
Test status
Simulation time 1191304508 ps
CPU time 3.82 seconds
Started Aug 08 06:23:38 PM PDT 24
Finished Aug 08 06:23:42 PM PDT 24
Peak memory 218048 kb
Host smart-a3f86a85-c6ef-4c74-8348-7766c9f4db91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409462985 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3409462985 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.4179902013
Short name T740
Test name
Test status
Simulation time 127212944 ps
CPU time 4.28 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:23:39 PM PDT 24
Peak memory 218096 kb
Host smart-82e9a77d-4bbb-4ab5-afa3-f6cb71442364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179902013 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.4179902013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.1434577535
Short name T401
Test name
Test status
Simulation time 39537899823 ps
CPU time 1838.55 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:54:28 PM PDT 24
Peak memory 1204980 kb
Host smart-335c3cf8-9953-4a96-8466-2a0b7cbdd62d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1434577535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1434577535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1337131945
Short name T81
Test name
Test status
Simulation time 178875203962 ps
CPU time 3322.5 seconds
Started Aug 08 06:23:52 PM PDT 24
Finished Aug 08 07:19:15 PM PDT 24
Peak memory 3109812 kb
Host smart-f5bd7850-3419-4052-925f-cbdf343fea32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1337131945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1337131945 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.3079503553
Short name T687
Test name
Test status
Simulation time 14511411341 ps
CPU time 1421.6 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:47:39 PM PDT 24
Peak memory 920732 kb
Host smart-6f4f004b-33da-4fdb-b2d5-5255df474085
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3079503553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.3079503553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.4101484888
Short name T1034
Test name
Test status
Simulation time 25340069877 ps
CPU time 952.78 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:39:46 PM PDT 24
Peak memory 706132 kb
Host smart-b6d8d187-4132-4f1a-a67a-c948020b1ab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4101484888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.4101484888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.3600657946
Short name T762
Test name
Test status
Simulation time 488243711509 ps
CPU time 9995.69 seconds
Started Aug 08 06:23:44 PM PDT 24
Finished Aug 08 09:10:21 PM PDT 24
Peak memory 7765136 kb
Host smart-4b87297d-fa59-49d5-a181-42261b7fa713
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3600657946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.3600657946 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.3843708258
Short name T315
Test name
Test status
Simulation time 87972016499 ps
CPU time 4258.56 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 07:34:52 PM PDT 24
Peak memory 2208728 kb
Host smart-49208bf5-58a5-4e0a-a8a0-c042526035f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3843708258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3843708258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.950552253
Short name T573
Test name
Test status
Simulation time 42308723 ps
CPU time 0.84 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:23:35 PM PDT 24
Peak memory 205240 kb
Host smart-64d308e5-59c5-445d-9dd8-f1411d861a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950552253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.950552253 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.4231848014
Short name T512
Test name
Test status
Simulation time 3857126268 ps
CPU time 72.31 seconds
Started Aug 08 06:23:56 PM PDT 24
Finished Aug 08 06:25:09 PM PDT 24
Peak memory 282048 kb
Host smart-a59cb2ca-a676-4682-90d4-7f050608863c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231848014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.4231848014 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.2340093562
Short name T1040
Test name
Test status
Simulation time 7683674967 ps
CPU time 687.46 seconds
Started Aug 08 06:23:48 PM PDT 24
Finished Aug 08 06:35:16 PM PDT 24
Peak memory 238392 kb
Host smart-cbd1aa31-4a7d-45ae-b6b6-537604893d0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340093562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.234009356
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.789362928
Short name T693
Test name
Test status
Simulation time 1641099205 ps
CPU time 31.39 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:24:06 PM PDT 24
Peak memory 223716 kb
Host smart-2b25fa3f-1f8e-4788-bfae-edc40589254e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=789362928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.789362928 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.3078307942
Short name T833
Test name
Test status
Simulation time 11363360806 ps
CPU time 38.59 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:24:39 PM PDT 24
Peak memory 223672 kb
Host smart-813e1415-9f3c-44fc-966c-989ea71d5cf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078307942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3078307942 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.2855276984
Short name T113
Test name
Test status
Simulation time 10912351473 ps
CPU time 67.02 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:25:08 PM PDT 24
Peak memory 245568 kb
Host smart-faffab7b-0ce4-464a-afd2-85a4e060c0fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855276984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2
855276984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.826823513
Short name T975
Test name
Test status
Simulation time 71176033885 ps
CPU time 251.48 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:28:01 PM PDT 24
Peak memory 447432 kb
Host smart-6d11a57a-60a2-4572-b820-fce206623667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826823513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.826823513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.726146105
Short name T838
Test name
Test status
Simulation time 1210143369 ps
CPU time 4.12 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:24:08 PM PDT 24
Peak memory 217708 kb
Host smart-49f0817e-d266-424c-ae73-ba3ba672ddb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726146105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.726146105 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.1793169432
Short name T529
Test name
Test status
Simulation time 442321070046 ps
CPU time 4297.2 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 07:35:13 PM PDT 24
Peak memory 3703800 kb
Host smart-247f06f9-e655-4a76-9927-c870d1baab31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793169432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.1793169432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.2618844122
Short name T279
Test name
Test status
Simulation time 6241371876 ps
CPU time 186.81 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:26:57 PM PDT 24
Peak memory 387700 kb
Host smart-5bbd55f5-45da-4934-b7d1-d599cf74c314
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618844122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2618844122 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.991478466
Short name T852
Test name
Test status
Simulation time 7678621406 ps
CPU time 42.71 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:24:32 PM PDT 24
Peak memory 217924 kb
Host smart-6163f0e5-e385-4b10-8504-fead31a8742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991478466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.991478466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.3184924396
Short name T939
Test name
Test status
Simulation time 80431330178 ps
CPU time 1496.09 seconds
Started Aug 08 06:23:44 PM PDT 24
Finished Aug 08 06:48:41 PM PDT 24
Peak memory 953348 kb
Host smart-b06ed85c-bf71-4e3c-90e2-0a72d32fa37a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3184924396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3184924396 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.1217897688
Short name T811
Test name
Test status
Simulation time 991217480 ps
CPU time 5.55 seconds
Started Aug 08 06:23:39 PM PDT 24
Finished Aug 08 06:23:45 PM PDT 24
Peak memory 218112 kb
Host smart-d7d3dd30-7519-49a5-b79f-e2244686b93d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217897688 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.1217897688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.3348210206
Short name T352
Test name
Test status
Simulation time 312104963 ps
CPU time 4.36 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:23:39 PM PDT 24
Peak memory 217972 kb
Host smart-eff1c50c-8a8d-4bde-a3bd-d158a58931a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348210206 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.3348210206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.3733350429
Short name T965
Test name
Test status
Simulation time 273865422217 ps
CPU time 3083.18 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 07:14:59 PM PDT 24
Peak memory 3272468 kb
Host smart-490cd5a0-2fbc-46b3-8f1f-33c1cedc0cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3733350429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.3733350429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.1468182237
Short name T880
Test name
Test status
Simulation time 61603568726 ps
CPU time 2663.92 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 07:08:00 PM PDT 24
Peak memory 2949868 kb
Host smart-bf4b72a9-0094-406c-adb8-c0925d579c2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1468182237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1468182237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.4172676753
Short name T938
Test name
Test status
Simulation time 103694274996 ps
CPU time 1296.11 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:45:44 PM PDT 24
Peak memory 909396 kb
Host smart-70cd87c4-4345-4e65-afb8-91af8dca57ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4172676753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.4172676753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.2583188092
Short name T213
Test name
Test status
Simulation time 322975047708 ps
CPU time 1419.71 seconds
Started Aug 08 06:23:55 PM PDT 24
Finished Aug 08 06:47:35 PM PDT 24
Peak memory 1708592 kb
Host smart-bc2ca867-6061-4bc3-a340-8b2d1b11a76e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2583188092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.2583188092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.279801783
Short name T779
Test name
Test status
Simulation time 90061983991 ps
CPU time 4228.27 seconds
Started Aug 08 06:23:42 PM PDT 24
Finished Aug 08 07:34:11 PM PDT 24
Peak memory 2215924 kb
Host smart-84c18ef0-a2d1-4408-ae12-17253fdc610f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=279801783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.279801783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.1208301226
Short name T467
Test name
Test status
Simulation time 45784400 ps
CPU time 0.81 seconds
Started Aug 08 06:23:56 PM PDT 24
Finished Aug 08 06:23:57 PM PDT 24
Peak memory 205248 kb
Host smart-ae75201a-1d42-4d68-91b4-502b1e1ffcdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208301226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1208301226 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.1541860965
Short name T1023
Test name
Test status
Simulation time 2255599073 ps
CPU time 26.18 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:24:27 PM PDT 24
Peak memory 240948 kb
Host smart-3d5df2ee-6b4d-43f0-9bf7-3e572c77ecf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541860965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1541860965 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.3099559954
Short name T147
Test name
Test status
Simulation time 11146186427 ps
CPU time 65.52 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:24:59 PM PDT 24
Peak memory 220940 kb
Host smart-bbc3e0b2-6cff-470d-beba-c95160d2adec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099559954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.309955995
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.741813171
Short name T569
Test name
Test status
Simulation time 6519472962 ps
CPU time 29.71 seconds
Started Aug 08 06:23:54 PM PDT 24
Finished Aug 08 06:24:24 PM PDT 24
Peak memory 223944 kb
Host smart-2b65e4a0-026b-4cbe-a2e6-56b71e36d158
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=741813171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.741813171 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.401408893
Short name T901
Test name
Test status
Simulation time 295087728 ps
CPU time 7.25 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 06:23:43 PM PDT 24
Peak memory 219288 kb
Host smart-04d4c69f-4bfd-4291-888b-cb20687805ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=401408893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.401408893 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.3224623867
Short name T685
Test name
Test status
Simulation time 20114303484 ps
CPU time 197.34 seconds
Started Aug 08 06:23:37 PM PDT 24
Finished Aug 08 06:26:55 PM PDT 24
Peak memory 304624 kb
Host smart-30d05dab-015e-4e8f-b4c9-2fba7790fe9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224623867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3
224623867 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.3532218564
Short name T830
Test name
Test status
Simulation time 7544769876 ps
CPU time 86.14 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:25:00 PM PDT 24
Peak memory 320152 kb
Host smart-22227e23-4bea-479a-8073-92e5d36599b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532218564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3532218564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.822342610
Short name T601
Test name
Test status
Simulation time 794595315 ps
CPU time 2.78 seconds
Started Aug 08 06:23:52 PM PDT 24
Finished Aug 08 06:23:55 PM PDT 24
Peak memory 217664 kb
Host smart-b551efa4-f4c7-4664-9e9a-9fe42e993596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822342610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.822342610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.3518029574
Short name T904
Test name
Test status
Simulation time 57234532 ps
CPU time 1.61 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:24:05 PM PDT 24
Peak memory 218292 kb
Host smart-b80ebf61-f279-4b16-9ca6-8e6febc4384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518029574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3518029574 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1645607013
Short name T794
Test name
Test status
Simulation time 18585457976 ps
CPU time 524.15 seconds
Started Aug 08 06:23:51 PM PDT 24
Finished Aug 08 06:32:36 PM PDT 24
Peak memory 886064 kb
Host smart-ee6f5863-5ae4-4a7e-9185-0d8bd020f74a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645607013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1645607013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.190125601
Short name T43
Test name
Test status
Simulation time 7452394006 ps
CPU time 213.13 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 06:27:10 PM PDT 24
Peak memory 415228 kb
Host smart-826eeb0e-8d1a-42f4-a20f-63277373ee15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190125601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.190125601 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.3338338915
Short name T824
Test name
Test status
Simulation time 7044541675 ps
CPU time 57.94 seconds
Started Aug 08 06:23:37 PM PDT 24
Finished Aug 08 06:24:35 PM PDT 24
Peak memory 220108 kb
Host smart-2fb7dfaa-3ce8-4c47-9d72-64da621ff9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338338915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3338338915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.1621873142
Short name T57
Test name
Test status
Simulation time 26772407940 ps
CPU time 268.46 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:28:26 PM PDT 24
Peak memory 407184 kb
Host smart-9670493d-e0e6-430a-8ea0-153f637eab61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1621873142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1621873142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.4017157649
Short name T293
Test name
Test status
Simulation time 247878011 ps
CPU time 5.36 seconds
Started Aug 08 06:23:52 PM PDT 24
Finished Aug 08 06:23:58 PM PDT 24
Peak memory 218156 kb
Host smart-2413c50b-686d-46f8-8eb2-9bb351dbd6e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017157649 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.4017157649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.96586794
Short name T717
Test name
Test status
Simulation time 260367542 ps
CPU time 5.2 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:23:40 PM PDT 24
Peak memory 217620 kb
Host smart-755ab20e-d783-4165-aa5e-1244fe43da0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96586794 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.kmac_test_vectors_kmac_xof.96586794 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.2718310843
Short name T373
Test name
Test status
Simulation time 334104686597 ps
CPU time 2962.43 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 07:12:58 PM PDT 24
Peak memory 3207088 kb
Host smart-9cd372bd-a010-4cbb-bc3e-187e3d5c4b23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2718310843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.2718310843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.2157309063
Short name T275
Test name
Test status
Simulation time 219244464950 ps
CPU time 1808.67 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:53:44 PM PDT 24
Peak memory 1123500 kb
Host smart-ac07ee09-e978-4106-b077-5de38ace1977
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2157309063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.2157309063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.2470168038
Short name T828
Test name
Test status
Simulation time 26934844057 ps
CPU time 1410.01 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 06:47:05 PM PDT 24
Peak memory 908140 kb
Host smart-c386eb7a-63ab-4b7c-bdde-678f929aff6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2470168038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.2470168038 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2869075245
Short name T404
Test name
Test status
Simulation time 169339260390 ps
CPU time 1486.04 seconds
Started Aug 08 06:23:54 PM PDT 24
Finished Aug 08 06:48:40 PM PDT 24
Peak memory 1719904 kb
Host smart-3b30f4e0-d976-4d70-a62f-06a15701c9e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2869075245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2869075245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.4190292335
Short name T958
Test name
Test status
Simulation time 225985110809 ps
CPU time 9815.03 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 09:07:11 PM PDT 24
Peak memory 6402240 kb
Host smart-7151183c-fcca-4d66-9828-fc191789c7ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4190292335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.4190292335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.5280124
Short name T306
Test name
Test status
Simulation time 43382518 ps
CPU time 0.78 seconds
Started Aug 08 06:23:59 PM PDT 24
Finished Aug 08 06:23:59 PM PDT 24
Peak memory 205228 kb
Host smart-da219367-7fe7-4eb9-89a9-209a9b44b242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5280124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.5280124 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.2933351534
Short name T996
Test name
Test status
Simulation time 5173432989 ps
CPU time 243.88 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:28:10 PM PDT 24
Peak memory 325800 kb
Host smart-93181bba-c077-4797-8e0c-ad11e018c23f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933351534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2933351534 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.3659280375
Short name T3
Test name
Test status
Simulation time 23164149382 ps
CPU time 886.65 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:38:47 PM PDT 24
Peak memory 255136 kb
Host smart-8237ae0b-ff98-4d30-bc75-de7faa86e99e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659280375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.365928037
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.462802458
Short name T359
Test name
Test status
Simulation time 166820124 ps
CPU time 10.79 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:24:12 PM PDT 24
Peak memory 223220 kb
Host smart-0e5eb0d3-2612-4319-b6eb-e9096911462d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=462802458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.462802458 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.2819985566
Short name T627
Test name
Test status
Simulation time 2441040750 ps
CPU time 24.38 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:24:31 PM PDT 24
Peak memory 223732 kb
Host smart-df7919b9-fce8-4f51-a339-851289d0f63f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2819985566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2819985566 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.3726931789
Short name T114
Test name
Test status
Simulation time 16930756943 ps
CPU time 292.55 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:29:01 PM PDT 24
Peak memory 462820 kb
Host smart-8061fc0f-2da5-4f89-918a-549c7667972a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726931789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3
726931789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.460091460
Short name T774
Test name
Test status
Simulation time 9995891810 ps
CPU time 231.02 seconds
Started Aug 08 06:23:54 PM PDT 24
Finished Aug 08 06:27:46 PM PDT 24
Peak memory 445388 kb
Host smart-a9383417-0918-4d3c-b7a3-1d94a545bcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460091460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.460091460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.3674686401
Short name T772
Test name
Test status
Simulation time 652529624 ps
CPU time 1.86 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:24:05 PM PDT 24
Peak memory 217900 kb
Host smart-97cceb63-146b-4be4-92e0-7429947fe5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674686401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3674686401 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.3338018686
Short name T682
Test name
Test status
Simulation time 179738098745 ps
CPU time 804.15 seconds
Started Aug 08 06:23:45 PM PDT 24
Finished Aug 08 06:37:10 PM PDT 24
Peak memory 1200692 kb
Host smart-0fcfbb2c-42e9-49c2-84d9-43aa3588fc78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338018686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.3338018686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.1095947415
Short name T661
Test name
Test status
Simulation time 1385567649 ps
CPU time 40.02 seconds
Started Aug 08 06:24:07 PM PDT 24
Finished Aug 08 06:24:47 PM PDT 24
Peak memory 247908 kb
Host smart-bbe9796e-3344-42e9-a765-db736f9cd047
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095947415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1095947415 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.106422942
Short name T322
Test name
Test status
Simulation time 2729780865 ps
CPU time 32.44 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:24:29 PM PDT 24
Peak memory 218248 kb
Host smart-9dbf730a-d819-441e-8389-5121c2cd5841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106422942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.106422942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.2605151501
Short name T338
Test name
Test status
Simulation time 4151150390 ps
CPU time 83.01 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:25:23 PM PDT 24
Peak memory 267092 kb
Host smart-c649a8cd-0f12-45bc-aaa3-b0c181f50686
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2605151501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2605151501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.1043644919
Short name T609
Test name
Test status
Simulation time 180295138 ps
CPU time 4.45 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:24:05 PM PDT 24
Peak memory 217840 kb
Host smart-b336ebde-0ff1-4305-92a2-8e5bb500bb23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043644919 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.1043644919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2007428341
Short name T791
Test name
Test status
Simulation time 241407430 ps
CPU time 4.14 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:23:54 PM PDT 24
Peak memory 218024 kb
Host smart-33862b65-7a7c-43f2-8602-b9051f5a46fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007428341 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2007428341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.439158072
Short name T195
Test name
Test status
Simulation time 97751990343 ps
CPU time 3443.69 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 07:21:26 PM PDT 24
Peak memory 3184516 kb
Host smart-43947525-5a87-4ad3-bbcf-e2878998bcd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=439158072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.439158072 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.2655481189
Short name T375
Test name
Test status
Simulation time 17350395298 ps
CPU time 1802.86 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:54:04 PM PDT 24
Peak memory 1110600 kb
Host smart-239fb0aa-efbd-4fa0-a9ef-6e372bde568d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2655481189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.2655481189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.961135838
Short name T655
Test name
Test status
Simulation time 96477294171 ps
CPU time 2130.51 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 06:59:36 PM PDT 24
Peak memory 2359640 kb
Host smart-81e216cb-1756-4c6a-8a99-23304bd23227
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=961135838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.961135838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.727802259
Short name T517
Test name
Test status
Simulation time 19879062586 ps
CPU time 926.42 seconds
Started Aug 08 06:23:59 PM PDT 24
Finished Aug 08 06:39:26 PM PDT 24
Peak memory 714796 kb
Host smart-bd16c95b-76fa-4f0f-a189-8445e2aecf8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=727802259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.727802259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.1801068313
Short name T949
Test name
Test status
Simulation time 215341830848 ps
CPU time 8137.01 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 08:39:41 PM PDT 24
Peak memory 6334512 kb
Host smart-b65adbb6-6e95-48be-a288-24669bbbb378
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1801068313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1801068313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.1713052040
Short name T53
Test name
Test status
Simulation time 57800561 ps
CPU time 0.81 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:24:04 PM PDT 24
Peak memory 205208 kb
Host smart-bcdb9205-c7b8-4624-bfd3-51a0f4c95abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713052040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1713052040 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.3844842227
Short name T1007
Test name
Test status
Simulation time 730091022 ps
CPU time 32.34 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:24:23 PM PDT 24
Peak memory 230264 kb
Host smart-b14e20a5-5140-45c7-9871-c886a576e19f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844842227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3844842227 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.1796190491
Short name T48
Test name
Test status
Simulation time 29841330301 ps
CPU time 654.49 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:34:55 PM PDT 24
Peak memory 238460 kb
Host smart-882b222d-124e-4345-a844-60881e4d6046
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796190491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.179619049
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.2771115722
Short name T795
Test name
Test status
Simulation time 913290226 ps
CPU time 23.36 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:24:13 PM PDT 24
Peak memory 225052 kb
Host smart-acf6a4a5-bce5-40c9-ba52-57986205a12b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2771115722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2771115722 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.4004724655
Short name T756
Test name
Test status
Simulation time 7377439511 ps
CPU time 38.99 seconds
Started Aug 08 06:23:56 PM PDT 24
Finished Aug 08 06:24:35 PM PDT 24
Peak memory 231776 kb
Host smart-a22baac6-0104-4f6a-82e7-57fa05bbb418
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4004724655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.4004724655 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.134166746
Short name T935
Test name
Test status
Simulation time 17882993347 ps
CPU time 370.91 seconds
Started Aug 08 06:23:51 PM PDT 24
Finished Aug 08 06:30:02 PM PDT 24
Peak memory 528384 kb
Host smart-86e1c041-727d-48e1-8478-4566f87d1ffb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134166746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.13
4166746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.576107973
Short name T940
Test name
Test status
Simulation time 14884012661 ps
CPU time 375.58 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 06:30:21 PM PDT 24
Peak memory 559220 kb
Host smart-664bf627-659c-4931-81d4-aff0966db552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576107973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.576107973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.3269038447
Short name T442
Test name
Test status
Simulation time 166409211 ps
CPU time 1.51 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:24:11 PM PDT 24
Peak memory 217656 kb
Host smart-7d0880a1-b64e-4872-8c45-2d8814a9bfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269038447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3269038447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.4251474143
Short name T699
Test name
Test status
Simulation time 48593115 ps
CPU time 1.28 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:23:55 PM PDT 24
Peak memory 217332 kb
Host smart-8f0cfb90-9104-4aac-b724-c982c7ca7179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251474143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.4251474143 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.1425056691
Short name T220
Test name
Test status
Simulation time 24188735002 ps
CPU time 1313.14 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 06:45:56 PM PDT 24
Peak memory 963984 kb
Host smart-e3613fe9-4ed4-48e8-ac8a-2a3ef37854b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425056691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.1425056691 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.945396920
Short name T273
Test name
Test status
Simulation time 2361672606 ps
CPU time 86.82 seconds
Started Aug 08 06:23:59 PM PDT 24
Finished Aug 08 06:25:26 PM PDT 24
Peak memory 257908 kb
Host smart-a5993bde-ccc7-4fea-9c0d-790cce566caf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945396920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.945396920 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.30632282
Short name T267
Test name
Test status
Simulation time 638061458 ps
CPU time 14 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:23 PM PDT 24
Peak memory 217652 kb
Host smart-fe3f59f1-c9d3-4be2-9edc-a881b031ea90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30632282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.30632282 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.1609763482
Short name T684
Test name
Test status
Simulation time 134650881243 ps
CPU time 1125.43 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:42:51 PM PDT 24
Peak memory 818064 kb
Host smart-3dbb765a-c981-4c70-bd7b-8dfd8c49f030
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1609763482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1609763482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.810201557
Short name T356
Test name
Test status
Simulation time 169947844 ps
CPU time 4.49 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 06:24:06 PM PDT 24
Peak memory 217612 kb
Host smart-5ca773e4-f361-465f-9db2-78762fd1cdce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810201557 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.kmac_test_vectors_kmac.810201557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.3794533001
Short name T634
Test name
Test status
Simulation time 324673637 ps
CPU time 4.33 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 06:24:06 PM PDT 24
Peak memory 218040 kb
Host smart-19612511-36b7-427d-949f-36a9f04b1e3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794533001 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.3794533001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.1089922190
Short name T771
Test name
Test status
Simulation time 97986419663 ps
CPU time 3107.39 seconds
Started Aug 08 06:23:59 PM PDT 24
Finished Aug 08 07:15:47 PM PDT 24
Peak memory 3188304 kb
Host smart-d2dd72b4-f30d-4e8f-8821-b244295929fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1089922190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1089922190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.1611051284
Short name T523
Test name
Test status
Simulation time 242699580286 ps
CPU time 2755.34 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 07:09:45 PM PDT 24
Peak memory 3026444 kb
Host smart-03d9735e-b4f3-448a-b484-68ed3c036c79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1611051284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.1611051284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.3966347309
Short name T483
Test name
Test status
Simulation time 198797587706 ps
CPU time 2076.59 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:58:40 PM PDT 24
Peak memory 2431044 kb
Host smart-5348283b-8dbc-4425-8348-03d238fb8ed7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3966347309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.3966347309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.686072440
Short name T686
Test name
Test status
Simulation time 126701685158 ps
CPU time 1307.51 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:45:53 PM PDT 24
Peak memory 1740456 kb
Host smart-737074f9-a9a4-4fa7-8cc0-57cf00e41e0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=686072440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.686072440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.2029541251
Short name T215
Test name
Test status
Simulation time 52231206002 ps
CPU time 5240.85 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 07:51:22 PM PDT 24
Peak memory 2645148 kb
Host smart-5a1f9b71-4a7e-4060-9f14-7598197e982b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2029541251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.2029541251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.750332824
Short name T778
Test name
Test status
Simulation time 173778280131 ps
CPU time 4931.01 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 07:46:14 PM PDT 24
Peak memory 2233852 kb
Host smart-6299ece7-b37c-4dcb-94e2-cc218baf8413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=750332824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.750332824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.3724324821
Short name T902
Test name
Test status
Simulation time 49645264 ps
CPU time 0.76 seconds
Started Aug 08 06:23:59 PM PDT 24
Finished Aug 08 06:24:00 PM PDT 24
Peak memory 205248 kb
Host smart-79e0ae22-8266-4a5d-9b54-9ab803966388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724324821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3724324821 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.943208104
Short name T593
Test name
Test status
Simulation time 11946573774 ps
CPU time 220.45 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:27:42 PM PDT 24
Peak memory 433460 kb
Host smart-0ade8e40-3240-4888-a089-7f1e604ab6b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943208104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.943208104 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.3094380296
Short name T450
Test name
Test status
Simulation time 18483047639 ps
CPU time 658.92 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:35:00 PM PDT 24
Peak memory 240448 kb
Host smart-1e41d303-98f5-4b1d-bec9-dcbf03765c09
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094380296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.309438029
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.4171339779
Short name T916
Test name
Test status
Simulation time 1354802094 ps
CPU time 20.29 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:24:21 PM PDT 24
Peak memory 219992 kb
Host smart-bd76ecbd-13ad-4c31-b6f0-94e33d9d9032
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4171339779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.4171339779 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2559107795
Short name T561
Test name
Test status
Simulation time 981560310 ps
CPU time 36.63 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:24:34 PM PDT 24
Peak memory 231184 kb
Host smart-903f3a07-3363-45df-a3ae-1692e4a65ebd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2559107795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2559107795 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.1011476660
Short name T847
Test name
Test status
Simulation time 1755094857 ps
CPU time 65.72 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:25:11 PM PDT 24
Peak memory 247892 kb
Host smart-5a1b259c-4318-4c34-9022-c4e365dfde88
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011476660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1
011476660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.34243059
Short name T571
Test name
Test status
Simulation time 6429566271 ps
CPU time 161.59 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 06:26:47 PM PDT 24
Peak memory 398896 kb
Host smart-0c0bfb8e-c322-4731-8007-251b56118ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34243059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.34243059 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.59897246
Short name T290
Test name
Test status
Simulation time 9804259809 ps
CPU time 6.82 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:24:20 PM PDT 24
Peak memory 217804 kb
Host smart-e35cafd9-e86b-4e9b-bd68-5a45b6e9be69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59897246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.59897246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.28577476
Short name T539
Test name
Test status
Simulation time 78341727 ps
CPU time 1.45 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:23:59 PM PDT 24
Peak memory 217112 kb
Host smart-e1c1cb4f-8ed0-4a1f-9e68-9145e053729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28577476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.28577476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2855682161
Short name T1002
Test name
Test status
Simulation time 25944023199 ps
CPU time 2084.79 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:58:45 PM PDT 24
Peak memory 1342400 kb
Host smart-d579dd35-c02e-4110-9680-a39c8d26643c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855682161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2855682161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.2237366051
Short name T871
Test name
Test status
Simulation time 229983957763 ps
CPU time 441.5 seconds
Started Aug 08 06:23:52 PM PDT 24
Finished Aug 08 06:31:14 PM PDT 24
Peak memory 585592 kb
Host smart-9a38319b-6de2-43fa-aa87-8b0c199e1dbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237366051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2237366051 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.3680640187
Short name T552
Test name
Test status
Simulation time 3412996102 ps
CPU time 50.54 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:24:57 PM PDT 24
Peak memory 217964 kb
Host smart-e45b4699-2630-438d-bee3-4e44ba9aa128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680640187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3680640187 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.2823623515
Short name T135
Test name
Test status
Simulation time 82321471717 ps
CPU time 575 seconds
Started Aug 08 06:23:48 PM PDT 24
Finished Aug 08 06:33:23 PM PDT 24
Peak memory 369652 kb
Host smart-b2e87681-3d0d-44c4-a7ec-9112b24a93e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2823623515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2823623515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.352766904
Short name T12
Test name
Test status
Simulation time 664424222 ps
CPU time 4.87 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:23:54 PM PDT 24
Peak memory 217748 kb
Host smart-806f8190-7d2d-4fe7-8b6e-f2cad48af49f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352766904 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_test_vectors_kmac.352766904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.2479174562
Short name T219
Test name
Test status
Simulation time 240311682 ps
CPU time 5.4 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 218136 kb
Host smart-601ed590-6f5d-4fa9-a320-5615c9e430d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479174562 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.2479174562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.2649275742
Short name T947
Test name
Test status
Simulation time 19621469890 ps
CPU time 1927.83 seconds
Started Aug 08 06:23:59 PM PDT 24
Finished Aug 08 06:56:07 PM PDT 24
Peak memory 1208144 kb
Host smart-2e0e0226-4d6b-4db1-a358-ea9943d033a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2649275742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.2649275742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.3209536766
Short name T414
Test name
Test status
Simulation time 251774253236 ps
CPU time 2518.55 seconds
Started Aug 08 06:24:04 PM PDT 24
Finished Aug 08 07:06:03 PM PDT 24
Peak memory 3017264 kb
Host smart-e5606747-905f-4a59-89a6-89ec56b27174
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3209536766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.3209536766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.1899041017
Short name T563
Test name
Test status
Simulation time 776103205215 ps
CPU time 2405.69 seconds
Started Aug 08 06:23:58 PM PDT 24
Finished Aug 08 07:04:04 PM PDT 24
Peak memory 2377876 kb
Host smart-944463be-8629-4372-8a8d-2d11a7385b10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1899041017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.1899041017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.266366879
Short name T481
Test name
Test status
Simulation time 222499819896 ps
CPU time 1509.05 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:49:12 PM PDT 24
Peak memory 1724152 kb
Host smart-03b10dc3-84db-4b75-84ed-777fba86bc58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=266366879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.266366879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.1561137064
Short name T402
Test name
Test status
Simulation time 51412782807 ps
CPU time 5323.42 seconds
Started Aug 08 06:23:54 PM PDT 24
Finished Aug 08 07:52:38 PM PDT 24
Peak memory 2662368 kb
Host smart-bfaf280c-525c-4334-8708-ee2ecfceedf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1561137064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.1561137064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.380268982
Short name T257
Test name
Test status
Simulation time 659747874772 ps
CPU time 10730.4 seconds
Started Aug 08 06:23:55 PM PDT 24
Finished Aug 08 09:22:47 PM PDT 24
Peak memory 6433432 kb
Host smart-b0a14563-3d27-44b9-bf37-8a00a8f01eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=380268982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.380268982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.627787133
Short name T363
Test name
Test status
Simulation time 17776470 ps
CPU time 0.79 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:24:02 PM PDT 24
Peak memory 205180 kb
Host smart-90f1297f-a7ed-41c5-b22c-dd835d78fef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627787133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.627787133 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.461842393
Short name T763
Test name
Test status
Simulation time 11196088185 ps
CPU time 135.16 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:26:28 PM PDT 24
Peak memory 330368 kb
Host smart-95d792a3-191e-45a2-82eb-9e6c1176a871
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461842393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.461842393 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.4228361221
Short name T503
Test name
Test status
Simulation time 9201907647 ps
CPU time 747.71 seconds
Started Aug 08 06:24:04 PM PDT 24
Finished Aug 08 06:36:32 PM PDT 24
Peak memory 239892 kb
Host smart-4ea306ed-25c0-4d81-b63d-c22773da7a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228361221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.422836122
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.4042314833
Short name T622
Test name
Test status
Simulation time 1281354057 ps
CPU time 13.93 seconds
Started Aug 08 06:24:07 PM PDT 24
Finished Aug 08 06:24:21 PM PDT 24
Peak memory 221836 kb
Host smart-8b05ff31-a4d5-4a1e-bdc3-a6ab6912303d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4042314833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.4042314833 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.1779295218
Short name T891
Test name
Test status
Simulation time 1230953929 ps
CPU time 9 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:24:15 PM PDT 24
Peak memory 219260 kb
Host smart-ad4717d1-c7c6-4c0a-bd0f-952fa7649902
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1779295218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1779295218 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.2249525729
Short name T1026
Test name
Test status
Simulation time 9055465860 ps
CPU time 69.64 seconds
Started Aug 08 06:24:04 PM PDT 24
Finished Aug 08 06:25:13 PM PDT 24
Peak memory 282792 kb
Host smart-67b59e8f-10d8-4a3b-8fa7-84b457e4e1c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249525729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2
249525729 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.2939347572
Short name T551
Test name
Test status
Simulation time 19896211654 ps
CPU time 278.97 seconds
Started Aug 08 06:23:48 PM PDT 24
Finished Aug 08 06:28:27 PM PDT 24
Peak memory 482036 kb
Host smart-03478116-ffef-4fc6-a7b2-14962f51b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939347572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2939347572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.3798859280
Short name T132
Test name
Test status
Simulation time 357548465 ps
CPU time 2.21 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:24:12 PM PDT 24
Peak memory 217592 kb
Host smart-a71c52db-ea15-4261-b605-ac7e611f6ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798859280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3798859280 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.1984047385
Short name T62
Test name
Test status
Simulation time 120768256 ps
CPU time 1.2 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:10 PM PDT 24
Peak memory 217180 kb
Host smart-f20bb4a0-6316-443c-9ad9-a95536b8e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984047385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1984047385 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.18566530
Short name T643
Test name
Test status
Simulation time 175509416108 ps
CPU time 3861.72 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 07:28:27 PM PDT 24
Peak memory 3246212 kb
Host smart-708ac7ae-158f-4d94-8ee1-13172809672f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and
_output.18566530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.1349019201
Short name T434
Test name
Test status
Simulation time 24535996128 ps
CPU time 175.02 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:26:53 PM PDT 24
Peak memory 373356 kb
Host smart-f154fd35-a457-4ab1-bbf2-983fda8979e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349019201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.1349019201 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_stress_all.281014823
Short name T710
Test name
Test status
Simulation time 83288450641 ps
CPU time 529.03 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:32:49 PM PDT 24
Peak memory 392796 kb
Host smart-282833f9-c205-4c93-94e0-1e16ef805e6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=281014823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.281014823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.2450414180
Short name T1010
Test name
Test status
Simulation time 658657678 ps
CPU time 4.72 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 218056 kb
Host smart-9327789a-d42b-4d3d-adcd-89e4eb097210
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450414180 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.2450414180 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3486435978
Short name T209
Test name
Test status
Simulation time 733471015 ps
CPU time 4.04 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:24:01 PM PDT 24
Peak memory 217684 kb
Host smart-cb061d5a-e2da-4e30-bff8-4420925d9d13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486435978 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3486435978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.3997985998
Short name T520
Test name
Test status
Simulation time 348173531574 ps
CPU time 3301.21 seconds
Started Aug 08 06:24:04 PM PDT 24
Finished Aug 08 07:19:06 PM PDT 24
Peak memory 3202720 kb
Host smart-bd618a21-8c25-45b3-8cb4-ff6e22c086ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3997985998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3997985998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.606417320
Short name T362
Test name
Test status
Simulation time 97041181705 ps
CPU time 3253.31 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 07:18:20 PM PDT 24
Peak memory 3110676 kb
Host smart-2a99503f-18e5-42d5-878d-015ab9c54fd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=606417320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.606417320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.1383944935
Short name T589
Test name
Test status
Simulation time 252554899023 ps
CPU time 2040.92 seconds
Started Aug 08 06:24:04 PM PDT 24
Finished Aug 08 06:58:05 PM PDT 24
Peak memory 2380548 kb
Host smart-d5fec15b-c7e8-4fee-b515-d1c4634c7dc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1383944935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.1383944935 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.1492816367
Short name T424
Test name
Test status
Simulation time 37320124603 ps
CPU time 916.27 seconds
Started Aug 08 06:23:54 PM PDT 24
Finished Aug 08 06:39:10 PM PDT 24
Peak memory 688716 kb
Host smart-a869363d-fe8e-4f5b-87cd-c63cd256155a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1492816367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.1492816367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.1350072042
Short name T1033
Test name
Test status
Simulation time 179193943731 ps
CPU time 4277.73 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 07:35:31 PM PDT 24
Peak memory 2200720 kb
Host smart-22c796ca-fd5e-4da0-afcb-c421434fd832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1350072042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1350072042 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.4230991386
Short name T695
Test name
Test status
Simulation time 186893781 ps
CPU time 0.88 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:23:22 PM PDT 24
Peak memory 205240 kb
Host smart-f03d5e15-c8f2-4dbf-8797-a5cfda6cd449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230991386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.4230991386 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.1624353446
Short name T170
Test name
Test status
Simulation time 12000261755 ps
CPU time 131.94 seconds
Started Aug 08 06:23:19 PM PDT 24
Finished Aug 08 06:25:31 PM PDT 24
Peak memory 276748 kb
Host smart-4f727fdc-075d-4494-aed1-d2b3194bc36f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624353446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1624353446 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2323166805
Short name T93
Test name
Test status
Simulation time 59889504652 ps
CPU time 262.65 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:27:37 PM PDT 24
Peak memory 442160 kb
Host smart-7d7885bf-010a-435e-a17b-00d43d5c74dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323166805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.2323166805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2404318371
Short name T873
Test name
Test status
Simulation time 25312307566 ps
CPU time 983.03 seconds
Started Aug 08 06:23:06 PM PDT 24
Finished Aug 08 06:39:29 PM PDT 24
Peak memory 259560 kb
Host smart-a6f155b5-b595-4f05-bfcf-901bf4ff487d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404318371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2404318371
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.3857220243
Short name T820
Test name
Test status
Simulation time 938084000 ps
CPU time 3.6 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 06:23:30 PM PDT 24
Peak memory 220620 kb
Host smart-705e790f-5bc2-4732-84a0-25abcaba2f01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3857220243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3857220243 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.3511166
Short name T249
Test name
Test status
Simulation time 43436493 ps
CPU time 2.99 seconds
Started Aug 08 06:23:15 PM PDT 24
Finished Aug 08 06:23:18 PM PDT 24
Peak memory 222956 kb
Host smart-3e21b0a5-2d3d-4fc7-bf45-44cdb0347307
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3511166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3511166 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.1396977761
Short name T30
Test name
Test status
Simulation time 29457536219 ps
CPU time 61.44 seconds
Started Aug 08 06:23:13 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 219284 kb
Host smart-f6abbd57-85a2-47c8-8965-2efc988cb236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396977761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1396977761 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.1980461472
Short name T268
Test name
Test status
Simulation time 25601199874 ps
CPU time 231.63 seconds
Started Aug 08 06:23:12 PM PDT 24
Finished Aug 08 06:27:04 PM PDT 24
Peak memory 309148 kb
Host smart-b579332f-fbee-430f-8f6a-76684353cf79
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980461472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.19
80461472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.3489969187
Short name T738
Test name
Test status
Simulation time 3596358382 ps
CPU time 99.49 seconds
Started Aug 08 06:23:30 PM PDT 24
Finished Aug 08 06:25:09 PM PDT 24
Peak memory 322200 kb
Host smart-5a97d659-36e8-4ea0-a22d-700db763eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489969187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3489969187 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.2983949161
Short name T705
Test name
Test status
Simulation time 616696863 ps
CPU time 1.67 seconds
Started Aug 08 06:23:11 PM PDT 24
Finished Aug 08 06:23:13 PM PDT 24
Peak memory 218956 kb
Host smart-9c799104-35b1-466a-b981-00d3d88815c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983949161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2983949161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.2827826572
Short name T998
Test name
Test status
Simulation time 52006360 ps
CPU time 1.37 seconds
Started Aug 08 06:23:39 PM PDT 24
Finished Aug 08 06:23:40 PM PDT 24
Peak memory 217220 kb
Host smart-2ab48c20-4edf-458e-8add-789a4bddfd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827826572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2827826572 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.3770814915
Short name T1038
Test name
Test status
Simulation time 261865000610 ps
CPU time 4831.09 seconds
Started Aug 08 06:23:10 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 3623568 kb
Host smart-f8a66cf5-2b73-4c14-969c-6e255d10a634
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770814915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.3770814915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.846407871
Short name T957
Test name
Test status
Simulation time 4702484561 ps
CPU time 232.87 seconds
Started Aug 08 06:23:07 PM PDT 24
Finished Aug 08 06:27:00 PM PDT 24
Peak memory 319616 kb
Host smart-04dc7f0b-d094-41cb-b10e-ee0f0af2ce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846407871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.846407871 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.2909184051
Short name T10
Test name
Test status
Simulation time 2804334230 ps
CPU time 26.87 seconds
Started Aug 08 06:23:28 PM PDT 24
Finished Aug 08 06:23:55 PM PDT 24
Peak memory 250792 kb
Host smart-812f254e-e0f4-4de6-af93-add969fde544
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909184051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2909184051 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.2873361756
Short name T585
Test name
Test status
Simulation time 48249748201 ps
CPU time 340.31 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:28:54 PM PDT 24
Peak memory 539300 kb
Host smart-0559ee3b-12df-410b-9cac-05589cd7eac4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873361756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.2873361756 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.1548154311
Short name T536
Test name
Test status
Simulation time 1624855958 ps
CPU time 34.54 seconds
Started Aug 08 06:23:13 PM PDT 24
Finished Aug 08 06:23:48 PM PDT 24
Peak memory 218176 kb
Host smart-704035c9-e77d-4471-9fc5-841260fed575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548154311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.1548154311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.3085304551
Short name T886
Test name
Test status
Simulation time 220932082327 ps
CPU time 1898.85 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:55:14 PM PDT 24
Peak memory 1828620 kb
Host smart-81067dbf-5564-4d67-8d7b-2c8f9f724d59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3085304551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3085304551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.2866861154
Short name T281
Test name
Test status
Simulation time 338738864 ps
CPU time 4.48 seconds
Started Aug 08 06:23:08 PM PDT 24
Finished Aug 08 06:23:13 PM PDT 24
Peak memory 217924 kb
Host smart-9b30f952-029d-4fd2-a5e6-8f16d35b1f85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866861154 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.2866861154 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.1314472706
Short name T942
Test name
Test status
Simulation time 587129285 ps
CPU time 4.29 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 06:23:33 PM PDT 24
Peak memory 218048 kb
Host smart-5df6c794-9a87-4454-bce5-69bfa561aec1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314472706 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1314472706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.1517808910
Short name T821
Test name
Test status
Simulation time 44099280999 ps
CPU time 1951.82 seconds
Started Aug 08 06:23:07 PM PDT 24
Finished Aug 08 06:55:39 PM PDT 24
Peak memory 1176416 kb
Host smart-8b63fbc1-aeee-4fe8-b4f1-b78a657f620a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1517808910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1517808910 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.3360800816
Short name T877
Test name
Test status
Simulation time 35355131455 ps
CPU time 1706.09 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:51:40 PM PDT 24
Peak memory 1133800 kb
Host smart-dd41a686-9141-4aed-be6d-c6dd79cbb0bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3360800816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3360800816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.3378580883
Short name T750
Test name
Test status
Simulation time 276907864753 ps
CPU time 2303.33 seconds
Started Aug 08 06:23:13 PM PDT 24
Finished Aug 08 07:01:37 PM PDT 24
Peak memory 2356740 kb
Host smart-dd3da7bd-6e87-4233-88eb-d967f4062091
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3378580883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3378580883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1637475953
Short name T724
Test name
Test status
Simulation time 38713740486 ps
CPU time 884.07 seconds
Started Aug 08 06:23:08 PM PDT 24
Finished Aug 08 06:37:52 PM PDT 24
Peak memory 685792 kb
Host smart-7baf47c4-fc28-42ba-850a-f36c3d8b2322
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1637475953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1637475953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.2409717664
Short name T437
Test name
Test status
Simulation time 107325591909 ps
CPU time 5538.76 seconds
Started Aug 08 06:23:12 PM PDT 24
Finished Aug 08 07:55:31 PM PDT 24
Peak memory 2662316 kb
Host smart-2a64eb0a-3ba3-4092-b2a7-416d7ffb401a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2409717664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2409717664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.1065135827
Short name T548
Test name
Test status
Simulation time 870017132601 ps
CPU time 4744.23 seconds
Started Aug 08 06:23:11 PM PDT 24
Finished Aug 08 07:42:16 PM PDT 24
Peak memory 2231736 kb
Host smart-98363df7-a71a-4b5c-907e-322a3346966a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1065135827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1065135827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3236467310
Short name T259
Test name
Test status
Simulation time 28897493 ps
CPU time 0.92 seconds
Started Aug 08 06:23:54 PM PDT 24
Finished Aug 08 06:23:55 PM PDT 24
Peak memory 205144 kb
Host smart-7e361134-ac76-4e2d-81b2-e3f57b34b754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236467310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3236467310 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.500339380
Short name T418
Test name
Test status
Simulation time 29558955327 ps
CPU time 289.5 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:28:59 PM PDT 24
Peak memory 484844 kb
Host smart-e5551bd3-4b07-4f7d-8fd7-dce06257ed52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500339380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.500339380 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.1668232482
Short name T647
Test name
Test status
Simulation time 41867311575 ps
CPU time 527.1 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:32:38 PM PDT 24
Peak memory 234480 kb
Host smart-5fc96255-a0de-4ffe-be6f-82c3fd5c08a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668232482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.166823248
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.3091243096
Short name T677
Test name
Test status
Simulation time 1608210121 ps
CPU time 35.91 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:24:49 PM PDT 24
Peak memory 233636 kb
Host smart-9bbdf500-b459-431d-872b-4cd7043c0c5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091243096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3
091243096 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.16603932
Short name T599
Test name
Test status
Simulation time 27051522992 ps
CPU time 204.6 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:27:33 PM PDT 24
Peak memory 403116 kb
Host smart-26608f87-1bf7-416b-bf8c-dbc9e65d3226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16603932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.16603932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.2092684916
Short name T974
Test name
Test status
Simulation time 3849183295 ps
CPU time 9.14 seconds
Started Aug 08 06:23:56 PM PDT 24
Finished Aug 08 06:24:05 PM PDT 24
Peak memory 217728 kb
Host smart-460521b1-d148-4b60-a32e-7e46721fa1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092684916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2092684916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.427415978
Short name T959
Test name
Test status
Simulation time 24496452 ps
CPU time 1.17 seconds
Started Aug 08 06:24:01 PM PDT 24
Finished Aug 08 06:24:03 PM PDT 24
Peak memory 218944 kb
Host smart-f58677a1-d6ee-44de-b7bc-e7495d3198b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427415978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.427415978 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.3780156134
Short name T395
Test name
Test status
Simulation time 1572109471 ps
CPU time 36.93 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:24:45 PM PDT 24
Peak memory 254784 kb
Host smart-626e3f27-60f2-492e-9e63-75867dfd036e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780156134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.3780156134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.3086867665
Short name T662
Test name
Test status
Simulation time 40421524423 ps
CPU time 347.58 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 06:29:50 PM PDT 24
Peak memory 533120 kb
Host smart-58e0f0db-e3d0-488b-9c6b-b7a179346549
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086867665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3086867665 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.470607644
Short name T296
Test name
Test status
Simulation time 3298134687 ps
CPU time 28.94 seconds
Started Aug 08 06:23:56 PM PDT 24
Finished Aug 08 06:24:26 PM PDT 24
Peak memory 217964 kb
Host smart-49e1959e-55fb-43c5-a832-991cd1abee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470607644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.470607644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2835253914
Short name T728
Test name
Test status
Simulation time 74173404214 ps
CPU time 1988.39 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:57:18 PM PDT 24
Peak memory 1540204 kb
Host smart-c8dad67a-fe73-4210-bdcf-7e7e1c43cfe2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2835253914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2835253914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.2722150769
Short name T495
Test name
Test status
Simulation time 225357367 ps
CPU time 5.15 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 06:24:10 PM PDT 24
Peak memory 218048 kb
Host smart-294f3646-b95a-47a2-b119-1d31edc0e3d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722150769 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.2722150769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.3415302866
Short name T214
Test name
Test status
Simulation time 538342056 ps
CPU time 5.32 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 218144 kb
Host smart-6cce1023-2316-41e3-b33a-3c06a69d9ec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415302866 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.3415302866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.2594810431
Short name T419
Test name
Test status
Simulation time 19215032952 ps
CPU time 1728.59 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:52:49 PM PDT 24
Peak memory 1195924 kb
Host smart-aaae4f85-9b33-4393-8931-30cf31b77619
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2594810431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.2594810431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.2660400335
Short name T894
Test name
Test status
Simulation time 51900575616 ps
CPU time 1694.38 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:52:15 PM PDT 24
Peak memory 1130620 kb
Host smart-e75c6b08-43ce-435d-9c37-c2b322cc1412
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2660400335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2660400335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.3825587824
Short name T702
Test name
Test status
Simulation time 325890781430 ps
CPU time 2285.2 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 07:02:10 PM PDT 24
Peak memory 2332068 kb
Host smart-c93784f5-6ac1-4b1a-8a9d-9115dc3fe1e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3825587824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.3825587824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.2280611099
Short name T526
Test name
Test status
Simulation time 149639357238 ps
CPU time 1352.56 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:46:36 PM PDT 24
Peak memory 1737172 kb
Host smart-d6efe554-936a-4e61-a04b-ecd1ed68d5d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2280611099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.2280611099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.2286188259
Short name T741
Test name
Test status
Simulation time 45151545703 ps
CPU time 4692.39 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 07:42:16 PM PDT 24
Peak memory 2226100 kb
Host smart-e0f6c889-0c9d-4647-9709-c93501426a3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2286188259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2286188259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.4213171062
Short name T321
Test name
Test status
Simulation time 31670843 ps
CPU time 0.82 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:24:08 PM PDT 24
Peak memory 205140 kb
Host smart-ad5fddbb-e395-4792-befd-d0e10b78688c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213171062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.4213171062 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.644039494
Short name T458
Test name
Test status
Simulation time 784897182 ps
CPU time 41.88 seconds
Started Aug 08 06:24:00 PM PDT 24
Finished Aug 08 06:24:42 PM PDT 24
Peak memory 233400 kb
Host smart-5e089afc-bbdd-4943-be72-936762fda812
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644039494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.644039494 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.635412549
Short name T435
Test name
Test status
Simulation time 2463446689 ps
CPU time 47.55 seconds
Started Aug 08 06:24:15 PM PDT 24
Finished Aug 08 06:25:03 PM PDT 24
Peak memory 223984 kb
Host smart-6b052474-2ea6-4ca8-be17-e2af52581bff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635412549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.635412549
+enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.4031914537
Short name T276
Test name
Test status
Simulation time 22450025392 ps
CPU time 256.93 seconds
Started Aug 08 06:24:07 PM PDT 24
Finished Aug 08 06:28:29 PM PDT 24
Peak memory 442728 kb
Host smart-160ffe6d-3905-4d84-949a-897a1b9035ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031914537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.4
031914537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.765469130
Short name T1019
Test name
Test status
Simulation time 19333346001 ps
CPU time 480.46 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:32:09 PM PDT 24
Peak memory 625568 kb
Host smart-38bb528e-5738-48b3-be0f-bca208adec17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765469130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.765469130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2836284889
Short name T21
Test name
Test status
Simulation time 4765658522 ps
CPU time 4.06 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:13 PM PDT 24
Peak memory 217788 kb
Host smart-53d6600e-46cc-47cb-9d83-ec7808fe56d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836284889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2836284889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.682027491
Short name T58
Test name
Test status
Simulation time 688521913 ps
CPU time 3.9 seconds
Started Aug 08 06:24:03 PM PDT 24
Finished Aug 08 06:24:07 PM PDT 24
Peak memory 220604 kb
Host smart-dc87c05a-fb72-4642-b9a0-5055a8fa4893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682027491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.682027491 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.4027863217
Short name T377
Test name
Test status
Simulation time 44710728746 ps
CPU time 2550.23 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 07:06:38 PM PDT 24
Peak memory 1562076 kb
Host smart-99cea717-79a4-4292-8e81-479741ba8471
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027863217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.4027863217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.4054950156
Short name T309
Test name
Test status
Simulation time 183578268325 ps
CPU time 340.85 seconds
Started Aug 08 06:24:07 PM PDT 24
Finished Aug 08 06:29:48 PM PDT 24
Peak memory 535916 kb
Host smart-d4826a18-f498-449a-a194-e199c0dc9fdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054950156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.4054950156 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.25462950
Short name T626
Test name
Test status
Simulation time 1453846280 ps
CPU time 24.2 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:24:31 PM PDT 24
Peak memory 222420 kb
Host smart-93b45f8a-b72b-4828-a522-8e40b0558249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25462950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.25462950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3382311469
Short name T648
Test name
Test status
Simulation time 1782489683 ps
CPU time 4.27 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 06:24:09 PM PDT 24
Peak memory 218240 kb
Host smart-d8932034-89ad-4e8f-96fd-8f652a61b67d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3382311469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3382311469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.2086038003
Short name T931
Test name
Test status
Simulation time 672134455 ps
CPU time 4.69 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 06:24:07 PM PDT 24
Peak memory 217964 kb
Host smart-ede17afb-e0b0-48ee-b353-c3b902c8834e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086038003 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.2086038003 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.1916436419
Short name T737
Test name
Test status
Simulation time 393770618 ps
CPU time 4.42 seconds
Started Aug 08 06:24:04 PM PDT 24
Finished Aug 08 06:24:08 PM PDT 24
Peak memory 217648 kb
Host smart-5d36c407-7e0e-4839-987f-b9b3198867b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916436419 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.1916436419 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.1757790684
Short name T248
Test name
Test status
Simulation time 19389806138 ps
CPU time 1890.01 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:55:39 PM PDT 24
Peak memory 1231984 kb
Host smart-cd4ef32c-78a7-4984-ad49-8267cc24b8b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1757790684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1757790684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.1693108348
Short name T1039
Test name
Test status
Simulation time 35931385172 ps
CPU time 1900.33 seconds
Started Aug 08 06:23:57 PM PDT 24
Finished Aug 08 06:55:38 PM PDT 24
Peak memory 1152384 kb
Host smart-89484feb-92cd-43eb-aa02-954b1680d2c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1693108348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.1693108348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.4226510893
Short name T206
Test name
Test status
Simulation time 286295146906 ps
CPU time 2240.84 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 07:01:23 PM PDT 24
Peak memory 2435108 kb
Host smart-162673e8-2ad8-48b9-af6c-e5406470c68a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4226510893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.4226510893 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.2265047158
Short name T95
Test name
Test status
Simulation time 67791516529 ps
CPU time 1310.37 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:46:00 PM PDT 24
Peak memory 1717736 kb
Host smart-f8c98400-d38b-4057-bbcd-8e906417aa5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2265047158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2265047158 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.3890390388
Short name T227
Test name
Test status
Simulation time 181117779956 ps
CPU time 4912.8 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 07:46:02 PM PDT 24
Peak memory 2233192 kb
Host smart-3f4fa866-2343-4733-af99-43efb3d0b10f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3890390388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3890390388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.3470150903
Short name T155
Test name
Test status
Simulation time 23563815 ps
CPU time 0.85 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 06:24:06 PM PDT 24
Peak memory 205136 kb
Host smart-69f4e603-50a6-4233-824f-c9703a7e186b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470150903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3470150903 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3845912429
Short name T430
Test name
Test status
Simulation time 14750433700 ps
CPU time 353.88 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:30:00 PM PDT 24
Peak memory 515812 kb
Host smart-9454e1f4-79cb-45da-9154-6f24f825a5c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845912429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3845912429 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.4104219928
Short name T466
Test name
Test status
Simulation time 14451347893 ps
CPU time 125.76 seconds
Started Aug 08 06:24:14 PM PDT 24
Finished Aug 08 06:26:20 PM PDT 24
Peak memory 233228 kb
Host smart-f2da4265-630d-4f36-9161-f14c68c8fc3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104219928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.410421992
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_error.2678063887
Short name T51
Test name
Test status
Simulation time 5169827329 ps
CPU time 159.07 seconds
Started Aug 08 06:24:07 PM PDT 24
Finished Aug 08 06:26:46 PM PDT 24
Peak memory 361204 kb
Host smart-1f44a56e-eb71-4c96-aad9-32d6bc86d228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678063887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2678063887 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.1132811098
Short name T310
Test name
Test status
Simulation time 1159715830 ps
CPU time 5.8 seconds
Started Aug 08 06:24:15 PM PDT 24
Finished Aug 08 06:24:21 PM PDT 24
Peak memory 217888 kb
Host smart-c486894d-af65-4f68-a72b-d19ae50d8c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132811098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1132811098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.3599810322
Short name T61
Test name
Test status
Simulation time 126659554 ps
CPU time 1.59 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:11 PM PDT 24
Peak memory 223820 kb
Host smart-86cb08cc-8687-4c07-b9a9-ebe17916d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599810322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3599810322 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.3769780342
Short name T251
Test name
Test status
Simulation time 6743019855 ps
CPU time 604.46 seconds
Started Aug 08 06:24:11 PM PDT 24
Finished Aug 08 06:34:15 PM PDT 24
Peak memory 621316 kb
Host smart-06e4caea-f8e1-48d8-8310-ca26ab134901
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769780342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.3769780342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2131922077
Short name T898
Test name
Test status
Simulation time 13555472894 ps
CPU time 262.08 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 06:28:24 PM PDT 24
Peak memory 337504 kb
Host smart-c1bd1067-aaa3-4fc9-a3a1-b8035059574c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131922077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2131922077 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.4283007826
Short name T606
Test name
Test status
Simulation time 1242753041 ps
CPU time 13.99 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:24:24 PM PDT 24
Peak memory 217868 kb
Host smart-953cb9fd-56d3-472d-949b-56065bdbff23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283007826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.4283007826 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.2052738453
Short name T139
Test name
Test status
Simulation time 9850627551 ps
CPU time 222.83 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:27:49 PM PDT 24
Peak memory 337548 kb
Host smart-20c2b63a-4b39-4dee-9480-740dcaabfbdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2052738453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2052738453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.723200773
Short name T666
Test name
Test status
Simulation time 133434222 ps
CPU time 4.22 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:24:12 PM PDT 24
Peak memory 217824 kb
Host smart-57010cf8-2423-4796-b20e-161e5e6f9310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723200773 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.kmac_test_vectors_kmac.723200773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1346742947
Short name T854
Test name
Test status
Simulation time 222681725 ps
CPU time 4.84 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 218028 kb
Host smart-7491f5fc-d9a4-4e78-a316-782e235d7755
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346742947 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.1346742947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.2378646166
Short name T85
Test name
Test status
Simulation time 329283286737 ps
CPU time 3160.63 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 07:16:50 PM PDT 24
Peak memory 3275148 kb
Host smart-cda511b6-e718-468c-aeda-e16372b12386
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2378646166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.2378646166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.3580403214
Short name T1037
Test name
Test status
Simulation time 319902880168 ps
CPU time 2987.03 seconds
Started Aug 08 06:24:15 PM PDT 24
Finished Aug 08 07:14:02 PM PDT 24
Peak memory 3074780 kb
Host smart-96aee22e-4531-4e12-86ed-d5d011ce9045
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3580403214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.3580403214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.4016904529
Short name T608
Test name
Test status
Simulation time 55483086927 ps
CPU time 1398.29 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:47:25 PM PDT 24
Peak memory 934448 kb
Host smart-1f54da5e-f9dd-4641-b1e5-693da24b8c68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4016904529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.4016904529 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.954351885
Short name T798
Test name
Test status
Simulation time 65204167122 ps
CPU time 1335.89 seconds
Started Aug 08 06:24:07 PM PDT 24
Finished Aug 08 06:46:23 PM PDT 24
Peak memory 1686128 kb
Host smart-c5785ca4-bb19-4a98-bffe-8221eacc3056
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=954351885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.954351885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1258471527
Short name T208
Test name
Test status
Simulation time 201620681469 ps
CPU time 5485.08 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 07:55:32 PM PDT 24
Peak memory 2662740 kb
Host smart-83a14998-8585-4a02-a9e9-252fbadf4ede
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1258471527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1258471527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.3861212135
Short name T408
Test name
Test status
Simulation time 45099394224 ps
CPU time 4301.43 seconds
Started Aug 08 06:24:11 PM PDT 24
Finished Aug 08 07:35:53 PM PDT 24
Peak memory 2219036 kb
Host smart-3fd04b62-7f5b-4183-a999-e86182418d6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3861212135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3861212135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.3608889376
Short name T992
Test name
Test status
Simulation time 14010392 ps
CPU time 0.74 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:24:10 PM PDT 24
Peak memory 205212 kb
Host smart-29bfec26-0def-432f-bae1-2777599b5c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608889376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3608889376 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.4272110111
Short name T154
Test name
Test status
Simulation time 4840855486 ps
CPU time 60.58 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:25:10 PM PDT 24
Peak memory 249512 kb
Host smart-3a5b2c92-45b9-4ec8-a214-d3ed47128688
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272110111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.4272110111 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.2295050005
Short name T1030
Test name
Test status
Simulation time 37437733726 ps
CPU time 552.63 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:33:25 PM PDT 24
Peak memory 244076 kb
Host smart-4ca9a2ed-8251-4e47-8ab3-320cea4007f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295050005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.229505000
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.1978256083
Short name T546
Test name
Test status
Simulation time 12671319417 ps
CPU time 254.59 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:28:28 PM PDT 24
Peak memory 327152 kb
Host smart-40f39e27-98cb-487c-9774-eda7e1c55808
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978256083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1
978256083 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.1941447197
Short name T537
Test name
Test status
Simulation time 22230430159 ps
CPU time 132.11 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:26:22 PM PDT 24
Peak memory 338644 kb
Host smart-3e7b07a8-59b3-45e6-af8a-75d67b6601a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941447197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1941447197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.1284076061
Short name T679
Test name
Test status
Simulation time 1306356418 ps
CPU time 3.93 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:24:10 PM PDT 24
Peak memory 217176 kb
Host smart-ce999903-9d1d-4c3a-beb6-9b601ad807cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284076061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1284076061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.2596714314
Short name T41
Test name
Test status
Simulation time 149127065 ps
CPU time 1.4 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:24:12 PM PDT 24
Peak memory 217328 kb
Host smart-d9355c22-45a3-462b-afa0-dd0d133aa795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596714314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2596714314 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.915307949
Short name T533
Test name
Test status
Simulation time 128938500939 ps
CPU time 1143.21 seconds
Started Aug 08 06:24:07 PM PDT 24
Finished Aug 08 06:43:10 PM PDT 24
Peak memory 885080 kb
Host smart-04ea9fc8-65f1-4f6c-bbd5-3c6a999c81a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915307949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_an
d_output.915307949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.3671824495
Short name T231
Test name
Test status
Simulation time 23556819293 ps
CPU time 169.46 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:26:58 PM PDT 24
Peak memory 387376 kb
Host smart-ee13d6b5-270e-4aa8-b592-22053fd91916
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671824495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3671824495 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1280887976
Short name T464
Test name
Test status
Simulation time 3342633411 ps
CPU time 60.52 seconds
Started Aug 08 06:24:02 PM PDT 24
Finished Aug 08 06:25:02 PM PDT 24
Peak memory 221660 kb
Host smart-e88c5b06-e34c-46bb-9e04-e99df012de9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280887976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1280887976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.1333933048
Short name T600
Test name
Test status
Simulation time 38909711120 ps
CPU time 745.57 seconds
Started Aug 08 06:24:11 PM PDT 24
Finished Aug 08 06:36:37 PM PDT 24
Peak memory 598184 kb
Host smart-4bb4ef35-81c0-4076-87e8-1ce18a126019
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1333933048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1333933048 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.4157295051
Short name T868
Test name
Test status
Simulation time 71795806 ps
CPU time 3.8 seconds
Started Aug 08 06:24:14 PM PDT 24
Finished Aug 08 06:24:18 PM PDT 24
Peak memory 217744 kb
Host smart-e6bb5d06-be81-448c-bd65-0ad748d83160
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157295051 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.4157295051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3116554376
Short name T211
Test name
Test status
Simulation time 950008223 ps
CPU time 5.23 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:24:15 PM PDT 24
Peak memory 217932 kb
Host smart-b15895b6-a59a-410d-a66c-c6d3795ce39b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116554376 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3116554376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.58358802
Short name T977
Test name
Test status
Simulation time 210629047239 ps
CPU time 1913.07 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:56:01 PM PDT 24
Peak memory 1203636 kb
Host smart-696c252e-1684-4d32-af8e-0cc8d35c1fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=58358802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.58358802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.932816570
Short name T212
Test name
Test status
Simulation time 62930601395 ps
CPU time 2554.64 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 07:06:45 PM PDT 24
Peak memory 3016700 kb
Host smart-6ec1042f-c872-442a-b21c-a8ab1ee83de5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=932816570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.932816570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.940782346
Short name T382
Test name
Test status
Simulation time 48630811576 ps
CPU time 1886.55 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:55:37 PM PDT 24
Peak memory 2375464 kb
Host smart-a29bab8e-b9b5-40f9-8798-42a8f0193485
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=940782346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.940782346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.3053312487
Short name T861
Test name
Test status
Simulation time 12406950674 ps
CPU time 897.16 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:39:10 PM PDT 24
Peak memory 709304 kb
Host smart-0a1babbf-08ff-44ca-a179-80fc58c6d854
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3053312487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.3053312487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.1126561160
Short name T334
Test name
Test status
Simulation time 173992754533 ps
CPU time 10732.6 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 09:23:04 PM PDT 24
Peak memory 7747584 kb
Host smart-536f9b9f-8321-49b1-ba1f-7d32182338f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1126561160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.1126561160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_alert_test.2920445141
Short name T654
Test name
Test status
Simulation time 47305903 ps
CPU time 0.81 seconds
Started Aug 08 06:24:11 PM PDT 24
Finished Aug 08 06:24:12 PM PDT 24
Peak memory 205184 kb
Host smart-d8d89ab0-d4aa-4520-a6ad-d212648f5324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920445141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2920445141 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.2775151098
Short name T120
Test name
Test status
Simulation time 20823484962 ps
CPU time 210.66 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:27:44 PM PDT 24
Peak memory 407816 kb
Host smart-859b1abc-8197-4970-b7e8-2ce7ec804624
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775151098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2775151098 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.535942188
Short name T586
Test name
Test status
Simulation time 15886423030 ps
CPU time 509.7 seconds
Started Aug 08 06:24:11 PM PDT 24
Finished Aug 08 06:32:41 PM PDT 24
Peak memory 243300 kb
Host smart-fd018acc-8a6a-4e31-8eb6-d8b3186db614
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535942188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.535942188
+enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3605313808
Short name T723
Test name
Test status
Simulation time 76866532965 ps
CPU time 350.7 seconds
Started Aug 08 06:24:16 PM PDT 24
Finished Aug 08 06:30:06 PM PDT 24
Peak memory 478832 kb
Host smart-df471bfb-fb12-4e8d-8c21-9f6ef8cd6c6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605313808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3
605313808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.919421283
Short name T797
Test name
Test status
Simulation time 7165948589 ps
CPU time 129.34 seconds
Started Aug 08 06:24:14 PM PDT 24
Finished Aug 08 06:26:23 PM PDT 24
Peak memory 285228 kb
Host smart-261ab283-5c3a-45c8-b9dd-966d190d515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919421283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.919421283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.2425999612
Short name T773
Test name
Test status
Simulation time 952838100 ps
CPU time 3.36 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:24:17 PM PDT 24
Peak memory 218012 kb
Host smart-8118aba5-a713-436e-8d0a-3095121673b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425999612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2425999612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.423827913
Short name T988
Test name
Test status
Simulation time 54064780 ps
CPU time 1.38 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:24:15 PM PDT 24
Peak memory 218084 kb
Host smart-36aaa6f3-8ac8-4c13-afb3-aee5ecaae998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423827913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.423827913 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.132502534
Short name T198
Test name
Test status
Simulation time 9268280013 ps
CPU time 235.84 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:28:06 PM PDT 24
Peak memory 529100 kb
Host smart-8f8f26aa-1d5b-4087-bd19-288ee3c7e1c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132502534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an
d_output.132502534 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.3443577090
Short name T240
Test name
Test status
Simulation time 148842112 ps
CPU time 4.1 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:24:10 PM PDT 24
Peak memory 220560 kb
Host smart-2e875dc8-a8c4-4afc-ae97-81c686b97328
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443577090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3443577090 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.3532200644
Short name T742
Test name
Test status
Simulation time 987911048 ps
CPU time 51.18 seconds
Started Aug 08 06:24:05 PM PDT 24
Finished Aug 08 06:24:56 PM PDT 24
Peak memory 217908 kb
Host smart-c66dfd5e-d6ab-4a11-ae0c-eea392f10d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532200644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3532200644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.3653552251
Short name T735
Test name
Test status
Simulation time 37418315177 ps
CPU time 747.58 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:36:41 PM PDT 24
Peak memory 481548 kb
Host smart-9c895b5f-5963-4135-92bd-5383622eee60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3653552251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3653552251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.1796388495
Short name T308
Test name
Test status
Simulation time 476062459 ps
CPU time 5.16 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 06:24:20 PM PDT 24
Peak memory 218120 kb
Host smart-32f43502-3e47-46ed-b812-c958b509e429
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796388495 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.1796388495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.3366924509
Short name T256
Test name
Test status
Simulation time 872140338 ps
CPU time 5.36 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:15 PM PDT 24
Peak memory 218100 kb
Host smart-feadfa5f-ff75-4045-82c1-e8cf852da607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366924509 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.3366924509 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.894394922
Short name T370
Test name
Test status
Simulation time 395859767600 ps
CPU time 3590.67 seconds
Started Aug 08 06:24:10 PM PDT 24
Finished Aug 08 07:24:01 PM PDT 24
Peak memory 3288036 kb
Host smart-0a1bd3d3-9596-4013-8104-b7e415ad11f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=894394922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.894394922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.1778298190
Short name T1035
Test name
Test status
Simulation time 18030760188 ps
CPU time 1664.9 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:51:53 PM PDT 24
Peak memory 1109712 kb
Host smart-86433012-89f5-4c7e-8cdd-515d37f00212
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1778298190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.1778298190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.1321238432
Short name T390
Test name
Test status
Simulation time 47518106331 ps
CPU time 1934.58 seconds
Started Aug 08 06:24:06 PM PDT 24
Finished Aug 08 06:56:21 PM PDT 24
Peak memory 2392724 kb
Host smart-632ca6c7-9442-4bc3-be47-5b1e8f917b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1321238432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.1321238432 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.2097084196
Short name T859
Test name
Test status
Simulation time 58989669753 ps
CPU time 867.98 seconds
Started Aug 08 06:24:15 PM PDT 24
Finished Aug 08 06:38:43 PM PDT 24
Peak memory 696344 kb
Host smart-d0854abe-3d0f-4b35-8b46-324e82d6b187
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2097084196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2097084196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1819057768
Short name T860
Test name
Test status
Simulation time 294915312021 ps
CPU time 8300.52 seconds
Started Aug 08 06:24:14 PM PDT 24
Finished Aug 08 08:42:35 PM PDT 24
Peak memory 6353500 kb
Host smart-8ea2aef0-d69a-42be-add3-ccdaf10d4add
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1819057768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1819057768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.3370344711
Short name T962
Test name
Test status
Simulation time 39378747 ps
CPU time 0.92 seconds
Started Aug 08 06:24:20 PM PDT 24
Finished Aug 08 06:24:21 PM PDT 24
Peak memory 204720 kb
Host smart-6d2cf84f-4868-4dbd-80cb-07ed3283e5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370344711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3370344711 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.1308584956
Short name T230
Test name
Test status
Simulation time 3673636471 ps
CPU time 167.37 seconds
Started Aug 08 06:24:21 PM PDT 24
Finished Aug 08 06:27:09 PM PDT 24
Peak memory 301488 kb
Host smart-e2d8dd0d-cc7b-4762-a748-d7cd2c7ae19e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308584956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1308584956 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.635025871
Short name T47
Test name
Test status
Simulation time 16167393915 ps
CPU time 739.26 seconds
Started Aug 08 06:24:15 PM PDT 24
Finished Aug 08 06:36:34 PM PDT 24
Peak memory 240880 kb
Host smart-05da3573-82af-4c76-9def-c0d722227a5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635025871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.635025871
+enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.3151760101
Short name T1016
Test name
Test status
Simulation time 19208533790 ps
CPU time 170.64 seconds
Started Aug 08 06:24:08 PM PDT 24
Finished Aug 08 06:26:59 PM PDT 24
Peak memory 292120 kb
Host smart-3bff1695-3857-42c2-b3e3-89f0a55a6b6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151760101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3
151760101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.3066796404
Short name T910
Test name
Test status
Simulation time 76449005751 ps
CPU time 407.54 seconds
Started Aug 08 06:24:28 PM PDT 24
Finished Aug 08 06:31:16 PM PDT 24
Peak memory 608872 kb
Host smart-c9356f9b-331f-4125-b343-0aa776d68ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066796404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3066796404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.2634119885
Short name T331
Test name
Test status
Simulation time 2354701458 ps
CPU time 4.61 seconds
Started Aug 08 06:24:32 PM PDT 24
Finished Aug 08 06:24:37 PM PDT 24
Peak memory 218140 kb
Host smart-462fd1b2-13e6-4ef6-be3e-2d6eb9834779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634119885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2634119885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.2313960405
Short name T348
Test name
Test status
Simulation time 1952006326 ps
CPU time 17.59 seconds
Started Aug 08 06:24:20 PM PDT 24
Finished Aug 08 06:24:38 PM PDT 24
Peak memory 240240 kb
Host smart-afbc146d-af41-4b53-8420-a6c279f0d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313960405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2313960405 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.991852686
Short name T1044
Test name
Test status
Simulation time 12562260411 ps
CPU time 435.29 seconds
Started Aug 08 06:24:12 PM PDT 24
Finished Aug 08 06:31:27 PM PDT 24
Peak memory 781756 kb
Host smart-1b25b7d3-b7cb-4c26-afb4-14216f025e93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991852686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an
d_output.991852686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.2434428660
Short name T550
Test name
Test status
Simulation time 78638430768 ps
CPU time 490.9 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:32:20 PM PDT 24
Peak memory 654148 kb
Host smart-7858d568-5100-472a-b0f2-bd69391eedad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434428660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2434428660 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.968118793
Short name T205
Test name
Test status
Simulation time 215902638 ps
CPU time 3.36 seconds
Started Aug 08 06:24:14 PM PDT 24
Finished Aug 08 06:24:18 PM PDT 24
Peak memory 219608 kb
Host smart-f4221985-5e7d-4c42-880e-2f03d1f3c0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968118793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.968118793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3606176580
Short name T872
Test name
Test status
Simulation time 154682422134 ps
CPU time 1409.66 seconds
Started Aug 08 06:24:29 PM PDT 24
Finished Aug 08 06:47:59 PM PDT 24
Peak memory 991612 kb
Host smart-c5481a9f-71bd-466c-b1a2-3198459fb6af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3606176580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3606176580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.3740904166
Short name T14
Test name
Test status
Simulation time 173619002 ps
CPU time 4.72 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 218044 kb
Host smart-84951504-21dc-4b67-9157-4780a0b4fcd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740904166 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.3740904166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.766709625
Short name T394
Test name
Test status
Simulation time 64920007 ps
CPU time 4.19 seconds
Started Aug 08 06:24:18 PM PDT 24
Finished Aug 08 06:24:22 PM PDT 24
Peak memory 217736 kb
Host smart-48ac0c2b-19fa-4df8-b5ed-822eeb7a3f19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766709625 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.766709625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.486191772
Short name T235
Test name
Test status
Simulation time 393504360457 ps
CPU time 3713.93 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 07:26:07 PM PDT 24
Peak memory 3274300 kb
Host smart-a5442df3-91f6-49da-8dfe-334c1514f78f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=486191772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.486191772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.3662627561
Short name T637
Test name
Test status
Simulation time 70974372056 ps
CPU time 1620.81 seconds
Started Aug 08 06:24:13 PM PDT 24
Finished Aug 08 06:51:14 PM PDT 24
Peak memory 1089788 kb
Host smart-26e1dca6-bd58-48c3-b14e-249d7e34a26d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3662627561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.3662627561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.2899248927
Short name T574
Test name
Test status
Simulation time 93956446052 ps
CPU time 2062.5 seconds
Started Aug 08 06:24:09 PM PDT 24
Finished Aug 08 06:58:32 PM PDT 24
Peak memory 2390096 kb
Host smart-aa2aadf5-5f8b-44ca-92a8-4533477d652e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2899248927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.2899248927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.553001169
Short name T207
Test name
Test status
Simulation time 20471574133 ps
CPU time 844.62 seconds
Started Aug 08 06:24:15 PM PDT 24
Finished Aug 08 06:38:19 PM PDT 24
Peak memory 695048 kb
Host smart-10be3d74-940b-4380-9a61-58c4e947abb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=553001169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.553001169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.1231933142
Short name T1032
Test name
Test status
Simulation time 905634191653 ps
CPU time 10626.4 seconds
Started Aug 08 06:24:14 PM PDT 24
Finished Aug 08 09:21:21 PM PDT 24
Peak memory 6421448 kb
Host smart-d6bcf09c-7d1e-4265-a1d4-e073c3a5c379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1231933142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.1231933142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1213138350
Short name T416
Test name
Test status
Simulation time 19486237 ps
CPU time 0.73 seconds
Started Aug 08 06:24:18 PM PDT 24
Finished Aug 08 06:24:18 PM PDT 24
Peak memory 205188 kb
Host smart-f429aeda-5e89-47df-8a5a-377ef3aadfdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213138350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1213138350 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.383811940
Short name T479
Test name
Test status
Simulation time 9098491717 ps
CPU time 203.06 seconds
Started Aug 08 06:24:20 PM PDT 24
Finished Aug 08 06:27:43 PM PDT 24
Peak memory 399852 kb
Host smart-1a855e13-5487-48dd-8169-44593d61402f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383811940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.383811940 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.4116667419
Short name T746
Test name
Test status
Simulation time 8991374203 ps
CPU time 369.54 seconds
Started Aug 08 06:24:30 PM PDT 24
Finished Aug 08 06:30:40 PM PDT 24
Peak memory 236272 kb
Host smart-73fa4eee-0941-45b5-9586-c20a4b483c75
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116667419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.411666741
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.2967953577
Short name T749
Test name
Test status
Simulation time 19217879639 ps
CPU time 208.76 seconds
Started Aug 08 06:24:28 PM PDT 24
Finished Aug 08 06:27:57 PM PDT 24
Peak memory 304904 kb
Host smart-cc8affc6-6b7d-4e9e-a2af-002ac2e85945
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967953577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2
967953577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.2910712862
Short name T171
Test name
Test status
Simulation time 12282787223 ps
CPU time 65.25 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:25:38 PM PDT 24
Peak memory 278700 kb
Host smart-2ffcc22d-be7a-44ee-82b4-81aba938b1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910712862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2910712862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.1808721404
Short name T510
Test name
Test status
Simulation time 1924217133 ps
CPU time 5.26 seconds
Started Aug 08 06:24:29 PM PDT 24
Finished Aug 08 06:24:35 PM PDT 24
Peak memory 217608 kb
Host smart-afa86d82-2244-4614-b4b2-9b0633eca9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808721404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1808721404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.3994551752
Short name T941
Test name
Test status
Simulation time 83563269 ps
CPU time 1.14 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:24:34 PM PDT 24
Peak memory 218988 kb
Host smart-55ea50c8-9837-4291-9028-ef2ec54b9010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994551752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3994551752 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_sideload.2572085423
Short name T202
Test name
Test status
Simulation time 14485724567 ps
CPU time 364.43 seconds
Started Aug 08 06:24:31 PM PDT 24
Finished Aug 08 06:30:36 PM PDT 24
Peak memory 547372 kb
Host smart-c0ad7582-7a1b-4be9-bffd-17a11f89a7a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572085423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2572085423 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.397728088
Short name T926
Test name
Test status
Simulation time 1139974687 ps
CPU time 4.77 seconds
Started Aug 08 06:24:18 PM PDT 24
Finished Aug 08 06:24:23 PM PDT 24
Peak memory 218168 kb
Host smart-dc6c9b1a-f236-48fd-bbcc-8ae7ba8009d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397728088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.397728088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.1779035477
Short name T869
Test name
Test status
Simulation time 8305285805 ps
CPU time 234.31 seconds
Started Aug 08 06:24:19 PM PDT 24
Finished Aug 08 06:28:13 PM PDT 24
Peak memory 289836 kb
Host smart-e5f1ebff-1633-4a9b-a63d-546280c6b190
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1779035477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1779035477 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.296636843
Short name T807
Test name
Test status
Simulation time 3525590090 ps
CPU time 6.77 seconds
Started Aug 08 06:24:18 PM PDT 24
Finished Aug 08 06:24:25 PM PDT 24
Peak memory 218188 kb
Host smart-a3cfe3b6-2d34-4980-a107-58aa8d0297fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296636843 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.kmac_test_vectors_kmac.296636843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.2897806665
Short name T427
Test name
Test status
Simulation time 973887544 ps
CPU time 5.34 seconds
Started Aug 08 06:24:30 PM PDT 24
Finished Aug 08 06:24:35 PM PDT 24
Peak memory 218236 kb
Host smart-ab55b608-815f-4a3a-9b32-09d75c7bd50d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897806665 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.2897806665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.95180780
Short name T986
Test name
Test status
Simulation time 19361156951 ps
CPU time 1764.94 seconds
Started Aug 08 06:24:28 PM PDT 24
Finished Aug 08 06:53:53 PM PDT 24
Peak memory 1179468 kb
Host smart-9d190502-d4e6-4bc3-9aef-ff6f6440bc30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=95180780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.95180780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.3294387090
Short name T287
Test name
Test status
Simulation time 17741593635 ps
CPU time 1814.84 seconds
Started Aug 08 06:24:19 PM PDT 24
Finished Aug 08 06:54:34 PM PDT 24
Peak memory 1135476 kb
Host smart-228c2bdf-f07c-4b32-8ad1-aa54e23d67d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3294387090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.3294387090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.1967783817
Short name T736
Test name
Test status
Simulation time 29025968985 ps
CPU time 1347.77 seconds
Started Aug 08 06:24:18 PM PDT 24
Finished Aug 08 06:46:46 PM PDT 24
Peak memory 919448 kb
Host smart-b2635ba3-4ce9-447f-9334-3fb83ae1d25a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1967783817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.1967783817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.1102148284
Short name T839
Test name
Test status
Simulation time 131485845255 ps
CPU time 1291.4 seconds
Started Aug 08 06:24:16 PM PDT 24
Finished Aug 08 06:45:48 PM PDT 24
Peak memory 1735544 kb
Host smart-0c440f15-561a-4ff4-a301-71bc3f4f1302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1102148284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1102148284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.1633408900
Short name T892
Test name
Test status
Simulation time 103842072563 ps
CPU time 5581.31 seconds
Started Aug 08 06:24:20 PM PDT 24
Finished Aug 08 07:57:22 PM PDT 24
Peak memory 2693048 kb
Host smart-c1765ae0-c98a-489d-9884-8a1334608651
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1633408900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.1633408900 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.465106688
Short name T445
Test name
Test status
Simulation time 172876779512 ps
CPU time 4524.86 seconds
Started Aug 08 06:24:18 PM PDT 24
Finished Aug 08 07:39:43 PM PDT 24
Peak memory 2217256 kb
Host smart-0d776724-9440-4a4d-8af8-265f0dc07aa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=465106688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.465106688 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.3771355887
Short name T726
Test name
Test status
Simulation time 12606753 ps
CPU time 0.76 seconds
Started Aug 08 06:24:29 PM PDT 24
Finished Aug 08 06:24:29 PM PDT 24
Peak memory 205168 kb
Host smart-2360e055-d95b-4b38-adce-96d92fa6ea04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771355887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3771355887 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.2800673489
Short name T513
Test name
Test status
Simulation time 3792608051 ps
CPU time 38.47 seconds
Started Aug 08 06:24:29 PM PDT 24
Finished Aug 08 06:25:08 PM PDT 24
Peak memory 231876 kb
Host smart-c5836dd6-90fd-477b-86f8-1bf0aca8eb54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800673489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2800673489 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.589162882
Short name T303
Test name
Test status
Simulation time 94996862347 ps
CPU time 854.95 seconds
Started Aug 08 06:24:36 PM PDT 24
Finished Aug 08 06:38:51 PM PDT 24
Peak memory 258740 kb
Host smart-061000b4-0ac6-4eab-9574-ee9526858ac3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589162882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.589162882
+enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.263093613
Short name T1046
Test name
Test status
Simulation time 4912642394 ps
CPU time 69.77 seconds
Started Aug 08 06:24:36 PM PDT 24
Finished Aug 08 06:25:46 PM PDT 24
Peak memory 245820 kb
Host smart-a390af51-b0ef-47f2-877b-ee6447d28198
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263093613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.26
3093613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.667049808
Short name T632
Test name
Test status
Simulation time 30464388452 ps
CPU time 139.83 seconds
Started Aug 08 06:24:28 PM PDT 24
Finished Aug 08 06:26:48 PM PDT 24
Peak memory 289496 kb
Host smart-d1539e82-4e4d-4e3c-8f90-32ca23672f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667049808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.667049808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.2806900222
Short name T688
Test name
Test status
Simulation time 3167370013 ps
CPU time 7.85 seconds
Started Aug 08 06:24:27 PM PDT 24
Finished Aug 08 06:24:35 PM PDT 24
Peak memory 218060 kb
Host smart-6a392f43-1e2f-42b5-afa5-4a59a746f74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806900222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2806900222 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.4082399154
Short name T919
Test name
Test status
Simulation time 949166446 ps
CPU time 25.54 seconds
Started Aug 08 06:24:28 PM PDT 24
Finished Aug 08 06:24:54 PM PDT 24
Peak memory 247988 kb
Host smart-b74457c4-ca48-4b60-a724-5eae2cf42b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082399154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.4082399154 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.1794241347
Short name T232
Test name
Test status
Simulation time 1444128204 ps
CPU time 16.42 seconds
Started Aug 08 06:24:28 PM PDT 24
Finished Aug 08 06:24:45 PM PDT 24
Peak memory 236264 kb
Host smart-56ed913b-15bc-49d7-bfb1-2489e1d9ab25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794241347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.1794241347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1320217869
Short name T678
Test name
Test status
Simulation time 2423625206 ps
CPU time 203.89 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:27:57 PM PDT 24
Peak memory 309504 kb
Host smart-cb4c35d8-13de-4efb-b645-280704b8a255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320217869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1320217869 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3417047458
Short name T999
Test name
Test status
Simulation time 2184504535 ps
CPU time 37.47 seconds
Started Aug 08 06:24:18 PM PDT 24
Finished Aug 08 06:24:55 PM PDT 24
Peak memory 218364 kb
Host smart-a9f444d6-989c-4386-9d99-76833ad1a0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417047458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3417047458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.2130699892
Short name T897
Test name
Test status
Simulation time 65307117896 ps
CPU time 1190.86 seconds
Started Aug 08 06:24:36 PM PDT 24
Finished Aug 08 06:44:27 PM PDT 24
Peak memory 1237444 kb
Host smart-bfe7cd7d-3cda-45c4-8dfe-ff11806c2266
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2130699892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2130699892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.1088130902
Short name T459
Test name
Test status
Simulation time 69905663 ps
CPU time 4.19 seconds
Started Aug 08 06:24:19 PM PDT 24
Finished Aug 08 06:24:23 PM PDT 24
Peak memory 217840 kb
Host smart-da18441a-cc66-4278-ab46-9e221b02e80c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088130902 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.1088130902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2803529346
Short name T583
Test name
Test status
Simulation time 171848143 ps
CPU time 4.59 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:24:38 PM PDT 24
Peak memory 217796 kb
Host smart-35087472-4f13-4d9b-aae3-b464f36d6452
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803529346 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2803529346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.1713601726
Short name T635
Test name
Test status
Simulation time 167070032254 ps
CPU time 1838.9 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:55:12 PM PDT 24
Peak memory 1166700 kb
Host smart-475f8f40-5eaa-48b9-b1ce-30c5759a2362
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1713601726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.1713601726 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.2309066913
Short name T238
Test name
Test status
Simulation time 188886107297 ps
CPU time 3119.82 seconds
Started Aug 08 06:24:38 PM PDT 24
Finished Aug 08 07:16:38 PM PDT 24
Peak memory 3025848 kb
Host smart-842cd8bf-43c9-4f5f-b7ca-54636ad238a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2309066913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.2309066913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.486910442
Short name T70
Test name
Test status
Simulation time 56894626882 ps
CPU time 1299.85 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:46:13 PM PDT 24
Peak memory 922252 kb
Host smart-2a4b0bc9-16ee-413c-8e2f-7cca30ef3747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=486910442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.486910442 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.1867038647
Short name T454
Test name
Test status
Simulation time 43263600751 ps
CPU time 1289.57 seconds
Started Aug 08 06:24:27 PM PDT 24
Finished Aug 08 06:45:57 PM PDT 24
Peak memory 1670968 kb
Host smart-05ca0c6c-0aa1-4b28-a189-7092efabf58a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1867038647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.1867038647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.1458726246
Short name T398
Test name
Test status
Simulation time 506518196337 ps
CPU time 5368.34 seconds
Started Aug 08 06:24:17 PM PDT 24
Finished Aug 08 07:53:46 PM PDT 24
Peak memory 2679028 kb
Host smart-51b7bec2-536b-4123-bfa3-ed24f6ff7562
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1458726246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1458726246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.2985173121
Short name T391
Test name
Test status
Simulation time 438852453007 ps
CPU time 9994.56 seconds
Started Aug 08 06:24:34 PM PDT 24
Finished Aug 08 09:11:10 PM PDT 24
Peak memory 6340216 kb
Host smart-49bb47d5-6d15-487a-b215-3f40924fa3f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2985173121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.2985173121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.2608253856
Short name T392
Test name
Test status
Simulation time 19770478 ps
CPU time 0.8 seconds
Started Aug 08 06:24:38 PM PDT 24
Finished Aug 08 06:24:39 PM PDT 24
Peak memory 205232 kb
Host smart-442bb33f-8d13-4446-b718-87e1781894ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608253856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2608253856 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.644399809
Short name T800
Test name
Test status
Simulation time 4148538618 ps
CPU time 51.66 seconds
Started Aug 08 06:24:36 PM PDT 24
Finished Aug 08 06:25:28 PM PDT 24
Peak memory 237484 kb
Host smart-83b8fe87-2042-4202-94ad-b1715e5c274e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644399809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.644399809 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.3348227266
Short name T318
Test name
Test status
Simulation time 158610714218 ps
CPU time 560.73 seconds
Started Aug 08 06:24:32 PM PDT 24
Finished Aug 08 06:33:53 PM PDT 24
Peak memory 242708 kb
Host smart-e08ac680-d582-485a-a15a-f5886f4f6120
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348227266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.334822726
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.1611757045
Short name T813
Test name
Test status
Simulation time 20317279848 ps
CPU time 261.7 seconds
Started Aug 08 06:24:34 PM PDT 24
Finished Aug 08 06:28:56 PM PDT 24
Peak memory 437568 kb
Host smart-03794928-b22d-4484-b0d6-09d8c85e5c3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611757045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1
611757045 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.3504631838
Short name T888
Test name
Test status
Simulation time 2079754601 ps
CPU time 62.25 seconds
Started Aug 08 06:24:32 PM PDT 24
Finished Aug 08 06:25:35 PM PDT 24
Peak memory 280172 kb
Host smart-49bf8058-cf07-41a9-bedb-998fc4d7c4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504631838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3504631838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.4257756
Short name T262
Test name
Test status
Simulation time 1303469843 ps
CPU time 6.16 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:24:39 PM PDT 24
Peak memory 217740 kb
Host smart-a2ed8448-c27a-4440-babb-adbd05a691cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.4257756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2816416431
Short name T453
Test name
Test status
Simulation time 449065118 ps
CPU time 22.53 seconds
Started Aug 08 06:24:39 PM PDT 24
Finished Aug 08 06:25:01 PM PDT 24
Peak memory 235312 kb
Host smart-d74c4f5e-101c-4429-a00b-e0083e68b956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816416431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2816416431 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.4119092855
Short name T428
Test name
Test status
Simulation time 107806905170 ps
CPU time 2871.04 seconds
Started Aug 08 06:24:29 PM PDT 24
Finished Aug 08 07:12:21 PM PDT 24
Peak memory 2774048 kb
Host smart-be72877d-6ab8-4dfa-89bb-37baae382c0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119092855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.4119092855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.3935174145
Short name T421
Test name
Test status
Simulation time 3636369171 ps
CPU time 135.61 seconds
Started Aug 08 06:24:28 PM PDT 24
Finished Aug 08 06:26:44 PM PDT 24
Peak memory 277692 kb
Host smart-4a9e8e0c-1e59-41ef-bd88-b2204834a364
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935174145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3935174145 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.3280646192
Short name T700
Test name
Test status
Simulation time 419455602 ps
CPU time 22 seconds
Started Aug 08 06:24:29 PM PDT 24
Finished Aug 08 06:24:51 PM PDT 24
Peak memory 218072 kb
Host smart-1472a7bd-cbb7-4c13-9252-d6aef0939959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280646192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3280646192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.1332126809
Short name T541
Test name
Test status
Simulation time 25334811798 ps
CPU time 163.79 seconds
Started Aug 08 06:24:34 PM PDT 24
Finished Aug 08 06:27:18 PM PDT 24
Peak memory 355900 kb
Host smart-4e0a4560-df0b-4809-a14f-c2f2d936de83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1332126809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1332126809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.37268359
Short name T410
Test name
Test status
Simulation time 60732915 ps
CPU time 3.89 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:24:37 PM PDT 24
Peak memory 218252 kb
Host smart-1e01dfa4-9663-4dab-867a-ca36ec2c15d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37268359 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.kmac_test_vectors_kmac.37268359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.735175995
Short name T193
Test name
Test status
Simulation time 988521899 ps
CPU time 5.46 seconds
Started Aug 08 06:24:29 PM PDT 24
Finished Aug 08 06:24:34 PM PDT 24
Peak memory 217956 kb
Host smart-7fd61876-ede4-40d4-899b-691badcd5b0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735175995 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.kmac_test_vectors_kmac_xof.735175995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.1209391427
Short name T337
Test name
Test status
Simulation time 64581328108 ps
CPU time 2822.1 seconds
Started Aug 08 06:24:28 PM PDT 24
Finished Aug 08 07:11:31 PM PDT 24
Peak memory 3210576 kb
Host smart-98060168-7eec-4301-91b1-c343eaa4d3bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1209391427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.1209391427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.555614264
Short name T224
Test name
Test status
Simulation time 63302626640 ps
CPU time 2913.1 seconds
Started Aug 08 06:24:36 PM PDT 24
Finished Aug 08 07:13:10 PM PDT 24
Peak memory 3035816 kb
Host smart-38ad2da3-3a43-401a-93d1-fb726ddc32cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=555614264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.555614264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.2136501543
Short name T540
Test name
Test status
Simulation time 336020724109 ps
CPU time 2178.26 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 07:00:51 PM PDT 24
Peak memory 2393488 kb
Host smart-45308ac8-c384-4d91-9fcd-c2539feadcc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2136501543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2136501543 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.4175172163
Short name T671
Test name
Test status
Simulation time 43783278655 ps
CPU time 1387.49 seconds
Started Aug 08 06:24:34 PM PDT 24
Finished Aug 08 06:47:42 PM PDT 24
Peak memory 1710684 kb
Host smart-cb018c4e-6728-4775-8de5-844ddeb227fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4175172163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.4175172163 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.902750104
Short name T361
Test name
Test status
Simulation time 176291302888 ps
CPU time 5021.63 seconds
Started Aug 08 06:24:26 PM PDT 24
Finished Aug 08 07:48:09 PM PDT 24
Peak memory 2271952 kb
Host smart-dc27c339-3c9a-46a4-9369-735835093650
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=902750104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.902750104 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.3714357059
Short name T1009
Test name
Test status
Simulation time 31141061 ps
CPU time 0.76 seconds
Started Aug 08 06:24:35 PM PDT 24
Finished Aug 08 06:24:36 PM PDT 24
Peak memory 205224 kb
Host smart-05da7c4c-386c-447f-8cb5-ecda9611235e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714357059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3714357059 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.2212219686
Short name T799
Test name
Test status
Simulation time 22351839607 ps
CPU time 326.17 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:29:59 PM PDT 24
Peak memory 488024 kb
Host smart-730ac941-391b-4d39-ae68-bb77479d04af
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212219686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2212219686 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.392705169
Short name T192
Test name
Test status
Simulation time 61007037980 ps
CPU time 633.34 seconds
Started Aug 08 06:24:39 PM PDT 24
Finished Aug 08 06:35:12 PM PDT 24
Peak memory 238868 kb
Host smart-3ba6243f-bd4b-429e-a85a-102bdd5c0f91
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392705169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.392705169
+enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.3669663221
Short name T591
Test name
Test status
Simulation time 43485218587 ps
CPU time 205 seconds
Started Aug 08 06:24:34 PM PDT 24
Finished Aug 08 06:27:59 PM PDT 24
Peak memory 421476 kb
Host smart-8a7e9ee3-e9f6-414e-879f-ac8f6e4d26ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669663221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3
669663221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_key_error.293947787
Short name T67
Test name
Test status
Simulation time 335000666 ps
CPU time 1.76 seconds
Started Aug 08 06:24:40 PM PDT 24
Finished Aug 08 06:24:42 PM PDT 24
Peak memory 218708 kb
Host smart-3d2a5da0-1309-48c1-9429-1062540495c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293947787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.293947787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.2278552690
Short name T157
Test name
Test status
Simulation time 66797735 ps
CPU time 1.18 seconds
Started Aug 08 06:24:36 PM PDT 24
Finished Aug 08 06:24:37 PM PDT 24
Peak memory 218780 kb
Host smart-2b1f871d-3bd2-4033-a9b6-c6174ad4650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278552690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2278552690 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1428657944
Short name T471
Test name
Test status
Simulation time 115720390276 ps
CPU time 1016.37 seconds
Started Aug 08 06:24:45 PM PDT 24
Finished Aug 08 06:41:42 PM PDT 24
Peak memory 1342952 kb
Host smart-0acba3c9-20c7-420c-a5df-5af907297f31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428657944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1428657944 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.1320819056
Short name T816
Test name
Test status
Simulation time 9389888256 ps
CPU time 288.29 seconds
Started Aug 08 06:24:34 PM PDT 24
Finished Aug 08 06:29:22 PM PDT 24
Peak memory 469768 kb
Host smart-0c7940ce-aa09-4412-ab7f-cd72cde35d61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320819056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1320819056 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.543854076
Short name T851
Test name
Test status
Simulation time 19755124377 ps
CPU time 65.98 seconds
Started Aug 08 06:24:38 PM PDT 24
Finished Aug 08 06:25:44 PM PDT 24
Peak memory 224140 kb
Host smart-2a572281-05f0-4b34-a485-8422971fb699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543854076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.543854076 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.656082274
Short name T521
Test name
Test status
Simulation time 26891534710 ps
CPU time 707.62 seconds
Started Aug 08 06:24:36 PM PDT 24
Finished Aug 08 06:36:23 PM PDT 24
Peak memory 987852 kb
Host smart-8942a8fa-c923-4c77-8ec5-666224800ece
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=656082274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.656082274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.3636283287
Short name T876
Test name
Test status
Simulation time 270091805 ps
CPU time 5.4 seconds
Started Aug 08 06:24:37 PM PDT 24
Finished Aug 08 06:24:42 PM PDT 24
Peak memory 217856 kb
Host smart-b0ceef7f-b9bf-46c5-809c-19b675d71e43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636283287 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.3636283287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2963011752
Short name T1000
Test name
Test status
Simulation time 2676328336 ps
CPU time 4.6 seconds
Started Aug 08 06:24:43 PM PDT 24
Finished Aug 08 06:24:48 PM PDT 24
Peak memory 218148 kb
Host smart-8fedbe5b-8d8c-44e5-9d04-860d640aa49a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963011752 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2963011752 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.3475586221
Short name T631
Test name
Test status
Simulation time 262713715679 ps
CPU time 3020.27 seconds
Started Aug 08 06:24:42 PM PDT 24
Finished Aug 08 07:15:03 PM PDT 24
Peak memory 3134636 kb
Host smart-966beb75-33fa-4b8f-96a0-45e7f194ba70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3475586221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.3475586221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.3422592496
Short name T980
Test name
Test status
Simulation time 92254791421 ps
CPU time 3426.64 seconds
Started Aug 08 06:24:40 PM PDT 24
Finished Aug 08 07:21:47 PM PDT 24
Peak memory 3078652 kb
Host smart-898107b5-12a1-4b39-9d5e-e4a1e1f2c7ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3422592496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3422592496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.2046452595
Short name T255
Test name
Test status
Simulation time 70017722355 ps
CPU time 2320 seconds
Started Aug 08 06:24:37 PM PDT 24
Finished Aug 08 07:03:17 PM PDT 24
Peak memory 2381660 kb
Host smart-8ae12d9f-0506-4c03-9b64-0349f1606617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2046452595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.2046452595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.669911418
Short name T707
Test name
Test status
Simulation time 299530365218 ps
CPU time 1375.51 seconds
Started Aug 08 06:24:35 PM PDT 24
Finished Aug 08 06:47:31 PM PDT 24
Peak memory 1738068 kb
Host smart-523aee7a-e556-4f9c-86f0-aa2e59782a3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=669911418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.669911418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.2339245235
Short name T867
Test name
Test status
Simulation time 170559116249 ps
CPU time 10087.3 seconds
Started Aug 08 06:24:36 PM PDT 24
Finished Aug 08 09:12:45 PM PDT 24
Peak memory 7752548 kb
Host smart-90f38538-20ef-4918-8302-7705d3d74743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2339245235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2339245235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.2691442268
Short name T954
Test name
Test status
Simulation time 607277719466 ps
CPU time 8793.67 seconds
Started Aug 08 06:24:40 PM PDT 24
Finished Aug 08 08:51:15 PM PDT 24
Peak memory 6408316 kb
Host smart-c87a55b1-685b-483f-8fc8-8ab11724c5eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2691442268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2691442268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.3804564329
Short name T52
Test name
Test status
Simulation time 68263622 ps
CPU time 0.9 seconds
Started Aug 08 06:23:17 PM PDT 24
Finished Aug 08 06:23:18 PM PDT 24
Peak memory 205264 kb
Host smart-91c23aa0-c032-4790-9ad2-52a12665cd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804564329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3804564329 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.899730445
Short name T115
Test name
Test status
Simulation time 3963478231 ps
CPU time 102.77 seconds
Started Aug 08 06:23:12 PM PDT 24
Finished Aug 08 06:24:55 PM PDT 24
Peak memory 307372 kb
Host smart-88558fef-48dd-48ff-b469-50f6a878449a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899730445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.899730445 +enable_masking=0
+sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.2799093157
Short name T446
Test name
Test status
Simulation time 26650975150 ps
CPU time 289.18 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 06:28:11 PM PDT 24
Peak memory 457116 kb
Host smart-193b00cd-7385-42fa-ba7a-2eda76020843
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799093157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_par
tial_data.2799093157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.2890208828
Short name T874
Test name
Test status
Simulation time 5617808094 ps
CPU time 131.78 seconds
Started Aug 08 06:23:15 PM PDT 24
Finished Aug 08 06:25:27 PM PDT 24
Peak memory 224216 kb
Host smart-c81c9ed3-5df6-4a98-9cb1-18dd787aa898
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890208828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2890208828
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3481733224
Short name T380
Test name
Test status
Simulation time 1599797560 ps
CPU time 34.09 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:23:55 PM PDT 24
Peak memory 236468 kb
Host smart-e152d0d3-6fa4-493a-a93a-492f17bef019
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3481733224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3481733224 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.2107228503
Short name T920
Test name
Test status
Simulation time 97612424 ps
CPU time 6.88 seconds
Started Aug 08 06:23:11 PM PDT 24
Finished Aug 08 06:23:18 PM PDT 24
Peak memory 223752 kb
Host smart-c50980b1-9ea8-4b65-929a-79dd0dc97585
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2107228503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2107228503 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.3438869304
Short name T642
Test name
Test status
Simulation time 8311357457 ps
CPU time 20.74 seconds
Started Aug 08 06:23:27 PM PDT 24
Finished Aug 08 06:23:48 PM PDT 24
Peak memory 218520 kb
Host smart-3b5e7064-4edb-4408-9462-db3de19bb013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438869304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3438869304 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.2634005347
Short name T758
Test name
Test status
Simulation time 75290434460 ps
CPU time 256.93 seconds
Started Aug 08 06:23:19 PM PDT 24
Finished Aug 08 06:27:36 PM PDT 24
Peak memory 322596 kb
Host smart-29a3a430-5396-49f5-8a62-7fe623ff9398
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634005347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.26
34005347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.238670352
Short name T443
Test name
Test status
Simulation time 42253319610 ps
CPU time 260.13 seconds
Started Aug 08 06:23:26 PM PDT 24
Finished Aug 08 06:27:46 PM PDT 24
Peak memory 446340 kb
Host smart-c3190522-0fa2-4e34-a503-12315257f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238670352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.238670352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.3751498599
Short name T357
Test name
Test status
Simulation time 1448039634 ps
CPU time 7.02 seconds
Started Aug 08 06:23:27 PM PDT 24
Finished Aug 08 06:23:34 PM PDT 24
Peak memory 217528 kb
Host smart-c089d615-c3e9-4711-81e7-885392b1a8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751498599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3751498599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.3529797193
Short name T899
Test name
Test status
Simulation time 415650059164 ps
CPU time 2770.58 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 07:09:47 PM PDT 24
Peak memory 2542564 kb
Host smart-d95a7009-4efb-4670-bd14-e466a4cb8b30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529797193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.3529797193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.2792071652
Short name T674
Test name
Test status
Simulation time 75904149338 ps
CPU time 311.02 seconds
Started Aug 08 06:23:13 PM PDT 24
Finished Aug 08 06:28:24 PM PDT 24
Peak memory 480596 kb
Host smart-8c46b299-8151-40e8-9264-db188c086221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792071652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2792071652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sideload.3701534530
Short name T605
Test name
Test status
Simulation time 3115515290 ps
CPU time 59.69 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:24:14 PM PDT 24
Peak memory 245556 kb
Host smart-499f6d94-e4cc-48c0-8877-4bcf601b8399
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701534530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3701534530 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.580651951
Short name T722
Test name
Test status
Simulation time 14605157058 ps
CPU time 59.31 seconds
Started Aug 08 06:23:18 PM PDT 24
Finished Aug 08 06:24:17 PM PDT 24
Peak memory 219900 kb
Host smart-a45a6a9e-088c-4171-9d72-9d78286c9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580651951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.580651951 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.2409825383
Short name T55
Test name
Test status
Simulation time 7162846936 ps
CPU time 410.59 seconds
Started Aug 08 06:23:17 PM PDT 24
Finished Aug 08 06:30:08 PM PDT 24
Peak memory 363184 kb
Host smart-9b79e852-04f5-4bf7-8de8-8ec99da88e75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2409825383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2409825383 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.1734412637
Short name T770
Test name
Test status
Simulation time 1210402852 ps
CPU time 4.25 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:23:38 PM PDT 24
Peak memory 218020 kb
Host smart-008ed1e6-f39b-425a-9f06-8132608b0644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734412637 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.1734412637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.1744872249
Short name T345
Test name
Test status
Simulation time 251818217 ps
CPU time 5.21 seconds
Started Aug 08 06:23:05 PM PDT 24
Finished Aug 08 06:23:10 PM PDT 24
Peak memory 217948 kb
Host smart-20a3e29e-8e95-4264-acd9-b76c8fd12b1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744872249 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1744872249 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2199370657
Short name T386
Test name
Test status
Simulation time 311564950481 ps
CPU time 3265.71 seconds
Started Aug 08 06:23:16 PM PDT 24
Finished Aug 08 07:17:43 PM PDT 24
Peak memory 3222588 kb
Host smart-bc200bb2-07aa-4a27-8b18-c8f95acf7ca1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2199370657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2199370657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.2379755951
Short name T381
Test name
Test status
Simulation time 82791143323 ps
CPU time 3203.52 seconds
Started Aug 08 06:23:25 PM PDT 24
Finished Aug 08 07:16:49 PM PDT 24
Peak memory 3092472 kb
Host smart-7c408ade-e7ef-42be-b0a4-36e5cc4081d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2379755951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.2379755951 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.1278740872
Short name T789
Test name
Test status
Simulation time 146248502046 ps
CPU time 2295.55 seconds
Started Aug 08 06:23:19 PM PDT 24
Finished Aug 08 07:01:34 PM PDT 24
Peak memory 2390068 kb
Host smart-b556f759-29b3-4b9c-a7b4-48ede8debb35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1278740872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1278740872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.81885153
Short name T346
Test name
Test status
Simulation time 193508169993 ps
CPU time 1487.59 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:48:09 PM PDT 24
Peak memory 1709700 kb
Host smart-36dd2d32-79d0-4d32-ab78-6d550d2b298f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=81885153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.81885153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.2862415322
Short name T439
Test name
Test status
Simulation time 203614781943 ps
CPU time 5335.45 seconds
Started Aug 08 06:23:20 PM PDT 24
Finished Aug 08 07:52:16 PM PDT 24
Peak memory 2695056 kb
Host smart-0381b0c9-7dfe-4fe5-bca9-df072f5fcf07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2862415322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.2862415322 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.21479305
Short name T500
Test name
Test status
Simulation time 754162304262 ps
CPU time 8849.66 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 08:50:45 PM PDT 24
Peak memory 6416492 kb
Host smart-8d1ed9f7-849e-4be2-8cc5-765d8ae64ce5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=21479305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.21479305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3397574757
Short name T280
Test name
Test status
Simulation time 20841209 ps
CPU time 0.82 seconds
Started Aug 08 06:24:43 PM PDT 24
Finished Aug 08 06:24:44 PM PDT 24
Peak memory 205164 kb
Host smart-1bfed7de-47a3-40b4-b016-9ba5c232b852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397574757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3397574757 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.3312418255
Short name T286
Test name
Test status
Simulation time 2598355411 ps
CPU time 14.76 seconds
Started Aug 08 06:24:42 PM PDT 24
Finished Aug 08 06:24:57 PM PDT 24
Peak memory 240408 kb
Host smart-a3628cb8-dd67-44be-ac83-cd2131487ee5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312418255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3312418255 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.437774788
Short name T253
Test name
Test status
Simulation time 2183460843 ps
CPU time 16.66 seconds
Started Aug 08 06:24:34 PM PDT 24
Finished Aug 08 06:24:51 PM PDT 24
Peak memory 218296 kb
Host smart-7bbdd4a8-efdb-4f03-8adc-385b6af0865e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437774788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.437774788
+enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.1597530101
Short name T342
Test name
Test status
Simulation time 2393752667 ps
CPU time 45.57 seconds
Started Aug 08 06:24:43 PM PDT 24
Finished Aug 08 06:25:28 PM PDT 24
Peak memory 261288 kb
Host smart-49e94b4b-37f6-4e0c-bc4a-7274f2ff25bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597530101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1
597530101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.4068348838
Short name T502
Test name
Test status
Simulation time 1551992281 ps
CPU time 102.31 seconds
Started Aug 08 06:24:43 PM PDT 24
Finished Aug 08 06:26:25 PM PDT 24
Peak memory 273144 kb
Host smart-a75127a3-b8c7-4df9-805e-13fab18c2e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068348838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.4068348838 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.1425123266
Short name T298
Test name
Test status
Simulation time 361314284 ps
CPU time 1.23 seconds
Started Aug 08 06:24:47 PM PDT 24
Finished Aug 08 06:24:49 PM PDT 24
Peak memory 217716 kb
Host smart-893f1308-d181-41e6-bad2-45f4e3c8d434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425123266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1425123266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.4181835214
Short name T715
Test name
Test status
Simulation time 1998299676 ps
CPU time 33.85 seconds
Started Aug 08 06:24:42 PM PDT 24
Finished Aug 08 06:25:16 PM PDT 24
Peak memory 241608 kb
Host smart-630f3745-664a-4314-b9f1-902279589e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181835214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.4181835214 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.4254540192
Short name T497
Test name
Test status
Simulation time 35100317459 ps
CPU time 883.43 seconds
Started Aug 08 06:24:38 PM PDT 24
Finished Aug 08 06:39:21 PM PDT 24
Peak memory 752356 kb
Host smart-d64e39bb-2c7f-4cbf-92f0-2cf729b4c0f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254540192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.4254540192 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.1751768374
Short name T204
Test name
Test status
Simulation time 21534013260 ps
CPU time 297.03 seconds
Started Aug 08 06:24:40 PM PDT 24
Finished Aug 08 06:29:37 PM PDT 24
Peak memory 504768 kb
Host smart-25ac8eaf-d8dc-4039-92f9-a01141261dd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751768374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1751768374 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.1955610099
Short name T457
Test name
Test status
Simulation time 1301842960 ps
CPU time 26.63 seconds
Started Aug 08 06:24:38 PM PDT 24
Finished Aug 08 06:25:04 PM PDT 24
Peak memory 218264 kb
Host smart-5ac40cb9-7903-4ef8-87b3-8cf1e2cb1223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955610099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1955610099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.1886192735
Short name T491
Test name
Test status
Simulation time 106320532592 ps
CPU time 1009.48 seconds
Started Aug 08 06:24:43 PM PDT 24
Finished Aug 08 06:41:32 PM PDT 24
Peak memory 1290512 kb
Host smart-74ef3b36-9825-4306-afff-9590f1310758
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1886192735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1886192735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.2102669427
Short name T752
Test name
Test status
Simulation time 65647543 ps
CPU time 4.3 seconds
Started Aug 08 06:24:41 PM PDT 24
Finished Aug 08 06:24:46 PM PDT 24
Peak memory 217696 kb
Host smart-2f840557-e064-4c80-94d7-b3b4bfbf1b91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102669427 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.2102669427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2382712284
Short name T929
Test name
Test status
Simulation time 211737772 ps
CPU time 4.42 seconds
Started Aug 08 06:24:41 PM PDT 24
Finished Aug 08 06:24:46 PM PDT 24
Peak memory 217780 kb
Host smart-6a1e8a0c-04c2-498b-99f3-38ed22347e67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382712284 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2382712284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.885842397
Short name T369
Test name
Test status
Simulation time 19349793194 ps
CPU time 1866.37 seconds
Started Aug 08 06:24:33 PM PDT 24
Finished Aug 08 06:55:40 PM PDT 24
Peak memory 1180456 kb
Host smart-f0a454c4-39f5-4a18-96cf-a622afdb9aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=885842397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.885842397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.572554049
Short name T542
Test name
Test status
Simulation time 36418809848 ps
CPU time 1742.57 seconds
Started Aug 08 06:24:38 PM PDT 24
Finished Aug 08 06:53:41 PM PDT 24
Peak memory 1142808 kb
Host smart-bf14120b-c161-4030-913c-0b3ef2d301cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=572554049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.572554049 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.924273990
Short name T995
Test name
Test status
Simulation time 130927071811 ps
CPU time 2033.94 seconds
Started Aug 08 06:24:42 PM PDT 24
Finished Aug 08 06:58:36 PM PDT 24
Peak memory 2400556 kb
Host smart-8a3a4f2b-8190-490a-85cc-7ef40a77d070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=924273990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.924273990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.3570318250
Short name T709
Test name
Test status
Simulation time 188242474020 ps
CPU time 1484.53 seconds
Started Aug 08 06:24:42 PM PDT 24
Finished Aug 08 06:49:27 PM PDT 24
Peak memory 1759060 kb
Host smart-d315beda-e8c3-4b15-96a9-65d43b5a69cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3570318250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.3570318250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.326350687
Short name T630
Test name
Test status
Simulation time 51114570756 ps
CPU time 5416.72 seconds
Started Aug 08 06:24:41 PM PDT 24
Finished Aug 08 07:54:59 PM PDT 24
Peak memory 2675644 kb
Host smart-a7d6c9ce-6331-42c3-b979-0186e02aa8b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=326350687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.326350687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.2295966694
Short name T311
Test name
Test status
Simulation time 70271525023 ps
CPU time 4549.41 seconds
Started Aug 08 06:24:42 PM PDT 24
Finished Aug 08 07:40:32 PM PDT 24
Peak memory 2196392 kb
Host smart-f7cf779c-a3d3-466b-bfa5-1796e0e6cafa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2295966694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.2295966694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.1043681765
Short name T243
Test name
Test status
Simulation time 20077829 ps
CPU time 0.82 seconds
Started Aug 08 06:24:57 PM PDT 24
Finished Aug 08 06:24:58 PM PDT 24
Peak memory 205204 kb
Host smart-fb79a630-b8ff-4e40-83b0-e18afb9b0d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043681765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1043681765 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.4137163088
Short name T289
Test name
Test status
Simulation time 19343951497 ps
CPU time 273.79 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:29:25 PM PDT 24
Peak memory 332760 kb
Host smart-3bdd52ad-44e1-4621-90f5-0a308a932031
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137163088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.4137163088 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.4113121524
Short name T344
Test name
Test status
Simulation time 22308215519 ps
CPU time 392.62 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:31:23 PM PDT 24
Peak memory 236288 kb
Host smart-724e87e6-101b-442a-b58d-dbc540f8915b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113121524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.411312152
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2803139242
Short name T923
Test name
Test status
Simulation time 297317218 ps
CPU time 9.38 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:24:59 PM PDT 24
Peak memory 223960 kb
Host smart-463ac3ad-012d-4634-8cc0-e4fc5d042562
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803139242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2
803139242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.3067566263
Short name T307
Test name
Test status
Simulation time 61021453287 ps
CPU time 355.02 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:30:46 PM PDT 24
Peak memory 539988 kb
Host smart-9a036184-5428-44cf-82cd-5a85de868738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067566263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3067566263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.702374840
Short name T628
Test name
Test status
Simulation time 2521358068 ps
CPU time 3.33 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:24:53 PM PDT 24
Peak memory 217872 kb
Host smart-81729fa5-c61f-468d-8ebb-96374661846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702374840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.702374840 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.2627136262
Short name T912
Test name
Test status
Simulation time 95488712 ps
CPU time 1.1 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:24:52 PM PDT 24
Peak memory 218620 kb
Host smart-8c1469b2-37cc-4c68-8dde-67fb69f2865d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627136262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2627136262 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.1316183233
Short name T918
Test name
Test status
Simulation time 10984086226 ps
CPU time 94.29 seconds
Started Aug 08 06:24:42 PM PDT 24
Finished Aug 08 06:26:16 PM PDT 24
Peak memory 333960 kb
Host smart-db652fe9-bc66-455a-98c2-bdbf31223538
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316183233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.1316183233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.2740551563
Short name T468
Test name
Test status
Simulation time 6731298955 ps
CPU time 182.51 seconds
Started Aug 08 06:24:43 PM PDT 24
Finished Aug 08 06:27:46 PM PDT 24
Peak memory 393728 kb
Host smart-707a98ed-339b-4eff-9e13-d4032f29f067
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740551563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2740551563 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.2552321678
Short name T664
Test name
Test status
Simulation time 3478405341 ps
CPU time 17.57 seconds
Started Aug 08 06:24:47 PM PDT 24
Finished Aug 08 06:25:04 PM PDT 24
Peak memory 218200 kb
Host smart-3c4e1557-5b2a-47dd-8d2f-037225d1af71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552321678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2552321678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.2228017593
Short name T825
Test name
Test status
Simulation time 51353171694 ps
CPU time 1581.55 seconds
Started Aug 08 06:24:53 PM PDT 24
Finished Aug 08 06:51:15 PM PDT 24
Peak memory 813804 kb
Host smart-a70a2db0-cbf4-41d4-8a77-d92c1c1da745
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2228017593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2228017593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.2599475309
Short name T857
Test name
Test status
Simulation time 244138378 ps
CPU time 4.04 seconds
Started Aug 08 06:24:51 PM PDT 24
Finished Aug 08 06:24:55 PM PDT 24
Peak memory 217832 kb
Host smart-e4199fa6-328d-4b9a-99dc-b23d0a4c9082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599475309 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.2599475309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.1692394865
Short name T870
Test name
Test status
Simulation time 171067914 ps
CPU time 4.23 seconds
Started Aug 08 06:24:49 PM PDT 24
Finished Aug 08 06:24:53 PM PDT 24
Peak memory 217736 kb
Host smart-102a3f9c-0e6f-4c03-9cd2-4bd4d135b32f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692394865 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.1692394865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.3216804977
Short name T444
Test name
Test status
Simulation time 748717845783 ps
CPU time 3573.03 seconds
Started Aug 08 06:24:53 PM PDT 24
Finished Aug 08 07:24:27 PM PDT 24
Peak memory 3237088 kb
Host smart-53b45002-ebcf-400b-9896-da763487b637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3216804977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3216804977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.2116881763
Short name T484
Test name
Test status
Simulation time 499357162334 ps
CPU time 2860.4 seconds
Started Aug 08 06:24:53 PM PDT 24
Finished Aug 08 07:12:34 PM PDT 24
Peak memory 2990060 kb
Host smart-f8c5447c-65f5-442a-983e-8a9348cc9db1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2116881763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.2116881763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.887536595
Short name T534
Test name
Test status
Simulation time 13560306936 ps
CPU time 1268.43 seconds
Started Aug 08 06:24:57 PM PDT 24
Finished Aug 08 06:46:05 PM PDT 24
Peak memory 914332 kb
Host smart-6ea7f61e-faab-4a71-b170-7ee71fe6e8c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=887536595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.887536595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1711887402
Short name T788
Test name
Test status
Simulation time 32552762509 ps
CPU time 1254.73 seconds
Started Aug 08 06:24:53 PM PDT 24
Finished Aug 08 06:45:48 PM PDT 24
Peak memory 1701996 kb
Host smart-7d7702ff-a25c-4815-9635-0740b57566df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1711887402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1711887402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.3981179640
Short name T787
Test name
Test status
Simulation time 223025649493 ps
CPU time 9476.55 seconds
Started Aug 08 06:24:54 PM PDT 24
Finished Aug 08 09:02:51 PM PDT 24
Peak memory 6380020 kb
Host smart-63bfcc77-3dd4-4849-b6db-0b804253ed31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3981179640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3981179640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.1689459811
Short name T462
Test name
Test status
Simulation time 57592744 ps
CPU time 0.76 seconds
Started Aug 08 06:24:55 PM PDT 24
Finished Aug 08 06:24:56 PM PDT 24
Peak memory 205140 kb
Host smart-ae0f8422-53db-40a0-86f0-c6ef1bb45617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689459811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1689459811 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.3393983289
Short name T490
Test name
Test status
Simulation time 13525766373 ps
CPU time 60.32 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:25:50 PM PDT 24
Peak memory 268020 kb
Host smart-64aba900-f942-45ef-95d7-88e8b1be4248
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393983289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3393983289 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.1651504832
Short name T993
Test name
Test status
Simulation time 11071784163 ps
CPU time 361.43 seconds
Started Aug 08 06:24:51 PM PDT 24
Finished Aug 08 06:30:52 PM PDT 24
Peak memory 235236 kb
Host smart-2ab0bc8d-d2ce-4e85-aeb9-e1efb09f5ba3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651504832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.165150483
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.2116297560
Short name T976
Test name
Test status
Simulation time 76774221866 ps
CPU time 366.62 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:30:57 PM PDT 24
Peak memory 491048 kb
Host smart-604e8ae7-7bf8-4eaf-85fd-b94463783c5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116297560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2
116297560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.1646602460
Short name T87
Test name
Test status
Simulation time 6665643652 ps
CPU time 42.48 seconds
Started Aug 08 06:24:54 PM PDT 24
Finished Aug 08 06:25:36 PM PDT 24
Peak memory 267896 kb
Host smart-7200216a-1724-4bc7-b0c8-600fbe99aee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646602460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1646602460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.646282681
Short name T887
Test name
Test status
Simulation time 440368927 ps
CPU time 2.77 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:24:53 PM PDT 24
Peak memory 217612 kb
Host smart-5a8c8a9d-dbef-4785-af09-30dbdd4c448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646282681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.646282681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.3095302109
Short name T9
Test name
Test status
Simulation time 81813497 ps
CPU time 1.28 seconds
Started Aug 08 06:24:54 PM PDT 24
Finished Aug 08 06:24:55 PM PDT 24
Peak memory 218728 kb
Host smart-93f13c2b-42b6-4018-a305-446266e2a159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095302109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3095302109 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_sideload.3452395967
Short name T960
Test name
Test status
Simulation time 8074319637 ps
CPU time 206.55 seconds
Started Aug 08 06:24:54 PM PDT 24
Finished Aug 08 06:28:21 PM PDT 24
Peak memory 441208 kb
Host smart-9b5b3dbe-a7cb-4af3-9df4-f0ef4f599117
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452395967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3452395967 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.1389523070
Short name T743
Test name
Test status
Simulation time 16111744669 ps
CPU time 55.42 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:25:45 PM PDT 24
Peak memory 224116 kb
Host smart-54e6b5e5-c3a3-4077-a376-fcdec2370ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389523070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1389523070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.1665402736
Short name T856
Test name
Test status
Simulation time 21679458522 ps
CPU time 1862.13 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:55:52 PM PDT 24
Peak memory 693992 kb
Host smart-83b1b897-6b92-4687-859e-c529842fc060
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1665402736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1665402736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.3681288515
Short name T505
Test name
Test status
Simulation time 176310960 ps
CPU time 4.85 seconds
Started Aug 08 06:24:48 PM PDT 24
Finished Aug 08 06:24:53 PM PDT 24
Peak memory 217752 kb
Host smart-ab863612-20ab-4a34-8ec9-6c40580581d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681288515 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.3681288515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.3992744549
Short name T882
Test name
Test status
Simulation time 594240117 ps
CPU time 4.71 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:24:55 PM PDT 24
Peak memory 218020 kb
Host smart-6dcef969-d88c-4afc-b83e-0241fc6a63a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992744549 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.3992744549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.823714157
Short name T619
Test name
Test status
Simulation time 102097171967 ps
CPU time 3511.91 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 07:23:22 PM PDT 24
Peak memory 3263108 kb
Host smart-ea725434-4528-459e-95c7-ca2cb845642d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=823714157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.823714157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.3143199901
Short name T560
Test name
Test status
Simulation time 94040053191 ps
CPU time 3123.41 seconds
Started Aug 08 06:24:55 PM PDT 24
Finished Aug 08 07:16:58 PM PDT 24
Peak memory 3106820 kb
Host smart-fa88a8eb-2ffc-4bdb-adea-901f023d65d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3143199901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.3143199901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.403580000
Short name T765
Test name
Test status
Simulation time 63072257834 ps
CPU time 2074.51 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:59:25 PM PDT 24
Peak memory 2373584 kb
Host smart-1af09412-4d1d-462e-b244-881608ae5332
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=403580000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.403580000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.3404453541
Short name T1036
Test name
Test status
Simulation time 407239929185 ps
CPU time 1517.49 seconds
Started Aug 08 06:24:49 PM PDT 24
Finished Aug 08 06:50:07 PM PDT 24
Peak memory 1724016 kb
Host smart-b7a355d0-1bae-4a52-96b0-792ba4374cae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3404453541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3404453541 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.57114628
Short name T501
Test name
Test status
Simulation time 50928464377 ps
CPU time 5468.51 seconds
Started Aug 08 06:24:53 PM PDT 24
Finished Aug 08 07:56:02 PM PDT 24
Peak memory 2697792 kb
Host smart-f9267ec6-bf21-4507-9a1b-f3580e848e43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=57114628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.57114628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.1796939451
Short name T990
Test name
Test status
Simulation time 904545363856 ps
CPU time 9756.75 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 09:07:29 PM PDT 24
Peak memory 6403944 kb
Host smart-e1f612d2-4fb6-4777-9dfc-01b304089208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1796939451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1796939451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.1583645104
Short name T493
Test name
Test status
Simulation time 24082684 ps
CPU time 0.84 seconds
Started Aug 08 06:24:57 PM PDT 24
Finished Aug 08 06:24:58 PM PDT 24
Peak memory 205140 kb
Host smart-01d96a36-6917-47f7-ac58-5438207adce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583645104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.1583645104 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.3369749822
Short name T519
Test name
Test status
Simulation time 65019418435 ps
CPU time 317.61 seconds
Started Aug 08 06:25:00 PM PDT 24
Finished Aug 08 06:30:18 PM PDT 24
Peak memory 477732 kb
Host smart-3744ab45-ed16-476e-946b-f24017eab3c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369749822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3369749822 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.4025347668
Short name T73
Test name
Test status
Simulation time 894477157 ps
CPU time 32.13 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:25:23 PM PDT 24
Peak memory 219564 kb
Host smart-eeee9e6c-8377-4883-a6df-aabe794ef976
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025347668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.402534766
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.3602418114
Short name T24
Test name
Test status
Simulation time 3839096804 ps
CPU time 68.23 seconds
Started Aug 08 06:24:58 PM PDT 24
Finished Aug 08 06:26:06 PM PDT 24
Peak memory 275464 kb
Host smart-c3f9fdb4-24be-4958-af65-4ab74c92c3d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602418114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3
602418114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.163286001
Short name T294
Test name
Test status
Simulation time 4870687972 ps
CPU time 25.21 seconds
Started Aug 08 06:25:00 PM PDT 24
Finished Aug 08 06:25:26 PM PDT 24
Peak memory 248708 kb
Host smart-83f07397-7553-4c5a-85cb-04a981837dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163286001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.163286001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.1026978732
Short name T426
Test name
Test status
Simulation time 3412223864 ps
CPU time 3.96 seconds
Started Aug 08 06:24:59 PM PDT 24
Finished Aug 08 06:25:04 PM PDT 24
Peak memory 217896 kb
Host smart-4e4bd7c6-eb95-40fd-a813-1282d5bb7c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026978732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1026978732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1063231224
Short name T98
Test name
Test status
Simulation time 101290281 ps
CPU time 1.19 seconds
Started Aug 08 06:25:00 PM PDT 24
Finished Aug 08 06:25:01 PM PDT 24
Peak memory 219196 kb
Host smart-1f0c612d-23cc-4ee6-8cbd-1cd1deb80005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063231224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1063231224 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.19045559
Short name T302
Test name
Test status
Simulation time 54476906990 ps
CPU time 1925.74 seconds
Started Aug 08 06:24:52 PM PDT 24
Finished Aug 08 06:56:58 PM PDT 24
Peak memory 2246556 kb
Host smart-536632b9-7564-46a0-97d1-9aa0a2ec43c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19045559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and
_output.19045559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.1932848318
Short name T429
Test name
Test status
Simulation time 23271746915 ps
CPU time 335.56 seconds
Started Aug 08 06:24:52 PM PDT 24
Finished Aug 08 06:30:28 PM PDT 24
Peak memory 365188 kb
Host smart-b8602a41-51e8-4d73-adb4-f047c3d6e74e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932848318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1932848318 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.141564651
Short name T624
Test name
Test status
Simulation time 1461066839 ps
CPU time 20.78 seconds
Started Aug 08 06:24:54 PM PDT 24
Finished Aug 08 06:25:15 PM PDT 24
Peak memory 217900 kb
Host smart-53705a3b-3028-4caa-8c2d-64a98d644811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141564651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.141564651 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.2387831646
Short name T890
Test name
Test status
Simulation time 78919894754 ps
CPU time 658.28 seconds
Started Aug 08 06:24:59 PM PDT 24
Finished Aug 08 06:35:57 PM PDT 24
Peak memory 1014032 kb
Host smart-0ba78388-67c2-44e9-8ad8-df2736620bbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2387831646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2387831646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.2873420369
Short name T587
Test name
Test status
Simulation time 351182981 ps
CPU time 4.68 seconds
Started Aug 08 06:24:50 PM PDT 24
Finished Aug 08 06:24:55 PM PDT 24
Peak memory 217976 kb
Host smart-168142a2-0bba-4857-91da-f4b90fe1afe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873420369 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.2873420369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3088950816
Short name T792
Test name
Test status
Simulation time 3220069279 ps
CPU time 5.06 seconds
Started Aug 08 06:24:58 PM PDT 24
Finished Aug 08 06:25:03 PM PDT 24
Peak memory 218160 kb
Host smart-62e116b3-acca-4648-a22c-d9e0a349cd5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088950816 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3088950816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.408026736
Short name T415
Test name
Test status
Simulation time 98778529080 ps
CPU time 1894.46 seconds
Started Aug 08 06:24:51 PM PDT 24
Finished Aug 08 06:56:26 PM PDT 24
Peak memory 1190780 kb
Host smart-ae548c81-d9a5-48b2-99e2-e2768edb4c81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=408026736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.408026736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.510307961
Short name T343
Test name
Test status
Simulation time 265356058946 ps
CPU time 2784.95 seconds
Started Aug 08 06:24:52 PM PDT 24
Finished Aug 08 07:11:18 PM PDT 24
Peak memory 3048492 kb
Host smart-09175374-99dd-4258-a22d-3460d4eb8e41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=510307961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.510307961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.1096228787
Short name T849
Test name
Test status
Simulation time 27457684958 ps
CPU time 1298.39 seconds
Started Aug 08 06:24:52 PM PDT 24
Finished Aug 08 06:46:30 PM PDT 24
Peak memory 908356 kb
Host smart-455b485e-9c8e-4a8e-aeb4-d13818d91aa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1096228787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.1096228787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.2574356718
Short name T855
Test name
Test status
Simulation time 123829926268 ps
CPU time 1272.74 seconds
Started Aug 08 06:24:53 PM PDT 24
Finished Aug 08 06:46:06 PM PDT 24
Peak memory 1698564 kb
Host smart-c8cefdf7-28e5-4b28-abf4-443391d0a6f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2574356718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.2574356718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.3806132547
Short name T216
Test name
Test status
Simulation time 805501668412 ps
CPU time 8795.33 seconds
Started Aug 08 06:24:54 PM PDT 24
Finished Aug 08 08:51:30 PM PDT 24
Peak memory 6370168 kb
Host smart-38483aba-feb8-4dc6-967d-fb06af85172b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3806132547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.3806132547 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.3756590032
Short name T808
Test name
Test status
Simulation time 26167859 ps
CPU time 0.79 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 06:25:09 PM PDT 24
Peak memory 205128 kb
Host smart-585b4fe1-e21d-4a4d-9758-f04d8958c932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756590032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3756590032 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.3679940331
Short name T989
Test name
Test status
Simulation time 54031179765 ps
CPU time 174.58 seconds
Started Aug 08 06:25:01 PM PDT 24
Finished Aug 08 06:27:56 PM PDT 24
Peak memory 354716 kb
Host smart-9c0902f6-90f9-4c3d-ab62-3a955c8b109e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679940331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3679940331 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.537005117
Short name T161
Test name
Test status
Simulation time 7074641581 ps
CPU time 123.64 seconds
Started Aug 08 06:24:57 PM PDT 24
Finished Aug 08 06:27:01 PM PDT 24
Peak memory 322668 kb
Host smart-8e91470b-933d-4e62-9707-1ea7a1530f2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537005117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.53
7005117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.3060539538
Short name T641
Test name
Test status
Simulation time 905857483 ps
CPU time 73.96 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 06:26:22 PM PDT 24
Peak memory 260440 kb
Host smart-6e3eb267-08be-4009-97f7-dcf5bcd94810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060539538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3060539538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.819230888
Short name T63
Test name
Test status
Simulation time 1517995086 ps
CPU time 7.39 seconds
Started Aug 08 06:25:10 PM PDT 24
Finished Aug 08 06:25:17 PM PDT 24
Peak memory 217852 kb
Host smart-75ccbe6b-9b02-41d6-9ed2-683572909acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819230888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.819230888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.3973473505
Short name T754
Test name
Test status
Simulation time 29029269 ps
CPU time 1.37 seconds
Started Aug 08 06:25:10 PM PDT 24
Finished Aug 08 06:25:12 PM PDT 24
Peak memory 218232 kb
Host smart-f160dd08-ade7-494a-8fa7-b8631bc81059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973473505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3973473505 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.898021655
Short name T595
Test name
Test status
Simulation time 43237924429 ps
CPU time 1302.04 seconds
Started Aug 08 06:25:01 PM PDT 24
Finished Aug 08 06:46:43 PM PDT 24
Peak memory 1648012 kb
Host smart-30f17655-8b66-4a5f-98ac-edb8efea9aff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898021655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an
d_output.898021655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3814522300
Short name T333
Test name
Test status
Simulation time 651076676 ps
CPU time 47.96 seconds
Started Aug 08 06:24:59 PM PDT 24
Finished Aug 08 06:25:47 PM PDT 24
Peak memory 240784 kb
Host smart-62515f1f-3881-4f7e-99ef-8091acc1df3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814522300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3814522300 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2101526066
Short name T970
Test name
Test status
Simulation time 3692156647 ps
CPU time 53.34 seconds
Started Aug 08 06:24:58 PM PDT 24
Finished Aug 08 06:25:52 PM PDT 24
Peak memory 217912 kb
Host smart-d6fb8222-490b-4321-9c46-826786df1ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101526066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2101526066 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.591359175
Short name T32
Test name
Test status
Simulation time 92750846835 ps
CPU time 103.85 seconds
Started Aug 08 06:25:10 PM PDT 24
Finished Aug 08 06:26:55 PM PDT 24
Peak memory 288676 kb
Host smart-ce393c9a-177e-4e54-85df-e4cb246579db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=591359175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.591359175 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.3519568070
Short name T367
Test name
Test status
Simulation time 164437855 ps
CPU time 4.53 seconds
Started Aug 08 06:24:59 PM PDT 24
Finished Aug 08 06:25:04 PM PDT 24
Peak memory 218040 kb
Host smart-51773d2b-6087-4761-a8e6-d03f3e85383c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519568070 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.3519568070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.2585154506
Short name T1005
Test name
Test status
Simulation time 2865957110 ps
CPU time 5.69 seconds
Started Aug 08 06:25:01 PM PDT 24
Finished Aug 08 06:25:07 PM PDT 24
Peak memory 218296 kb
Host smart-36fbd1fc-cff1-43da-ab72-71ae7a5d9f31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585154506 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.2585154506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.2921766986
Short name T200
Test name
Test status
Simulation time 65652024337 ps
CPU time 2853.32 seconds
Started Aug 08 06:24:59 PM PDT 24
Finished Aug 08 07:12:33 PM PDT 24
Peak memory 3171788 kb
Host smart-dbf5ec06-0efd-466a-bb5d-25bb9802f845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2921766986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2921766986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.3110791532
Short name T819
Test name
Test status
Simulation time 78361856945 ps
CPU time 2886.92 seconds
Started Aug 08 06:25:00 PM PDT 24
Finished Aug 08 07:13:07 PM PDT 24
Peak memory 3014812 kb
Host smart-c7e2bea4-c83d-4e52-b1ad-ab52a178a15e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3110791532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.3110791532 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.733148440
Short name T197
Test name
Test status
Simulation time 97028821244 ps
CPU time 2038.88 seconds
Started Aug 08 06:24:58 PM PDT 24
Finished Aug 08 06:58:57 PM PDT 24
Peak memory 2371580 kb
Host smart-1c431db6-d89b-435c-a8f6-b2d67741e9c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=733148440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.733148440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.3883968610
Short name T658
Test name
Test status
Simulation time 68870008738 ps
CPU time 1289.19 seconds
Started Aug 08 06:24:59 PM PDT 24
Finished Aug 08 06:46:29 PM PDT 24
Peak memory 1743476 kb
Host smart-2ed1b095-ced7-45bf-941d-6bb0155a2c48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3883968610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.3883968610 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.3784914785
Short name T326
Test name
Test status
Simulation time 1204609399643 ps
CPU time 8903.92 seconds
Started Aug 08 06:24:58 PM PDT 24
Finished Aug 08 08:53:24 PM PDT 24
Peak memory 6358548 kb
Host smart-7746c28c-9f25-494a-a189-3a408ebf797a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3784914785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.3784914785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.1936908537
Short name T355
Test name
Test status
Simulation time 26398946 ps
CPU time 0.77 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:25:19 PM PDT 24
Peak memory 205220 kb
Host smart-5b50c8e2-5b18-4faa-b9e6-e6eb220cae04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936908537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1936908537 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.710390298
Short name T987
Test name
Test status
Simulation time 69105311301 ps
CPU time 188.63 seconds
Started Aug 08 06:25:20 PM PDT 24
Finished Aug 08 06:28:29 PM PDT 24
Peak memory 371848 kb
Host smart-64208d81-99e5-41d8-a406-1a08189cca93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710390298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.710390298 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.1020804762
Short name T713
Test name
Test status
Simulation time 8970010058 ps
CPU time 406.41 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 06:31:55 PM PDT 24
Peak memory 233912 kb
Host smart-143c4a60-2560-4e01-b6e2-a4b46e6e6706
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020804762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.102080476
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.3117027411
Short name T676
Test name
Test status
Simulation time 3197668252 ps
CPU time 45.45 seconds
Started Aug 08 06:25:20 PM PDT 24
Finished Aug 08 06:26:06 PM PDT 24
Peak memory 253984 kb
Host smart-ff0d6e85-cb26-4f74-8d64-7ea33546cecd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117027411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3
117027411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.2782672742
Short name T516
Test name
Test status
Simulation time 51523025944 ps
CPU time 440.03 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:32:38 PM PDT 24
Peak memory 564488 kb
Host smart-8a242d22-0a31-4083-bd30-c69584f8c676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782672742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2782672742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.733196549
Short name T295
Test name
Test status
Simulation time 5012986776 ps
CPU time 8.62 seconds
Started Aug 08 06:25:17 PM PDT 24
Finished Aug 08 06:25:26 PM PDT 24
Peak memory 218120 kb
Host smart-a4980f2d-1ae3-472e-a6bf-6c6cfcaffbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733196549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.733196549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.2154121188
Short name T621
Test name
Test status
Simulation time 8136618073 ps
CPU time 26.6 seconds
Started Aug 08 06:25:20 PM PDT 24
Finished Aug 08 06:25:47 PM PDT 24
Peak memory 251404 kb
Host smart-2f05459c-0cae-4a97-9c44-c735b9dcddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154121188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2154121188 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.2460806018
Short name T594
Test name
Test status
Simulation time 19480996118 ps
CPU time 2002.42 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 06:58:31 PM PDT 24
Peak memory 1369576 kb
Host smart-6b214c6b-62bb-46c0-9c07-bc99274ef884
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460806018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.2460806018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.3375627644
Short name T244
Test name
Test status
Simulation time 14282219279 ps
CPU time 430.71 seconds
Started Aug 08 06:25:09 PM PDT 24
Finished Aug 08 06:32:20 PM PDT 24
Peak memory 587724 kb
Host smart-f21a74ab-6eff-4f60-b11c-340478af1d62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375627644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3375627644 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.992702100
Short name T1003
Test name
Test status
Simulation time 120160508 ps
CPU time 3.29 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 06:25:11 PM PDT 24
Peak memory 218172 kb
Host smart-f761c968-d928-4c8d-b044-b594382eca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992702100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.992702100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.2054142356
Short name T1012
Test name
Test status
Simulation time 91083396279 ps
CPU time 251.78 seconds
Started Aug 08 06:25:17 PM PDT 24
Finished Aug 08 06:29:29 PM PDT 24
Peak memory 322024 kb
Host smart-fe9925c6-3782-439b-93db-4631aef8be8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2054142356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2054142356 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.1479681057
Short name T156
Test name
Test status
Simulation time 268055251 ps
CPU time 5.59 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 06:25:14 PM PDT 24
Peak memory 218060 kb
Host smart-2c0fc6cb-5f7b-4980-9eb4-2f1dd6cca6c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479681057 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.1479681057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.3076010764
Short name T327
Test name
Test status
Simulation time 896262129 ps
CPU time 4.56 seconds
Started Aug 08 06:25:17 PM PDT 24
Finished Aug 08 06:25:22 PM PDT 24
Peak memory 218052 kb
Host smart-c10d10e1-e2eb-4042-b383-bd034583671c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076010764 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.3076010764 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.3390701021
Short name T733
Test name
Test status
Simulation time 38290380613 ps
CPU time 1840.68 seconds
Started Aug 08 06:25:09 PM PDT 24
Finished Aug 08 06:55:50 PM PDT 24
Peak memory 1191504 kb
Host smart-5e489fb4-eb62-4939-8e42-9c40d354a6c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3390701021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.3390701021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.1963084095
Short name T720
Test name
Test status
Simulation time 124219231937 ps
CPU time 1698.15 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 06:53:26 PM PDT 24
Peak memory 1114108 kb
Host smart-85f44476-e7dd-4bff-bb4b-661a38d34940
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1963084095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.1963084095 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3531329660
Short name T2
Test name
Test status
Simulation time 13747817894 ps
CPU time 1454.32 seconds
Started Aug 08 06:25:10 PM PDT 24
Finished Aug 08 06:49:24 PM PDT 24
Peak memory 926072 kb
Host smart-611d585f-25e3-451a-8140-0dc10a5c1b75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3531329660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3531329660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2172375703
Short name T242
Test name
Test status
Simulation time 302077696927 ps
CPU time 1527 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 06:50:35 PM PDT 24
Peak memory 1707496 kb
Host smart-2b3ec784-9f5c-420e-beaa-7af706d9f0f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2172375703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2172375703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.681123549
Short name T461
Test name
Test status
Simulation time 50541959501 ps
CPU time 5727.48 seconds
Started Aug 08 06:25:08 PM PDT 24
Finished Aug 08 08:00:36 PM PDT 24
Peak memory 2670592 kb
Host smart-f0e7d9cf-cb75-4930-8465-578375755b1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=681123549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.681123549 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.3558016845
Short name T922
Test name
Test status
Simulation time 180900228013 ps
CPU time 4343.34 seconds
Started Aug 08 06:25:09 PM PDT 24
Finished Aug 08 07:37:33 PM PDT 24
Peak memory 2227768 kb
Host smart-09503a69-0230-40de-9c42-b912aab511be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3558016845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.3558016845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.6856149
Short name T879
Test name
Test status
Simulation time 94090761 ps
CPU time 0.76 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:25:19 PM PDT 24
Peak memory 205212 kb
Host smart-3274b7ff-409a-4452-9ad2-16e02a143d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6856149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.6856149 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.4265556759
Short name T455
Test name
Test status
Simulation time 986072310 ps
CPU time 62.27 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:26:20 PM PDT 24
Peak memory 244684 kb
Host smart-04320bf5-7c7b-4679-80b5-f447b5cb348d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265556759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.4265556759 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.2613581282
Short name T153
Test name
Test status
Simulation time 4379436740 ps
CPU time 173.55 seconds
Started Aug 08 06:25:17 PM PDT 24
Finished Aug 08 06:28:10 PM PDT 24
Peak memory 226176 kb
Host smart-bac15eb8-4998-44bb-97b6-a780df0267f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613581282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.261358128
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.2914843925
Short name T556
Test name
Test status
Simulation time 2428569050 ps
CPU time 52.81 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:26:11 PM PDT 24
Peak memory 266756 kb
Host smart-52b3c215-f3cf-4d2c-8f9f-80ea64232364
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914843925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2
914843925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.603633656
Short name T336
Test name
Test status
Simulation time 24526760844 ps
CPU time 194.99 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:28:33 PM PDT 24
Peak memory 404196 kb
Host smart-78803f21-e0b9-41d1-8e3d-c77be1d14409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603633656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.603633656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.3556008260
Short name T739
Test name
Test status
Simulation time 5395375676 ps
CPU time 8.25 seconds
Started Aug 08 06:25:17 PM PDT 24
Finished Aug 08 06:25:26 PM PDT 24
Peak memory 218048 kb
Host smart-c0da1d11-c8ec-4b0c-93bd-392733f06a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556008260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3556008260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.3123055091
Short name T734
Test name
Test status
Simulation time 68401903 ps
CPU time 1.41 seconds
Started Aug 08 06:25:20 PM PDT 24
Finished Aug 08 06:25:22 PM PDT 24
Peak memory 217372 kb
Host smart-d2c778f4-cc86-4165-83de-ecab2081f355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123055091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3123055091 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.2221096684
Short name T848
Test name
Test status
Simulation time 8158501972 ps
CPU time 254.9 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:29:33 PM PDT 24
Peak memory 389620 kb
Host smart-ed9395d9-49f9-4209-aa95-9ed0ce4b9c87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221096684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.2221096684 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.3914355388
Short name T951
Test name
Test status
Simulation time 40505201743 ps
CPU time 373.5 seconds
Started Aug 08 06:25:17 PM PDT 24
Finished Aug 08 06:31:31 PM PDT 24
Peak memory 545884 kb
Host smart-eb0a995e-5605-4bd8-ae87-b8aa12bacb7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914355388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3914355388 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.2732348540
Short name T669
Test name
Test status
Simulation time 5916928370 ps
CPU time 50.78 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:26:09 PM PDT 24
Peak memory 217964 kb
Host smart-f291fe99-b02a-44a6-91b3-7190f948a882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732348540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2732348540 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.3638928793
Short name T667
Test name
Test status
Simulation time 25888986877 ps
CPU time 437.72 seconds
Started Aug 08 06:25:20 PM PDT 24
Finished Aug 08 06:32:37 PM PDT 24
Peak memory 435860 kb
Host smart-f6a04f4e-db4e-4438-99fe-f586ec5f5edb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3638928793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3638928793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.3175136039
Short name T760
Test name
Test status
Simulation time 237322526 ps
CPU time 5.09 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:25:24 PM PDT 24
Peak memory 217872 kb
Host smart-f65d98e8-f6aa-4727-a040-a27f99af0563
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175136039 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.3175136039 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.2673277233
Short name T413
Test name
Test status
Simulation time 500606100 ps
CPU time 5.51 seconds
Started Aug 08 06:25:20 PM PDT 24
Finished Aug 08 06:25:26 PM PDT 24
Peak memory 217748 kb
Host smart-0b55fa8a-7b77-4782-885e-9f2ec543ff59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673277233 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.2673277233 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.2632289173
Short name T412
Test name
Test status
Simulation time 234593313156 ps
CPU time 3337.47 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 07:20:56 PM PDT 24
Peak memory 3238284 kb
Host smart-4ac6f906-fd1a-4268-ac57-ebf6d25c717d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2632289173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2632289173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.4033521212
Short name T745
Test name
Test status
Simulation time 17754929228 ps
CPU time 1794.87 seconds
Started Aug 08 06:25:17 PM PDT 24
Finished Aug 08 06:55:12 PM PDT 24
Peak memory 1137696 kb
Host smart-f329c9a8-c6cf-46e8-a4de-7b6d0047904d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4033521212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.4033521212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.706636118
Short name T900
Test name
Test status
Simulation time 234540147181 ps
CPU time 2210.84 seconds
Started Aug 08 06:25:17 PM PDT 24
Finished Aug 08 07:02:09 PM PDT 24
Peak memory 2398480 kb
Host smart-c7eea424-1aae-43de-88b6-74f32e861ae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=706636118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.706636118 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.227982219
Short name T250
Test name
Test status
Simulation time 135509000895 ps
CPU time 1314.85 seconds
Started Aug 08 06:25:19 PM PDT 24
Finished Aug 08 06:47:14 PM PDT 24
Peak memory 1717624 kb
Host smart-0b8b04ff-cce9-4adf-b3f7-c2f9d35e59a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=227982219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.227982219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.2708411990
Short name T572
Test name
Test status
Simulation time 473742307053 ps
CPU time 4721.15 seconds
Started Aug 08 06:25:21 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 2178364 kb
Host smart-c791b5a3-275c-4953-ac5d-698a6c77633a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2708411990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.2708411990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1406634476
Short name T19
Test name
Test status
Simulation time 14078221 ps
CPU time 0.78 seconds
Started Aug 08 06:25:37 PM PDT 24
Finished Aug 08 06:25:38 PM PDT 24
Peak memory 205140 kb
Host smart-159b772f-a695-4195-8bda-fb1b54075919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406634476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1406634476 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.1489180287
Short name T393
Test name
Test status
Simulation time 14135152212 ps
CPU time 291.63 seconds
Started Aug 08 06:25:27 PM PDT 24
Finished Aug 08 06:30:19 PM PDT 24
Peak memory 475180 kb
Host smart-3efd7a00-19e8-418b-abdd-fc29bdd1970b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489180287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1489180287 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.1010112749
Short name T675
Test name
Test status
Simulation time 80451977460 ps
CPU time 516.86 seconds
Started Aug 08 06:25:27 PM PDT 24
Finished Aug 08 06:34:04 PM PDT 24
Peak memory 241100 kb
Host smart-63db6d03-1c29-4a2e-90e3-2f4061c4426c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010112749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.101011274
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.2751656119
Short name T265
Test name
Test status
Simulation time 652209160 ps
CPU time 10.63 seconds
Started Aug 08 06:25:25 PM PDT 24
Finished Aug 08 06:25:36 PM PDT 24
Peak memory 223992 kb
Host smart-d8e86d6a-839b-4ce1-a615-520dcf21745a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751656119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2
751656119 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.1556942620
Short name T172
Test name
Test status
Simulation time 8205918650 ps
CPU time 353.19 seconds
Started Aug 08 06:25:28 PM PDT 24
Finished Aug 08 06:31:21 PM PDT 24
Peak memory 373088 kb
Host smart-e3dc37ad-fd9c-4101-bfeb-fe6ab231b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556942620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1556942620 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.4263073799
Short name T908
Test name
Test status
Simulation time 1469765906 ps
CPU time 3.05 seconds
Started Aug 08 06:25:25 PM PDT 24
Finished Aug 08 06:25:28 PM PDT 24
Peak memory 217968 kb
Host smart-9d5f6f00-fa62-4370-9037-96f995c5131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263073799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.4263073799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.3354424670
Short name T4
Test name
Test status
Simulation time 136824255 ps
CPU time 1.55 seconds
Started Aug 08 06:25:26 PM PDT 24
Finished Aug 08 06:25:28 PM PDT 24
Peak memory 217304 kb
Host smart-8827c320-b021-4055-ad7e-61f43d8c7f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354424670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3354424670 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.4059648460
Short name T823
Test name
Test status
Simulation time 8853712381 ps
CPU time 882.5 seconds
Started Aug 08 06:25:27 PM PDT 24
Finished Aug 08 06:40:10 PM PDT 24
Peak memory 697432 kb
Host smart-66af7155-8e8c-4818-b03d-f9f2b8ce0618
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059648460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.4059648460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.3895432097
Short name T875
Test name
Test status
Simulation time 16180744309 ps
CPU time 419.07 seconds
Started Aug 08 06:25:24 PM PDT 24
Finished Aug 08 06:32:23 PM PDT 24
Peak memory 586372 kb
Host smart-7d8db489-9c88-49df-bc94-d8726629bf8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895432097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3895432097 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.1590010290
Short name T776
Test name
Test status
Simulation time 3069387440 ps
CPU time 39.49 seconds
Started Aug 08 06:25:18 PM PDT 24
Finished Aug 08 06:25:58 PM PDT 24
Peak memory 223176 kb
Host smart-a6d1c6d6-77bc-42c6-9517-9012e329ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590010290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1590010290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.3490468082
Short name T92
Test name
Test status
Simulation time 37791517522 ps
CPU time 1122.83 seconds
Started Aug 08 06:25:35 PM PDT 24
Finished Aug 08 06:44:18 PM PDT 24
Peak memory 614980 kb
Host smart-5c658dc4-5f39-4aa2-bb40-8b969688663f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3490468082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3490468082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1284712294
Short name T837
Test name
Test status
Simulation time 335957059 ps
CPU time 4.99 seconds
Started Aug 08 06:25:26 PM PDT 24
Finished Aug 08 06:25:31 PM PDT 24
Peak memory 218044 kb
Host smart-577e5d85-2825-42bb-afc4-052d48529321
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284712294 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1284712294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2722548573
Short name T470
Test name
Test status
Simulation time 290032817 ps
CPU time 4.58 seconds
Started Aug 08 06:25:26 PM PDT 24
Finished Aug 08 06:25:31 PM PDT 24
Peak memory 217776 kb
Host smart-92944cb2-8762-44e8-bc14-b301fe9058e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722548573 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2722548573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.1059213912
Short name T409
Test name
Test status
Simulation time 465259027424 ps
CPU time 3402.78 seconds
Started Aug 08 06:25:25 PM PDT 24
Finished Aug 08 07:22:09 PM PDT 24
Peak memory 3243420 kb
Host smart-bf8993b9-79e4-4a87-a038-f746c2958cfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1059213912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1059213912 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.4223705186
Short name T234
Test name
Test status
Simulation time 181916237707 ps
CPU time 3140.82 seconds
Started Aug 08 06:25:25 PM PDT 24
Finished Aug 08 07:17:47 PM PDT 24
Peak memory 3033676 kb
Host smart-7af9cb25-e756-483c-9d78-0ad2bf683657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4223705186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.4223705186 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.132117088
Short name T708
Test name
Test status
Simulation time 48065841912 ps
CPU time 2039.62 seconds
Started Aug 08 06:25:25 PM PDT 24
Finished Aug 08 06:59:25 PM PDT 24
Peak memory 2350080 kb
Host smart-f1757a56-adc0-4747-aa39-4d4c2e067779
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=132117088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.132117088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.3232940315
Short name T844
Test name
Test status
Simulation time 38461772131 ps
CPU time 936.54 seconds
Started Aug 08 06:25:25 PM PDT 24
Finished Aug 08 06:41:02 PM PDT 24
Peak memory 707888 kb
Host smart-84ed584b-1dc6-4e53-8c6d-70fb9ddc05d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3232940315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3232940315 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.3020110497
Short name T775
Test name
Test status
Simulation time 56691601337 ps
CPU time 5287.36 seconds
Started Aug 08 06:25:27 PM PDT 24
Finished Aug 08 07:53:35 PM PDT 24
Peak memory 2666396 kb
Host smart-1002db06-e082-421f-bec1-95a53ebf95bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3020110497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.3020110497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_alert_test.1631898609
Short name T812
Test name
Test status
Simulation time 17612735 ps
CPU time 0.71 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:25:35 PM PDT 24
Peak memory 205232 kb
Host smart-4f0136fe-da9b-454b-bfaa-17b3271ad683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631898609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1631898609 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.3872478584
Short name T46
Test name
Test status
Simulation time 4498168749 ps
CPU time 180.83 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:28:35 PM PDT 24
Peak memory 302456 kb
Host smart-0d37797c-5702-4295-b581-35abad819564
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872478584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3872478584 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.1311346919
Short name T914
Test name
Test status
Simulation time 136048710912 ps
CPU time 1052.9 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:43:07 PM PDT 24
Peak memory 256508 kb
Host smart-c5a75f61-a4a3-421b-9d27-ad71877feb03
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311346919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.131134691
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.1827498706
Short name T611
Test name
Test status
Simulation time 5174286327 ps
CPU time 187.33 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:28:41 PM PDT 24
Peak memory 300988 kb
Host smart-02aa6ce3-55d2-412b-b5c8-1fe947dbf493
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827498706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1
827498706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_key_error.4167782861
Short name T618
Test name
Test status
Simulation time 1096927882 ps
CPU time 3.75 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:25:38 PM PDT 24
Peak memory 219148 kb
Host smart-6ea9cb78-5379-4e35-ac4b-28e9635170b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167782861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.4167782861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.649019668
Short name T485
Test name
Test status
Simulation time 56120785 ps
CPU time 1.33 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:25:35 PM PDT 24
Peak memory 218376 kb
Host smart-4f833374-27f4-4a96-b990-49a9b609899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649019668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.649019668 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.1449829922
Short name T478
Test name
Test status
Simulation time 11331416505 ps
CPU time 162.88 seconds
Started Aug 08 06:25:36 PM PDT 24
Finished Aug 08 06:28:19 PM PDT 24
Peak memory 317408 kb
Host smart-ba563b80-f63c-4011-a561-45f850eda01a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449829922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.1449829922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.1045656168
Short name T264
Test name
Test status
Simulation time 6694280833 ps
CPU time 165.02 seconds
Started Aug 08 06:25:38 PM PDT 24
Finished Aug 08 06:28:23 PM PDT 24
Peak memory 365924 kb
Host smart-23f2689a-e630-4840-ac98-d3efa1db4130
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045656168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1045656168 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.3569230353
Short name T806
Test name
Test status
Simulation time 629336257 ps
CPU time 2.42 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:25:37 PM PDT 24
Peak memory 217664 kb
Host smart-2504c661-f6e2-4e0f-839c-4cfabf53c5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569230353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3569230353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.4267017519
Short name T374
Test name
Test status
Simulation time 27106260731 ps
CPU time 740.99 seconds
Started Aug 08 06:25:33 PM PDT 24
Finished Aug 08 06:37:55 PM PDT 24
Peak memory 824304 kb
Host smart-ffb7c019-f317-4804-9036-9705812fd3c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4267017519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.4267017519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.1820956752
Short name T803
Test name
Test status
Simulation time 128732151 ps
CPU time 4.11 seconds
Started Aug 08 06:25:35 PM PDT 24
Finished Aug 08 06:25:39 PM PDT 24
Peak memory 217948 kb
Host smart-4de581e3-889f-4fa4-8bdd-f8e11c25eecd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820956752 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.1820956752 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.515250798
Short name T731
Test name
Test status
Simulation time 261642793 ps
CPU time 5.08 seconds
Started Aug 08 06:25:35 PM PDT 24
Finished Aug 08 06:25:40 PM PDT 24
Peak memory 217768 kb
Host smart-2c96006c-88aa-483c-8abe-4568033f0858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515250798 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.kmac_test_vectors_kmac_xof.515250798 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.3694085504
Short name T441
Test name
Test status
Simulation time 198706975633 ps
CPU time 3145.7 seconds
Started Aug 08 06:25:35 PM PDT 24
Finished Aug 08 07:18:01 PM PDT 24
Peak memory 3172036 kb
Host smart-4b86e6ce-ffed-4a39-a600-9eef3a0c35bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3694085504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.3694085504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.2474787766
Short name T74
Test name
Test status
Simulation time 162406437658 ps
CPU time 2667.1 seconds
Started Aug 08 06:25:35 PM PDT 24
Finished Aug 08 07:10:02 PM PDT 24
Peak memory 2999940 kb
Host smart-f49dd716-a83d-4bc3-bdbe-c3c5a4915d02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2474787766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.2474787766 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.3404427880
Short name T657
Test name
Test status
Simulation time 28911621044 ps
CPU time 1282.16 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:46:56 PM PDT 24
Peak memory 896596 kb
Host smart-bb13b9ca-2aa0-431d-998e-aa402f727292
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3404427880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3404427880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.30664448
Short name T1015
Test name
Test status
Simulation time 66672472311 ps
CPU time 1300.84 seconds
Started Aug 08 06:25:33 PM PDT 24
Finished Aug 08 06:47:14 PM PDT 24
Peak memory 1722852 kb
Host smart-bf46f754-68b9-4a6a-b0cb-df657d0a86b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=30664448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.30664448 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.1905034670
Short name T610
Test name
Test status
Simulation time 1551640913960 ps
CPU time 9327.41 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 09:01:03 PM PDT 24
Peak memory 6404700 kb
Host smart-38a82f69-5346-40d0-a7ab-e90b506a3f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1905034670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1905034670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.3904341671
Short name T884
Test name
Test status
Simulation time 55276783 ps
CPU time 0.82 seconds
Started Aug 08 06:25:42 PM PDT 24
Finished Aug 08 06:25:43 PM PDT 24
Peak memory 205264 kb
Host smart-7dd96ebd-4225-4f3c-8fe3-d57a3b56cd12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904341671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3904341671 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.1602321144
Short name T283
Test name
Test status
Simulation time 3115760918 ps
CPU time 77.23 seconds
Started Aug 08 06:25:44 PM PDT 24
Finished Aug 08 06:27:01 PM PDT 24
Peak memory 288832 kb
Host smart-1cfc2cee-b3b0-45ee-849e-4cf749a89853
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602321144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1602321144 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.2345269966
Short name T796
Test name
Test status
Simulation time 20456809213 ps
CPU time 642.86 seconds
Started Aug 08 06:25:43 PM PDT 24
Finished Aug 08 06:36:26 PM PDT 24
Peak memory 249076 kb
Host smart-73cd7085-c961-41bc-acd2-76e9c1e0a8de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345269966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.234526996
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.1315278692
Short name T432
Test name
Test status
Simulation time 87583834926 ps
CPU time 312.58 seconds
Started Aug 08 06:25:42 PM PDT 24
Finished Aug 08 06:30:55 PM PDT 24
Peak memory 434812 kb
Host smart-e152bdc3-4fec-4173-a93a-c7ac87391be3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315278692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1
315278692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.2367038902
Short name T173
Test name
Test status
Simulation time 14913189097 ps
CPU time 160.59 seconds
Started Aug 08 06:25:41 PM PDT 24
Finished Aug 08 06:28:22 PM PDT 24
Peak memory 294380 kb
Host smart-a531e9df-26a0-42fb-a494-8b701000a768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367038902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2367038902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.1438072597
Short name T20
Test name
Test status
Simulation time 730485897 ps
CPU time 4.16 seconds
Started Aug 08 06:25:42 PM PDT 24
Finished Aug 08 06:25:46 PM PDT 24
Peak memory 218084 kb
Host smart-503f2c27-4e82-4164-a749-2a1d1259a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438072597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1438072597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1205031835
Short name T39
Test name
Test status
Simulation time 35369126 ps
CPU time 1.24 seconds
Started Aug 08 06:25:42 PM PDT 24
Finished Aug 08 06:25:43 PM PDT 24
Peak memory 219136 kb
Host smart-f2874335-6617-43ba-96af-92548228c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205031835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1205031835 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.1325887931
Short name T376
Test name
Test status
Simulation time 83013674453 ps
CPU time 640.33 seconds
Started Aug 08 06:25:44 PM PDT 24
Finished Aug 08 06:36:24 PM PDT 24
Peak memory 1070156 kb
Host smart-40023a92-7f41-421c-ace6-bee7a2738f2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325887931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.1325887931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.1368521940
Short name T639
Test name
Test status
Simulation time 11110194319 ps
CPU time 323.76 seconds
Started Aug 08 06:25:43 PM PDT 24
Finished Aug 08 06:31:07 PM PDT 24
Peak memory 533960 kb
Host smart-c51bc134-8a57-4e1c-ac34-4f26190fb4bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368521940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1368521940 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.1732519858
Short name T498
Test name
Test status
Simulation time 708166016 ps
CPU time 27.79 seconds
Started Aug 08 06:25:34 PM PDT 24
Finished Aug 08 06:26:01 PM PDT 24
Peak memory 218052 kb
Host smart-edaaa9c7-0f90-4be2-9e58-a3c4ff4e8b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732519858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1732519858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.2035961732
Short name T964
Test name
Test status
Simulation time 2936468201 ps
CPU time 48 seconds
Started Aug 08 06:25:45 PM PDT 24
Finished Aug 08 06:26:33 PM PDT 24
Peak memory 256660 kb
Host smart-49b3c5bc-5bc2-4f32-8473-018f95a3fe97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2035961732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2035961732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.3148277539
Short name T277
Test name
Test status
Simulation time 628356279 ps
CPU time 3.9 seconds
Started Aug 08 06:25:44 PM PDT 24
Finished Aug 08 06:25:48 PM PDT 24
Peak memory 218044 kb
Host smart-485e5caa-8330-4eb2-89c7-0a9e028b890f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148277539 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.3148277539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3488492187
Short name T701
Test name
Test status
Simulation time 491350089 ps
CPU time 5.13 seconds
Started Aug 08 06:25:45 PM PDT 24
Finished Aug 08 06:25:50 PM PDT 24
Peak memory 217936 kb
Host smart-404a5df2-139e-4234-b226-190a8f57489e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488492187 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3488492187 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.1757797627
Short name T15
Test name
Test status
Simulation time 39274265557 ps
CPU time 2086.14 seconds
Started Aug 08 06:25:42 PM PDT 24
Finished Aug 08 07:00:28 PM PDT 24
Peak memory 1196392 kb
Host smart-d34ca59f-fef9-4dea-aaa4-27815dc8c2f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1757797627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.1757797627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.1501761120
Short name T944
Test name
Test status
Simulation time 65910441568 ps
CPU time 2038.56 seconds
Started Aug 08 06:25:44 PM PDT 24
Finished Aug 08 06:59:43 PM PDT 24
Peak memory 1139616 kb
Host smart-28c05ef0-c708-4d80-97fb-f5be5f635ffa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1501761120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.1501761120 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.2787012354
Short name T531
Test name
Test status
Simulation time 175353181801 ps
CPU time 2075.99 seconds
Started Aug 08 06:25:42 PM PDT 24
Finished Aug 08 07:00:19 PM PDT 24
Peak memory 2412544 kb
Host smart-dbc20f77-d17a-4bd4-b3c6-8356cb089d43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2787012354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.2787012354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.2035846592
Short name T474
Test name
Test status
Simulation time 48422124522 ps
CPU time 1469.04 seconds
Started Aug 08 06:25:42 PM PDT 24
Finished Aug 08 06:50:11 PM PDT 24
Peak memory 1709204 kb
Host smart-e75eefc9-f6a9-456a-a508-cc2efb1f8de8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2035846592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2035846592 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.2298439318
Short name T335
Test name
Test status
Simulation time 224433195662 ps
CPU time 9848.77 seconds
Started Aug 08 06:25:44 PM PDT 24
Finished Aug 08 09:09:54 PM PDT 24
Peak memory 6350196 kb
Host smart-d9419d55-e9a7-4fed-9fbf-17af03be0e36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2298439318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.2298439318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.459770855
Short name T358
Test name
Test status
Simulation time 119945640 ps
CPU time 0.77 seconds
Started Aug 08 06:23:17 PM PDT 24
Finished Aug 08 06:23:18 PM PDT 24
Peak memory 205216 kb
Host smart-729e5b07-0c57-4f39-97ec-bbc0d21d0dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459770855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.459770855 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.3869682951
Short name T576
Test name
Test status
Simulation time 10499110120 ps
CPU time 313.1 seconds
Started Aug 08 06:23:40 PM PDT 24
Finished Aug 08 06:28:54 PM PDT 24
Peak memory 478224 kb
Host smart-fd045af3-6f4c-4c8a-9f38-a89c4b0ccfb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869682951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3869682951 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.3020280075
Short name T476
Test name
Test status
Simulation time 20123035528 ps
CPU time 144.83 seconds
Started Aug 08 06:23:20 PM PDT 24
Finished Aug 08 06:25:45 PM PDT 24
Peak memory 275612 kb
Host smart-f43b40f6-d2a9-4b1a-b4fb-281e95f617c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020280075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.3020280075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.147142053
Short name T690
Test name
Test status
Simulation time 33776229162 ps
CPU time 790.25 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:36:31 PM PDT 24
Peak memory 241856 kb
Host smart-6f7b3e96-58f1-4927-b9ba-9e1eb6afcec3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147142053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.147142053 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.1463981587
Short name T117
Test name
Test status
Simulation time 456814072 ps
CPU time 30.89 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:23:45 PM PDT 24
Peak memory 223696 kb
Host smart-d3046c8a-64e5-47a3-8332-6d7b032f30b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1463981587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1463981587 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.4173343666
Short name T452
Test name
Test status
Simulation time 1029078814 ps
CPU time 21.4 seconds
Started Aug 08 06:23:16 PM PDT 24
Finished Aug 08 06:23:37 PM PDT 24
Peak memory 223824 kb
Host smart-38d93d3d-e2af-4ebe-a2d7-6ba7c6adeca8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4173343666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.4173343666 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.599113259
Short name T547
Test name
Test status
Simulation time 14284066242 ps
CPU time 63.12 seconds
Started Aug 08 06:23:19 PM PDT 24
Finished Aug 08 06:24:22 PM PDT 24
Peak memory 219148 kb
Host smart-b7a3d39c-7f9f-48bb-92dd-7b0dce1e0f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599113259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.599113259 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.4291515385
Short name T575
Test name
Test status
Simulation time 7744763310 ps
CPU time 172.32 seconds
Started Aug 08 06:23:25 PM PDT 24
Finished Aug 08 06:26:17 PM PDT 24
Peak memory 357772 kb
Host smart-1aa4e3b5-db98-43ff-808d-985c575a0807
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291515385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.42
91515385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.693343176
Short name T638
Test name
Test status
Simulation time 802740078 ps
CPU time 14.72 seconds
Started Aug 08 06:23:13 PM PDT 24
Finished Aug 08 06:23:27 PM PDT 24
Peak memory 237684 kb
Host smart-9c32b2cd-6c00-47b4-b095-9efcc4f62818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693343176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.693343176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.769152560
Short name T955
Test name
Test status
Simulation time 5771011413 ps
CPU time 8.6 seconds
Started Aug 08 06:23:15 PM PDT 24
Finished Aug 08 06:23:24 PM PDT 24
Peak memory 218348 kb
Host smart-84c61962-ce3f-42cf-9ed2-93835d8b0650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769152560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.769152560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.1971379155
Short name T753
Test name
Test status
Simulation time 53865978379 ps
CPU time 1219.22 seconds
Started Aug 08 06:23:23 PM PDT 24
Finished Aug 08 06:43:43 PM PDT 24
Peak memory 1587100 kb
Host smart-a781d8fa-c191-4bf1-9634-66db95822778
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971379155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.1971379155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.54836419
Short name T440
Test name
Test status
Simulation time 4010208094 ps
CPU time 243.6 seconds
Started Aug 08 06:23:10 PM PDT 24
Finished Aug 08 06:27:13 PM PDT 24
Peak memory 323908 kb
Host smart-bd729be6-a4e1-4dfd-95ee-28a2330bd67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54836419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.54836419 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.1029509533
Short name T71
Test name
Test status
Simulation time 4374084024 ps
CPU time 55.75 seconds
Started Aug 08 06:23:10 PM PDT 24
Finished Aug 08 06:24:06 PM PDT 24
Peak memory 267208 kb
Host smart-74a33877-7d0b-4d0e-9cc6-d5b122e6c17f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029509533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1029509533 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.2396450376
Short name T472
Test name
Test status
Simulation time 958440646 ps
CPU time 14.52 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:23:36 PM PDT 24
Peak memory 227508 kb
Host smart-a815a97b-0d03-47f9-8f92-cb234be83560
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396450376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2396450376 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.3646964358
Short name T625
Test name
Test status
Simulation time 215846954 ps
CPU time 1.13 seconds
Started Aug 08 06:23:20 PM PDT 24
Finished Aug 08 06:23:21 PM PDT 24
Peak memory 217820 kb
Host smart-1639984f-a138-4c92-b38e-c4d39f118a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646964358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3646964358 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.555002576
Short name T341
Test name
Test status
Simulation time 6078423989 ps
CPU time 621.62 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 06:33:45 PM PDT 24
Peak memory 459244 kb
Host smart-286436da-5c9c-4ae1-8cbf-09c079db4fba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=555002576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.555002576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.4279054824
Short name T241
Test name
Test status
Simulation time 586427488 ps
CPU time 4.18 seconds
Started Aug 08 06:23:46 PM PDT 24
Finished Aug 08 06:23:50 PM PDT 24
Peak memory 218200 kb
Host smart-ce14edaa-608d-4223-99ef-f6d448f8f8a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279054824 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.4279054824 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.4052894739
Short name T351
Test name
Test status
Simulation time 982610485 ps
CPU time 5.48 seconds
Started Aug 08 06:23:26 PM PDT 24
Finished Aug 08 06:23:32 PM PDT 24
Peak memory 218068 kb
Host smart-8941114c-24d1-4396-9760-17d972e577a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052894739 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.4052894739 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.2129432342
Short name T451
Test name
Test status
Simulation time 19311295622 ps
CPU time 1873.76 seconds
Started Aug 08 06:23:17 PM PDT 24
Finished Aug 08 06:54:31 PM PDT 24
Peak memory 1163192 kb
Host smart-46093132-1bae-41b8-bee1-8da478469b8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2129432342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2129432342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1788325239
Short name T948
Test name
Test status
Simulation time 65434071081 ps
CPU time 2744.82 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 07:09:07 PM PDT 24
Peak memory 3135996 kb
Host smart-0da8f441-749e-4c71-8071-a36a69dd7be5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1788325239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1788325239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.817107570
Short name T1025
Test name
Test status
Simulation time 13645365636 ps
CPU time 1328.44 seconds
Started Aug 08 06:23:19 PM PDT 24
Finished Aug 08 06:45:27 PM PDT 24
Peak memory 919424 kb
Host smart-384a16c2-4723-4863-9155-f479a1186a6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=817107570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.817107570 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.897883705
Short name T759
Test name
Test status
Simulation time 155586657324 ps
CPU time 1272 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:44:45 PM PDT 24
Peak memory 1723508 kb
Host smart-310b2917-cad6-4fc2-bbdd-b9234b0d71e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=897883705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.897883705 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.3901172933
Short name T967
Test name
Test status
Simulation time 88130262170 ps
CPU time 4407.97 seconds
Started Aug 08 06:23:23 PM PDT 24
Finished Aug 08 07:36:52 PM PDT 24
Peak memory 2212976 kb
Host smart-f5c11758-3adf-441b-bb7b-a2a1cafab3d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3901172933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3901172933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.2303207
Short name T136
Test name
Test status
Simulation time 15331755 ps
CPU time 0.76 seconds
Started Aug 08 06:25:59 PM PDT 24
Finished Aug 08 06:26:00 PM PDT 24
Peak memory 205212 kb
Host smart-314adf7d-5980-4650-967c-a0645547b8d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2303207 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.289034732
Short name T802
Test name
Test status
Simulation time 14099398004 ps
CPU time 155.48 seconds
Started Aug 08 06:25:53 PM PDT 24
Finished Aug 08 06:28:29 PM PDT 24
Peak memory 360992 kb
Host smart-94b52086-2322-4d7a-a6cd-c006c39c6d72
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289034732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.289034732 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.82361167
Short name T148
Test name
Test status
Simulation time 4666777263 ps
CPU time 424.76 seconds
Started Aug 08 06:25:53 PM PDT 24
Finished Aug 08 06:32:58 PM PDT 24
Peak memory 235108 kb
Host smart-887b1361-989a-4f52-bf2a-7307b5518d8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82361167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.82361167 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.3818480409
Short name T488
Test name
Test status
Simulation time 16488508639 ps
CPU time 371.17 seconds
Started Aug 08 06:25:51 PM PDT 24
Finished Aug 08 06:32:02 PM PDT 24
Peak memory 523076 kb
Host smart-49a0b39f-1167-43d3-94d6-b7e085900334
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818480409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3
818480409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1360728777
Short name T304
Test name
Test status
Simulation time 12089019447 ps
CPU time 242.55 seconds
Started Aug 08 06:25:50 PM PDT 24
Finished Aug 08 06:29:53 PM PDT 24
Peak memory 325768 kb
Host smart-38071fec-7e20-4c1a-a866-a3a35fcc085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360728777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1360728777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.3010407741
Short name T65
Test name
Test status
Simulation time 11046333618 ps
CPU time 11.25 seconds
Started Aug 08 06:25:50 PM PDT 24
Finished Aug 08 06:26:01 PM PDT 24
Peak memory 219500 kb
Host smart-e8a074ba-887b-402e-b82e-6c7ab97041a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010407741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3010407741 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.1380747144
Short name T946
Test name
Test status
Simulation time 179813530 ps
CPU time 1.4 seconds
Started Aug 08 06:25:52 PM PDT 24
Finished Aug 08 06:25:54 PM PDT 24
Peak memory 219668 kb
Host smart-e1a923fd-91e0-4bca-bd25-0c3f3ba03a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380747144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1380747144 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.766219483
Short name T613
Test name
Test status
Simulation time 222253060364 ps
CPU time 1759.04 seconds
Started Aug 08 06:25:50 PM PDT 24
Finished Aug 08 06:55:09 PM PDT 24
Peak memory 1987972 kb
Host smart-b881220a-0bbb-4900-a74e-9389aa2225ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766219483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.766219483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.2478371010
Short name T1014
Test name
Test status
Simulation time 3896861752 ps
CPU time 74.23 seconds
Started Aug 08 06:25:49 PM PDT 24
Finished Aug 08 06:27:03 PM PDT 24
Peak memory 249196 kb
Host smart-2eb0e10b-7568-459d-a1e3-aca4719c76e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478371010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2478371010 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.61385685
Short name T339
Test name
Test status
Simulation time 16813087 ps
CPU time 1.07 seconds
Started Aug 08 06:25:50 PM PDT 24
Finished Aug 08 06:25:52 PM PDT 24
Peak memory 217856 kb
Host smart-cc5faa53-838f-466a-8301-ec71bf7a59be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61385685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.61385685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.1414068789
Short name T711
Test name
Test status
Simulation time 34983513808 ps
CPU time 1199.7 seconds
Started Aug 08 06:26:00 PM PDT 24
Finished Aug 08 06:45:59 PM PDT 24
Peak memory 1145204 kb
Host smart-d652cafe-1372-4e54-bbb6-3d264365ea32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1414068789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1414068789 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.2549325722
Short name T236
Test name
Test status
Simulation time 245875196 ps
CPU time 3.93 seconds
Started Aug 08 06:25:53 PM PDT 24
Finished Aug 08 06:25:57 PM PDT 24
Peak memory 217700 kb
Host smart-28dd88b2-ca48-4a86-80d4-04122d5fa6ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549325722 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.2549325722 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.2525909388
Short name T769
Test name
Test status
Simulation time 238994612 ps
CPU time 4.24 seconds
Started Aug 08 06:25:51 PM PDT 24
Finished Aug 08 06:25:55 PM PDT 24
Peak memory 217752 kb
Host smart-6e08e14d-bc04-4768-a199-d300f96940f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525909388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.2525909388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.2391356591
Short name T846
Test name
Test status
Simulation time 97631223955 ps
CPU time 3654.27 seconds
Started Aug 08 06:25:52 PM PDT 24
Finished Aug 08 07:26:47 PM PDT 24
Peak memory 3246704 kb
Host smart-ae9d2305-0f9e-470b-a573-3554f9c8fe25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2391356591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.2391356591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.2891650081
Short name T725
Test name
Test status
Simulation time 62406342539 ps
CPU time 2805.86 seconds
Started Aug 08 06:25:50 PM PDT 24
Finished Aug 08 07:12:36 PM PDT 24
Peak memory 3117040 kb
Host smart-c818d028-9c87-42cd-a857-4364e43882bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2891650081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2891650081 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.923319259
Short name T917
Test name
Test status
Simulation time 54833298778 ps
CPU time 1382.82 seconds
Started Aug 08 06:25:52 PM PDT 24
Finished Aug 08 06:48:56 PM PDT 24
Peak memory 924748 kb
Host smart-c3909271-33b2-406e-9429-089a6a37907f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=923319259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.923319259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.842006820
Short name T801
Test name
Test status
Simulation time 33064509344 ps
CPU time 1291.09 seconds
Started Aug 08 06:25:50 PM PDT 24
Finished Aug 08 06:47:21 PM PDT 24
Peak memory 1742720 kb
Host smart-b1069be0-0088-4650-a0d8-32d85ade7280
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=842006820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.842006820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.251301589
Short name T911
Test name
Test status
Simulation time 52870628167 ps
CPU time 5464.53 seconds
Started Aug 08 06:25:50 PM PDT 24
Finished Aug 08 07:56:55 PM PDT 24
Peak memory 2683636 kb
Host smart-096bd03b-ce68-4760-8147-9515e192e354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=251301589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.251301589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.3880724189
Short name T893
Test name
Test status
Simulation time 604081169554 ps
CPU time 8659.17 seconds
Started Aug 08 06:25:50 PM PDT 24
Finished Aug 08 08:50:11 PM PDT 24
Peak memory 6377912 kb
Host smart-f3041d77-3150-44fd-ab79-f3fe264a51bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3880724189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3880724189 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.1414162357
Short name T347
Test name
Test status
Simulation time 38071297 ps
CPU time 0.86 seconds
Started Aug 08 06:26:09 PM PDT 24
Finished Aug 08 06:26:10 PM PDT 24
Peak memory 205196 kb
Host smart-33684933-e2e7-42a6-91d9-5318d81236f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414162357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1414162357 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.3800334131
Short name T364
Test name
Test status
Simulation time 1785343484 ps
CPU time 19.69 seconds
Started Aug 08 06:26:08 PM PDT 24
Finished Aug 08 06:26:28 PM PDT 24
Peak memory 223400 kb
Host smart-ec1a47ce-b2d0-4523-a602-d79d95b50eaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800334131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3800334131 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.3850288316
Short name T652
Test name
Test status
Simulation time 1455006049 ps
CPU time 57.72 seconds
Started Aug 08 06:26:00 PM PDT 24
Finished Aug 08 06:26:58 PM PDT 24
Peak memory 219784 kb
Host smart-38426a31-5707-444f-a74d-d20f3df682eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850288316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.385028831
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.1199384478
Short name T78
Test name
Test status
Simulation time 9325544210 ps
CPU time 46.06 seconds
Started Aug 08 06:26:11 PM PDT 24
Finished Aug 08 06:26:58 PM PDT 24
Peak memory 247260 kb
Host smart-52455534-b419-448e-a942-f4db67e47b8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199384478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1
199384478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.1046049976
Short name T673
Test name
Test status
Simulation time 1999673634 ps
CPU time 79.66 seconds
Started Aug 08 06:26:09 PM PDT 24
Finished Aug 08 06:27:29 PM PDT 24
Peak memory 256728 kb
Host smart-7aedf1ae-fe2b-4be3-bd9b-d1d0df8aeaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046049976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1046049976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.1390729090
Short name T350
Test name
Test status
Simulation time 958242233 ps
CPU time 3.43 seconds
Started Aug 08 06:26:08 PM PDT 24
Finished Aug 08 06:26:11 PM PDT 24
Peak memory 217900 kb
Host smart-373b15d5-99e1-4b44-a9d3-2b5ab3d14f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390729090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1390729090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.3431153638
Short name T953
Test name
Test status
Simulation time 144946577 ps
CPU time 1.43 seconds
Started Aug 08 06:26:09 PM PDT 24
Finished Aug 08 06:26:10 PM PDT 24
Peak memory 223516 kb
Host smart-6bcf6f1a-cc6c-41da-b14d-f1df0c0a3de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431153638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3431153638 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.1932575846
Short name T732
Test name
Test status
Simulation time 47037394939 ps
CPU time 1765.37 seconds
Started Aug 08 06:26:00 PM PDT 24
Finished Aug 08 06:55:26 PM PDT 24
Peak memory 2055736 kb
Host smart-fa75264a-f0d1-46a1-815c-b44813d20f7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932575846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.1932575846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.3830031372
Short name T716
Test name
Test status
Simulation time 5084804521 ps
CPU time 151.6 seconds
Started Aug 08 06:26:00 PM PDT 24
Finished Aug 08 06:28:31 PM PDT 24
Peak memory 354412 kb
Host smart-8c4cfc8b-fedc-4d38-b94b-ab7536b89efa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830031372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3830031372 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.3937154531
Short name T316
Test name
Test status
Simulation time 1048650365 ps
CPU time 27.58 seconds
Started Aug 08 06:26:00 PM PDT 24
Finished Aug 08 06:26:27 PM PDT 24
Peak memory 218156 kb
Host smart-65591759-5399-4256-952c-2918e4d5339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937154531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3937154531 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.3096324530
Short name T90
Test name
Test status
Simulation time 179924740 ps
CPU time 5.25 seconds
Started Aug 08 06:26:08 PM PDT 24
Finished Aug 08 06:26:14 PM PDT 24
Peak memory 224232 kb
Host smart-a1704678-e015-45b8-a12f-a400b1b7f6e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3096324530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3096324530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.61922284
Short name T217
Test name
Test status
Simulation time 254116756 ps
CPU time 4.76 seconds
Started Aug 08 06:26:09 PM PDT 24
Finished Aug 08 06:26:14 PM PDT 24
Peak memory 218036 kb
Host smart-b6904c40-eeea-4c18-b868-0f079a1a03e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61922284 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.kmac_test_vectors_kmac.61922284 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.4189642102
Short name T885
Test name
Test status
Simulation time 239876352 ps
CPU time 3.85 seconds
Started Aug 08 06:26:08 PM PDT 24
Finished Aug 08 06:26:12 PM PDT 24
Peak memory 217968 kb
Host smart-840c5558-aae0-44f3-ad76-1eb4e382e660
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189642102 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.4189642102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2778700647
Short name T544
Test name
Test status
Simulation time 66225998545 ps
CPU time 2878.11 seconds
Started Aug 08 06:26:00 PM PDT 24
Finished Aug 08 07:13:59 PM PDT 24
Peak memory 3228940 kb
Host smart-580bc74b-88ec-4d47-8e79-2fd00a17d18c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2778700647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2778700647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.3034994474
Short name T751
Test name
Test status
Simulation time 73096047336 ps
CPU time 1746.51 seconds
Started Aug 08 06:26:09 PM PDT 24
Finished Aug 08 06:55:15 PM PDT 24
Peak memory 1123420 kb
Host smart-5f45dcb1-9d2e-4784-a6f6-2b868b4aef81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3034994474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3034994474 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.4034075484
Short name T13
Test name
Test status
Simulation time 48321211031 ps
CPU time 1863.91 seconds
Started Aug 08 06:26:11 PM PDT 24
Finished Aug 08 06:57:15 PM PDT 24
Peak memory 2362360 kb
Host smart-8813aaee-dc17-4e88-b771-8e79012f87a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4034075484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.4034075484 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.2647724990
Short name T747
Test name
Test status
Simulation time 32799695706 ps
CPU time 1279.35 seconds
Started Aug 08 06:26:08 PM PDT 24
Finished Aug 08 06:47:28 PM PDT 24
Peak memory 1732024 kb
Host smart-8a2c6193-a0aa-494c-9402-b01477a5ce25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2647724990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.2647724990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.286500706
Short name T319
Test name
Test status
Simulation time 52671284123 ps
CPU time 5314.54 seconds
Started Aug 08 06:26:08 PM PDT 24
Finished Aug 08 07:54:43 PM PDT 24
Peak memory 2673988 kb
Host smart-8343e49b-5379-4b0d-84a5-430e046d8782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=286500706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.286500706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.4163441019
Short name T915
Test name
Test status
Simulation time 172123200617 ps
CPU time 4543.87 seconds
Started Aug 08 06:26:11 PM PDT 24
Finished Aug 08 07:41:56 PM PDT 24
Peak memory 2202988 kb
Host smart-39a2cb00-af65-4ef2-82d8-9d5e46bb9534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4163441019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.4163441019 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.1141704822
Short name T258
Test name
Test status
Simulation time 17937771 ps
CPU time 0.85 seconds
Started Aug 08 06:26:26 PM PDT 24
Finished Aug 08 06:26:27 PM PDT 24
Peak memory 205208 kb
Host smart-67f886d2-071d-4d01-a212-0719e0ca31e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141704822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1141704822 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.3207386211
Short name T31
Test name
Test status
Simulation time 810566695 ps
CPU time 3.17 seconds
Started Aug 08 06:26:17 PM PDT 24
Finished Aug 08 06:26:20 PM PDT 24
Peak memory 219728 kb
Host smart-219648a2-6e0c-49d9-8965-a3f6b8b5d254
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207386211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3207386211 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.64113159
Short name T729
Test name
Test status
Simulation time 16150472697 ps
CPU time 526.77 seconds
Started Aug 08 06:26:17 PM PDT 24
Finished Aug 08 06:35:04 PM PDT 24
Peak memory 244224 kb
Host smart-ac861adb-1200-4642-9f53-82e648386d70
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64113159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.64113159 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.1228793671
Short name T288
Test name
Test status
Simulation time 39625593296 ps
CPU time 138.61 seconds
Started Aug 08 06:26:15 PM PDT 24
Finished Aug 08 06:28:34 PM PDT 24
Peak memory 343864 kb
Host smart-a957313b-5c94-428c-95c4-414debcc523c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228793671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1
228793671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.3592661615
Short name T566
Test name
Test status
Simulation time 2043863329 ps
CPU time 141.45 seconds
Started Aug 08 06:26:15 PM PDT 24
Finished Aug 08 06:28:37 PM PDT 24
Peak memory 288564 kb
Host smart-d4dbef88-c612-4a2f-919e-911f93aaba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592661615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3592661615 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.1336396419
Short name T588
Test name
Test status
Simulation time 4951033950 ps
CPU time 10.41 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 06:26:27 PM PDT 24
Peak memory 219236 kb
Host smart-a37f9503-cea1-4b9a-a3a6-fa4b9b218fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336396419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1336396419 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.3181587005
Short name T590
Test name
Test status
Simulation time 833064384 ps
CPU time 11.95 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 06:26:28 PM PDT 24
Peak memory 240304 kb
Host smart-c48f5a66-03e9-40e1-9959-fdaafb9d1245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181587005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3181587005 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.1112209959
Short name T633
Test name
Test status
Simulation time 1193257619 ps
CPU time 112.29 seconds
Started Aug 08 06:26:08 PM PDT 24
Finished Aug 08 06:28:01 PM PDT 24
Peak memory 284660 kb
Host smart-09e4f73a-c5c6-4d0f-ba8e-318a08367f13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112209959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.1112209959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.3634441282
Short name T511
Test name
Test status
Simulation time 202689232 ps
CPU time 4.51 seconds
Started Aug 08 06:26:09 PM PDT 24
Finished Aug 08 06:26:14 PM PDT 24
Peak memory 219244 kb
Host smart-c18be95b-70c9-45cd-9c67-09992098be5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634441282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3634441282 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.2472043107
Short name T564
Test name
Test status
Simulation time 835496558 ps
CPU time 43.28 seconds
Started Aug 08 06:26:09 PM PDT 24
Finished Aug 08 06:26:52 PM PDT 24
Peak memory 218300 kb
Host smart-6f4f2e40-f3b4-4709-9637-76b1a85152af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472043107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2472043107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.2651099252
Short name T555
Test name
Test status
Simulation time 31509881633 ps
CPU time 1466.66 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 06:50:43 PM PDT 24
Peak memory 710012 kb
Host smart-b9bfd076-4d12-4641-94a9-9496d0640535
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2651099252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2651099252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.1957442894
Short name T767
Test name
Test status
Simulation time 91389723 ps
CPU time 4.36 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 06:26:21 PM PDT 24
Peak memory 218024 kb
Host smart-21b53381-9dd6-4403-96d0-50d432628846
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957442894 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.1957442894 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2176988960
Short name T689
Test name
Test status
Simulation time 348993391 ps
CPU time 3.87 seconds
Started Aug 08 06:26:17 PM PDT 24
Finished Aug 08 06:26:21 PM PDT 24
Peak memory 218172 kb
Host smart-70ff13bf-eb97-4a2b-972c-c3f64ad86243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176988960 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2176988960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.2526406071
Short name T515
Test name
Test status
Simulation time 73223066797 ps
CPU time 2875.44 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 07:14:12 PM PDT 24
Peak memory 3206124 kb
Host smart-2260d0f4-50b8-4fc5-a61e-bdd35dd46f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2526406071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2526406071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.1360935976
Short name T952
Test name
Test status
Simulation time 18095907146 ps
CPU time 1814.87 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 06:56:31 PM PDT 24
Peak memory 1147316 kb
Host smart-e6c072b7-864e-4a04-be97-0dcf7f6cb3b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1360935976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.1360935976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.2718573339
Short name T805
Test name
Test status
Simulation time 188868738444 ps
CPU time 2073.18 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 07:00:49 PM PDT 24
Peak memory 2405304 kb
Host smart-263b4c01-82b0-418e-a1ee-f2f51ff5ad3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2718573339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2718573339 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.2068335521
Short name T994
Test name
Test status
Simulation time 134329207556 ps
CPU time 1254.98 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 06:47:11 PM PDT 24
Peak memory 1701868 kb
Host smart-f0f8052b-b257-4871-a7ed-ef195f36c593
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2068335521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.2068335521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.851432234
Short name T841
Test name
Test status
Simulation time 93227632034 ps
CPU time 4185.19 seconds
Started Aug 08 06:26:16 PM PDT 24
Finished Aug 08 07:36:01 PM PDT 24
Peak memory 2191744 kb
Host smart-d2c6d93e-32bf-4a82-ad5b-b8d7da9b3ea4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=851432234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.851432234 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.3151668295
Short name T80
Test name
Test status
Simulation time 36400716 ps
CPU time 0.75 seconds
Started Aug 08 06:26:40 PM PDT 24
Finished Aug 08 06:26:41 PM PDT 24
Peak memory 205224 kb
Host smart-d95f6855-8fee-462e-b350-7ff041bc74ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151668295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3151668295 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.3230163319
Short name T597
Test name
Test status
Simulation time 17419785183 ps
CPU time 346.73 seconds
Started Aug 08 06:26:33 PM PDT 24
Finished Aug 08 06:32:19 PM PDT 24
Peak memory 516108 kb
Host smart-6eb0316c-47f0-45f0-8f05-211e22d44315
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230163319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3230163319 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.1506359276
Short name T187
Test name
Test status
Simulation time 7826084080 ps
CPU time 740.04 seconds
Started Aug 08 06:26:23 PM PDT 24
Finished Aug 08 06:38:43 PM PDT 24
Peak memory 239908 kb
Host smart-ccf4d554-32ce-40ba-a548-db9a7a6975e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506359276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.150635927
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.1510781508
Short name T905
Test name
Test status
Simulation time 3731272051 ps
CPU time 54.95 seconds
Started Aug 08 06:26:31 PM PDT 24
Finished Aug 08 06:27:26 PM PDT 24
Peak memory 265516 kb
Host smart-8e13ba26-9e0c-48fa-b8ba-1a674c8fc3c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510781508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1
510781508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.1482507430
Short name T889
Test name
Test status
Simulation time 26657975995 ps
CPU time 306.97 seconds
Started Aug 08 06:26:31 PM PDT 24
Finished Aug 08 06:31:38 PM PDT 24
Peak memory 502264 kb
Host smart-a24e11ff-590e-4c12-aee7-4a56f90ad47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482507430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1482507430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.1795532579
Short name T1021
Test name
Test status
Simulation time 2599309745 ps
CPU time 4.35 seconds
Started Aug 08 06:26:32 PM PDT 24
Finished Aug 08 06:26:36 PM PDT 24
Peak memory 218060 kb
Host smart-4726c00a-0944-4fd8-8856-82dd406487f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795532579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1795532579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.2253866632
Short name T38
Test name
Test status
Simulation time 138605503 ps
CPU time 1.29 seconds
Started Aug 08 06:26:40 PM PDT 24
Finished Aug 08 06:26:42 PM PDT 24
Peak memory 219304 kb
Host smart-e59e62be-5c90-4b46-8fce-239964c2cd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253866632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2253866632 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.1873245261
Short name T272
Test name
Test status
Simulation time 824265495531 ps
CPU time 4531.91 seconds
Started Aug 08 06:26:25 PM PDT 24
Finished Aug 08 07:41:58 PM PDT 24
Peak memory 3583596 kb
Host smart-d64a1468-8490-4518-bedb-8f3c62abe9ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873245261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.1873245261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.932909062
Short name T365
Test name
Test status
Simulation time 19862220358 ps
CPU time 257.56 seconds
Started Aug 08 06:26:22 PM PDT 24
Finished Aug 08 06:30:40 PM PDT 24
Peak memory 450400 kb
Host smart-522d2d47-f72f-4625-9abb-fb6f3427a2cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932909062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.932909062 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1621115823
Short name T218
Test name
Test status
Simulation time 245104805 ps
CPU time 12.23 seconds
Started Aug 08 06:26:23 PM PDT 24
Finished Aug 08 06:26:35 PM PDT 24
Peak memory 219524 kb
Host smart-a1dcbaee-9e8f-4fb6-b3ba-5382e87a121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621115823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1621115823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.2766689617
Short name T489
Test name
Test status
Simulation time 17931877525 ps
CPU time 86.67 seconds
Started Aug 08 06:26:40 PM PDT 24
Finished Aug 08 06:28:07 PM PDT 24
Peak memory 288968 kb
Host smart-0362e27a-532b-4e8c-a875-6776288bd4ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2766689617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2766689617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.1503156403
Short name T237
Test name
Test status
Simulation time 333096255 ps
CPU time 4.68 seconds
Started Aug 08 06:26:31 PM PDT 24
Finished Aug 08 06:26:36 PM PDT 24
Peak memory 218036 kb
Host smart-1565bc3d-8487-4095-9ea8-920c606847bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503156403 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.1503156403 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.2778742518
Short name T225
Test name
Test status
Simulation time 123710960 ps
CPU time 3.77 seconds
Started Aug 08 06:26:32 PM PDT 24
Finished Aug 08 06:26:36 PM PDT 24
Peak memory 217680 kb
Host smart-db698105-b560-4ac3-82d7-8e4923558bf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778742518 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.2778742518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.3149701553
Short name T269
Test name
Test status
Simulation time 206833561035 ps
CPU time 3073.45 seconds
Started Aug 08 06:26:25 PM PDT 24
Finished Aug 08 07:17:39 PM PDT 24
Peak memory 3168972 kb
Host smart-7a01da10-ead1-44ab-a74d-3ecedb7c471f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3149701553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3149701553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.145259872
Short name T721
Test name
Test status
Simulation time 40236361585 ps
CPU time 1764.36 seconds
Started Aug 08 06:26:25 PM PDT 24
Finished Aug 08 06:55:50 PM PDT 24
Peak memory 1107972 kb
Host smart-978c5449-192a-432c-81b2-024cae018367
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=145259872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.145259872 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.2612558852
Short name T543
Test name
Test status
Simulation time 27125776327 ps
CPU time 1292.64 seconds
Started Aug 08 06:26:23 PM PDT 24
Finished Aug 08 06:47:56 PM PDT 24
Peak memory 916096 kb
Host smart-207219ee-89ab-4946-acc1-5700e5f5696f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2612558852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2612558852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.4274182525
Short name T853
Test name
Test status
Simulation time 33280351269 ps
CPU time 1269.91 seconds
Started Aug 08 06:26:24 PM PDT 24
Finished Aug 08 06:47:34 PM PDT 24
Peak memory 1685468 kb
Host smart-5e1e12d0-c278-46bb-a941-8f0f87239563
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4274182525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.4274182525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.3288609009
Short name T584
Test name
Test status
Simulation time 465972958317 ps
CPU time 10470.2 seconds
Started Aug 08 06:26:23 PM PDT 24
Finished Aug 08 09:20:54 PM PDT 24
Peak memory 6481436 kb
Host smart-01e02671-fa1b-45d9-b486-c1cdac6e7ca2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3288609009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3288609009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.1896533534
Short name T581
Test name
Test status
Simulation time 14682205 ps
CPU time 0.76 seconds
Started Aug 08 06:26:55 PM PDT 24
Finished Aug 08 06:26:56 PM PDT 24
Peak memory 205128 kb
Host smart-c7b10b0a-60fe-4995-bb71-60b37b58dafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896533534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1896533534 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.4108047891
Short name T985
Test name
Test status
Simulation time 9938901029 ps
CPU time 127.33 seconds
Started Aug 08 06:26:46 PM PDT 24
Finished Aug 08 06:28:53 PM PDT 24
Peak memory 272008 kb
Host smart-e8a4a44f-494a-4bff-bb66-6498a9dbe433
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108047891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.4108047891 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.3397322541
Short name T614
Test name
Test status
Simulation time 90774600041 ps
CPU time 1217.98 seconds
Started Aug 08 06:26:38 PM PDT 24
Finished Aug 08 06:46:56 PM PDT 24
Peak memory 262020 kb
Host smart-8610fa73-09f7-48b5-bd04-72d8db12a199
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397322541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.339732254
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.1101741665
Short name T727
Test name
Test status
Simulation time 2164063312 ps
CPU time 21.75 seconds
Started Aug 08 06:26:46 PM PDT 24
Finished Aug 08 06:27:08 PM PDT 24
Peak memory 227184 kb
Host smart-93d38bd9-6ce5-47c8-86ac-39a38c711b82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101741665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1
101741665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.987878405
Short name T863
Test name
Test status
Simulation time 23226160352 ps
CPU time 148.99 seconds
Started Aug 08 06:26:46 PM PDT 24
Finished Aug 08 06:29:15 PM PDT 24
Peak memory 284000 kb
Host smart-72c0dca4-a5c7-46d2-8e00-0f0141f473c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987878405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.987878405 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.316512230
Short name T850
Test name
Test status
Simulation time 930939712 ps
CPU time 2.09 seconds
Started Aug 08 06:26:46 PM PDT 24
Finished Aug 08 06:26:48 PM PDT 24
Peak memory 217680 kb
Host smart-80bcef74-a031-48b1-9c2d-e60da70652fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316512230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.316512230 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.2658374720
Short name T840
Test name
Test status
Simulation time 127176073 ps
CPU time 1.36 seconds
Started Aug 08 06:26:54 PM PDT 24
Finished Aug 08 06:26:55 PM PDT 24
Peak memory 223432 kb
Host smart-bec6d5d7-e0e1-4239-98fb-90a1d38e4292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658374720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2658374720 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.3881570496
Short name T284
Test name
Test status
Simulation time 332845487371 ps
CPU time 5356.2 seconds
Started Aug 08 06:26:39 PM PDT 24
Finished Aug 08 07:55:56 PM PDT 24
Peak memory 4084296 kb
Host smart-3fc2db5b-a810-471a-926b-7ffede3db176
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881570496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.3881570496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.2196669925
Short name T835
Test name
Test status
Simulation time 2686523667 ps
CPU time 48.35 seconds
Started Aug 08 06:26:43 PM PDT 24
Finished Aug 08 06:27:32 PM PDT 24
Peak memory 241176 kb
Host smart-8b15d20d-efb6-4cfa-80f8-15c4d7ae6d15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196669925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2196669925 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.2767804321
Short name T553
Test name
Test status
Simulation time 2712145748 ps
CPU time 16.37 seconds
Started Aug 08 06:26:40 PM PDT 24
Finished Aug 08 06:26:57 PM PDT 24
Peak memory 220976 kb
Host smart-dbdebbc7-02f5-4ed4-a5f7-4a5fff1a9e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767804321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2767804321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.505639041
Short name T49
Test name
Test status
Simulation time 11382530351 ps
CPU time 691.49 seconds
Started Aug 08 06:26:55 PM PDT 24
Finished Aug 08 06:38:27 PM PDT 24
Peak memory 314460 kb
Host smart-0c420595-fbee-486d-b2d6-e611a34bd814
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=505639041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.505639041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.1885928975
Short name T518
Test name
Test status
Simulation time 131180527 ps
CPU time 4.2 seconds
Started Aug 08 06:26:46 PM PDT 24
Finished Aug 08 06:26:50 PM PDT 24
Peak memory 218004 kb
Host smart-d1a12171-9c3a-48c6-9426-c91a19cc6b6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885928975 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.1885928975 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.2722513151
Short name T790
Test name
Test status
Simulation time 72906070 ps
CPU time 4.65 seconds
Started Aug 08 06:26:47 PM PDT 24
Finished Aug 08 06:26:52 PM PDT 24
Peak memory 217676 kb
Host smart-3a7ae81e-d242-45bc-b0aa-026b159b4ccd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722513151 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.2722513151 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.4078163538
Short name T323
Test name
Test status
Simulation time 254915613498 ps
CPU time 2837.15 seconds
Started Aug 08 06:26:39 PM PDT 24
Finished Aug 08 07:13:56 PM PDT 24
Peak memory 3166352 kb
Host smart-4759b48c-5881-4c2f-89bf-9c10f94cb43a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4078163538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.4078163538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.224259979
Short name T487
Test name
Test status
Simulation time 69772057007 ps
CPU time 1627.12 seconds
Started Aug 08 06:26:39 PM PDT 24
Finished Aug 08 06:53:46 PM PDT 24
Peak memory 1116636 kb
Host smart-ec240b91-5511-457e-b843-bb510d2d4f1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=224259979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.224259979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.2879532110
Short name T864
Test name
Test status
Simulation time 149148489350 ps
CPU time 2314.49 seconds
Started Aug 08 06:26:46 PM PDT 24
Finished Aug 08 07:05:21 PM PDT 24
Peak memory 2431764 kb
Host smart-a9b4c0eb-7a7d-4db4-a115-13c059775dfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2879532110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.2879532110 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.1071149869
Short name T827
Test name
Test status
Simulation time 9422088086 ps
CPU time 883.2 seconds
Started Aug 08 06:26:46 PM PDT 24
Finished Aug 08 06:41:29 PM PDT 24
Peak memory 694440 kb
Host smart-e32be694-f597-4c96-be45-814ce5b359a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1071149869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1071149869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.60274949
Short name T417
Test name
Test status
Simulation time 174850950838 ps
CPU time 4654.91 seconds
Started Aug 08 06:26:46 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 2248292 kb
Host smart-e5312985-c544-4f0d-96c3-1530f9496754
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=60274949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.60274949 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.3192917201
Short name T285
Test name
Test status
Simulation time 19004612 ps
CPU time 0.82 seconds
Started Aug 08 06:27:04 PM PDT 24
Finished Aug 08 06:27:05 PM PDT 24
Peak memory 205180 kb
Host smart-b14bed50-3f0c-4637-b02e-a6ca26da4052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192917201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3192917201 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.2309905229
Short name T261
Test name
Test status
Simulation time 30331939126 ps
CPU time 143.7 seconds
Started Aug 08 06:27:03 PM PDT 24
Finished Aug 08 06:29:27 PM PDT 24
Peak memory 343800 kb
Host smart-e8204ee3-4acb-4a3f-aea2-fcb0f21d682e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309905229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2309905229 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.2243612697
Short name T185
Test name
Test status
Simulation time 5582952547 ps
CPU time 546.77 seconds
Started Aug 08 06:26:55 PM PDT 24
Finished Aug 08 06:36:02 PM PDT 24
Peak memory 240448 kb
Host smart-f3cac727-0529-4f3e-a03c-d0978809e35a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243612697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.224361269
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1751397306
Short name T325
Test name
Test status
Simulation time 2491545338 ps
CPU time 34.08 seconds
Started Aug 08 06:27:02 PM PDT 24
Finished Aug 08 06:27:36 PM PDT 24
Peak memory 239144 kb
Host smart-d82bc817-5430-45f2-a0a7-d7111b14e83f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751397306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1
751397306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.3890445653
Short name T34
Test name
Test status
Simulation time 16588158207 ps
CPU time 376.75 seconds
Started Aug 08 06:27:05 PM PDT 24
Finished Aug 08 06:33:21 PM PDT 24
Peak memory 572864 kb
Host smart-3a95b30d-511a-483c-bf80-05519c03c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890445653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3890445653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.3100799577
Short name T422
Test name
Test status
Simulation time 1331812200 ps
CPU time 6.85 seconds
Started Aug 08 06:27:02 PM PDT 24
Finished Aug 08 06:27:09 PM PDT 24
Peak memory 217752 kb
Host smart-89c93531-8731-4724-9a31-48abe32aaa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100799577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3100799577 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3071957693
Short name T59
Test name
Test status
Simulation time 10189089520 ps
CPU time 22.92 seconds
Started Aug 08 06:27:02 PM PDT 24
Finished Aug 08 06:27:25 PM PDT 24
Peak memory 240560 kb
Host smart-c6aca707-07ec-4c38-bce8-cbbbd9b045ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071957693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3071957693 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.2862190633
Short name T945
Test name
Test status
Simulation time 8185951830 ps
CPU time 194.69 seconds
Started Aug 08 06:26:55 PM PDT 24
Finished Aug 08 06:30:10 PM PDT 24
Peak memory 335188 kb
Host smart-338b75cb-5635-4f83-a73f-713fd1c51e7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862190633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.2862190633 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.833402378
Short name T602
Test name
Test status
Simulation time 763221983 ps
CPU time 30.07 seconds
Started Aug 08 06:26:54 PM PDT 24
Finished Aug 08 06:27:25 PM PDT 24
Peak memory 232192 kb
Host smart-1613934c-5488-4256-bde2-c9e8038d0144
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833402378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.833402378 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.2336687990
Short name T936
Test name
Test status
Simulation time 4853044301 ps
CPU time 41.94 seconds
Started Aug 08 06:26:54 PM PDT 24
Finished Aug 08 06:27:36 PM PDT 24
Peak memory 219364 kb
Host smart-43a7c1d5-00ea-4d93-8c02-b14452b9187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336687990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2336687990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.185587090
Short name T577
Test name
Test status
Simulation time 29414248316 ps
CPU time 290.03 seconds
Started Aug 08 06:27:01 PM PDT 24
Finished Aug 08 06:31:51 PM PDT 24
Peak memory 290432 kb
Host smart-d945dffb-0d26-49e5-9a5a-ca5f6027bf6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=185587090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.185587090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.4285031770
Short name T266
Test name
Test status
Simulation time 478987473 ps
CPU time 5.28 seconds
Started Aug 08 06:27:12 PM PDT 24
Finished Aug 08 06:27:17 PM PDT 24
Peak memory 218052 kb
Host smart-36f62e21-55e8-4606-8383-97cae497ac07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285031770 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.4285031770 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.1035495179
Short name T1017
Test name
Test status
Simulation time 1034924116 ps
CPU time 4.99 seconds
Started Aug 08 06:27:02 PM PDT 24
Finished Aug 08 06:27:08 PM PDT 24
Peak memory 218068 kb
Host smart-4c8990f9-09b1-415e-bbfe-c26d585effdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035495179 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.1035495179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2184025940
Short name T406
Test name
Test status
Simulation time 129179047332 ps
CPU time 3051.66 seconds
Started Aug 08 06:26:57 PM PDT 24
Finished Aug 08 07:17:49 PM PDT 24
Peak memory 3154016 kb
Host smart-d42d85d0-4c69-44b3-9d1e-67cc2724f763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2184025940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2184025940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.2226619400
Short name T222
Test name
Test status
Simulation time 64345527163 ps
CPU time 1807.27 seconds
Started Aug 08 06:26:55 PM PDT 24
Finished Aug 08 06:57:02 PM PDT 24
Peak memory 1155436 kb
Host smart-563bbc7e-3372-40f6-9224-6144f0dd8592
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2226619400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.2226619400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2167998965
Short name T274
Test name
Test status
Simulation time 299366384994 ps
CPU time 2322.46 seconds
Started Aug 08 06:26:54 PM PDT 24
Finished Aug 08 07:05:37 PM PDT 24
Peak memory 2343112 kb
Host smart-9dd82ed1-1e34-487d-a18e-79db89bc8b8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2167998965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2167998965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.337109167
Short name T983
Test name
Test status
Simulation time 123045847794 ps
CPU time 1249.02 seconds
Started Aug 08 06:26:53 PM PDT 24
Finished Aug 08 06:47:43 PM PDT 24
Peak memory 1689936 kb
Host smart-61e4dae0-f3ae-43f7-9c9c-da9baa0682d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=337109167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.337109167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.60927628
Short name T862
Test name
Test status
Simulation time 170326200020 ps
CPU time 4654.52 seconds
Started Aug 08 06:27:12 PM PDT 24
Finished Aug 08 07:44:47 PM PDT 24
Peak memory 2171272 kb
Host smart-70b025f9-a1da-45af-9481-ab5088671fa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=60927628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.60927628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.3547377842
Short name T396
Test name
Test status
Simulation time 24116601 ps
CPU time 0.77 seconds
Started Aug 08 06:27:17 PM PDT 24
Finished Aug 08 06:27:18 PM PDT 24
Peak memory 205224 kb
Host smart-f34cb51c-c86b-4029-8942-272dd557dbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547377842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3547377842 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.540623700
Short name T925
Test name
Test status
Simulation time 356410699 ps
CPU time 10.47 seconds
Started Aug 08 06:27:10 PM PDT 24
Finished Aug 08 06:27:20 PM PDT 24
Peak memory 223916 kb
Host smart-d97e0550-13dc-4f14-8090-b63052b3f82d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540623700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.540623700 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.3240483123
Short name T865
Test name
Test status
Simulation time 33019934687 ps
CPU time 1092.31 seconds
Started Aug 08 06:27:11 PM PDT 24
Finished Aug 08 06:45:24 PM PDT 24
Peak memory 258352 kb
Host smart-3c2b7365-69bf-424e-aa41-e837544f35e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240483123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.324048312
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.3604340531
Short name T656
Test name
Test status
Simulation time 3877452138 ps
CPU time 80.34 seconds
Started Aug 08 06:27:10 PM PDT 24
Finished Aug 08 06:28:30 PM PDT 24
Peak memory 283980 kb
Host smart-9249531a-9524-4380-bdb4-ea68787ab484
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604340531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3
604340531 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.3925882016
Short name T436
Test name
Test status
Simulation time 1809969917 ps
CPU time 128.81 seconds
Started Aug 08 06:27:12 PM PDT 24
Finished Aug 08 06:29:21 PM PDT 24
Peak memory 289412 kb
Host smart-50bf62b2-8246-4270-884f-37b76c1b3fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925882016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3925882016 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.1143064866
Short name T612
Test name
Test status
Simulation time 1504971325 ps
CPU time 4.32 seconds
Started Aug 08 06:27:16 PM PDT 24
Finished Aug 08 06:27:21 PM PDT 24
Peak memory 217956 kb
Host smart-18c29c3d-3c87-4aee-91c0-ca62ff012755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143064866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1143064866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.4099314367
Short name T644
Test name
Test status
Simulation time 68550768 ps
CPU time 1.27 seconds
Started Aug 08 06:27:17 PM PDT 24
Finished Aug 08 06:27:18 PM PDT 24
Peak memory 219040 kb
Host smart-16d8ff29-6b0a-4718-9563-c5b9c181f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099314367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.4099314367 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_sideload.1890298988
Short name T297
Test name
Test status
Simulation time 1230222335 ps
CPU time 92.35 seconds
Started Aug 08 06:27:04 PM PDT 24
Finished Aug 08 06:28:37 PM PDT 24
Peak memory 261368 kb
Host smart-7dad8f36-179d-4896-81a4-d2d3fdd0c3ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890298988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1890298988 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1215530941
Short name T818
Test name
Test status
Simulation time 7722916792 ps
CPU time 44.55 seconds
Started Aug 08 06:27:03 PM PDT 24
Finished Aug 08 06:27:48 PM PDT 24
Peak memory 224148 kb
Host smart-f872cd76-6cbc-4e7c-b39e-0d5af46ace2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215530941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1215530941 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.3544734921
Short name T463
Test name
Test status
Simulation time 16712353477 ps
CPU time 1315.35 seconds
Started Aug 08 06:27:16 PM PDT 24
Finished Aug 08 06:49:12 PM PDT 24
Peak memory 671016 kb
Host smart-6f880220-bc8b-4886-b7b5-16f853ff4704
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3544734921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3544734921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.3722212718
Short name T504
Test name
Test status
Simulation time 500149333 ps
CPU time 5.31 seconds
Started Aug 08 06:27:10 PM PDT 24
Finished Aug 08 06:27:15 PM PDT 24
Peak memory 217748 kb
Host smart-8a296064-fc93-40e7-bd63-015a5df8be5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722212718 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.3722212718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2862609352
Short name T44
Test name
Test status
Simulation time 172540566 ps
CPU time 4.76 seconds
Started Aug 08 06:27:10 PM PDT 24
Finished Aug 08 06:27:15 PM PDT 24
Peak memory 217620 kb
Host smart-d3dd1c93-12ad-4b67-b796-f49f89b95377
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862609352 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2862609352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.2133436363
Short name T196
Test name
Test status
Simulation time 97048907354 ps
CPU time 3352.79 seconds
Started Aug 08 06:27:12 PM PDT 24
Finished Aug 08 07:23:05 PM PDT 24
Peak memory 3229588 kb
Host smart-e68b213c-8e47-483c-8608-eae74990b719
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2133436363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.2133436363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.4046517383
Short name T815
Test name
Test status
Simulation time 18589763236 ps
CPU time 1831.39 seconds
Started Aug 08 06:27:09 PM PDT 24
Finished Aug 08 06:57:41 PM PDT 24
Peak memory 1119004 kb
Host smart-fc9abe06-ff6d-4fe0-a75c-66bdf2cd5701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4046517383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.4046517383 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.4167363582
Short name T696
Test name
Test status
Simulation time 94913646949 ps
CPU time 1966.15 seconds
Started Aug 08 06:27:11 PM PDT 24
Finished Aug 08 06:59:57 PM PDT 24
Peak memory 2415048 kb
Host smart-c49ca160-2334-45fa-92f2-86d675b9062c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4167363582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.4167363582 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2218094065
Short name T271
Test name
Test status
Simulation time 49316994986 ps
CPU time 886.49 seconds
Started Aug 08 06:27:10 PM PDT 24
Finished Aug 08 06:41:56 PM PDT 24
Peak memory 691440 kb
Host smart-e6c4d71e-8dde-41d3-85af-468b5b893710
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2218094065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2218094065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.1521111897
Short name T263
Test name
Test status
Simulation time 174941144372 ps
CPU time 4374.28 seconds
Started Aug 08 06:27:10 PM PDT 24
Finished Aug 08 07:40:04 PM PDT 24
Peak memory 2248764 kb
Host smart-bf7a9ef7-e666-489a-9dbc-ba61363b118e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1521111897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1521111897 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.2431555115
Short name T228
Test name
Test status
Simulation time 64336341 ps
CPU time 0.91 seconds
Started Aug 08 06:27:34 PM PDT 24
Finished Aug 08 06:27:35 PM PDT 24
Peak memory 205236 kb
Host smart-42d53dca-825a-4b5c-91b0-1fc14b9970f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431555115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2431555115 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.3093979988
Short name T456
Test name
Test status
Simulation time 36550886846 ps
CPU time 216.37 seconds
Started Aug 08 06:27:25 PM PDT 24
Finished Aug 08 06:31:02 PM PDT 24
Peak memory 406080 kb
Host smart-f44ee81c-d099-4526-8cec-8b69434c6ede
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093979988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3093979988 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.3735867180
Short name T186
Test name
Test status
Simulation time 2072489458 ps
CPU time 191.94 seconds
Started Aug 08 06:27:17 PM PDT 24
Finished Aug 08 06:30:29 PM PDT 24
Peak memory 227212 kb
Host smart-e872dc31-31cc-49e4-891b-2bbdfe0d5a34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735867180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.373586718
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.948731817
Short name T1020
Test name
Test status
Simulation time 65094806963 ps
CPU time 353.66 seconds
Started Aug 08 06:27:25 PM PDT 24
Finished Aug 08 06:33:19 PM PDT 24
Peak memory 493180 kb
Host smart-1306f34c-3c7d-413a-9f4e-05f6aed2cc7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948731817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.94
8731817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.1096092670
Short name T845
Test name
Test status
Simulation time 10789004742 ps
CPU time 254.22 seconds
Started Aug 08 06:27:35 PM PDT 24
Finished Aug 08 06:31:49 PM PDT 24
Peak memory 468760 kb
Host smart-1feedf70-5cc5-40fd-8c2d-590de94bdbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096092670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1096092670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.1862859414
Short name T928
Test name
Test status
Simulation time 108180074 ps
CPU time 1.19 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 06:27:35 PM PDT 24
Peak memory 217384 kb
Host smart-a47cf5a7-8044-4564-bf00-ba7c05f68874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862859414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1862859414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.957789504
Short name T389
Test name
Test status
Simulation time 101039332 ps
CPU time 1.27 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 06:27:35 PM PDT 24
Peak memory 218752 kb
Host smart-707efd43-2273-45e6-8c99-3c8a4ab1ee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957789504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.957789504 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.710852063
Short name T530
Test name
Test status
Simulation time 68526636097 ps
CPU time 1563.49 seconds
Started Aug 08 06:27:17 PM PDT 24
Finished Aug 08 06:53:21 PM PDT 24
Peak memory 1793160 kb
Host smart-c3699523-07fb-4e7f-8b27-b55e919a4cab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710852063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_an
d_output.710852063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.1552295920
Short name T557
Test name
Test status
Simulation time 19693298126 ps
CPU time 305.27 seconds
Started Aug 08 06:27:17 PM PDT 24
Finished Aug 08 06:32:23 PM PDT 24
Peak memory 487472 kb
Host smart-3ec9b113-80b2-4a13-9c15-eee2dfddaa59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552295920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1552295920 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.3992016587
Short name T407
Test name
Test status
Simulation time 1174855712 ps
CPU time 19.7 seconds
Started Aug 08 06:27:17 PM PDT 24
Finished Aug 08 06:27:37 PM PDT 24
Peak memory 217872 kb
Host smart-ef46e14c-d76e-4f92-a628-d1e476adb07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992016587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3992016587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.1635602597
Short name T783
Test name
Test status
Simulation time 67577091 ps
CPU time 4.16 seconds
Started Aug 08 06:27:25 PM PDT 24
Finished Aug 08 06:27:29 PM PDT 24
Peak memory 217840 kb
Host smart-a75a151e-f200-4e8d-872c-73ee237915c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635602597 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.1635602597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.434987384
Short name T278
Test name
Test status
Simulation time 748763903 ps
CPU time 3.92 seconds
Started Aug 08 06:27:25 PM PDT 24
Finished Aug 08 06:27:29 PM PDT 24
Peak memory 217992 kb
Host smart-bb5b447f-cb52-4d2b-82e8-b35085b9c86c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434987384 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.kmac_test_vectors_kmac_xof.434987384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.321534595
Short name T118
Test name
Test status
Simulation time 119664964728 ps
CPU time 3319.13 seconds
Started Aug 08 06:27:26 PM PDT 24
Finished Aug 08 07:22:45 PM PDT 24
Peak memory 3184328 kb
Host smart-d66cbe0d-e02b-40eb-aa8c-0dc9d5fea77d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=321534595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.321534595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.2420836347
Short name T906
Test name
Test status
Simulation time 18481040686 ps
CPU time 1777.05 seconds
Started Aug 08 06:27:25 PM PDT 24
Finished Aug 08 06:57:02 PM PDT 24
Peak memory 1147784 kb
Host smart-44bc8a3b-6de3-46ad-91d9-3edfff2e463c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2420836347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2420836347 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1505336119
Short name T305
Test name
Test status
Simulation time 53980639905 ps
CPU time 1304.08 seconds
Started Aug 08 06:27:25 PM PDT 24
Finished Aug 08 06:49:10 PM PDT 24
Peak memory 910944 kb
Host smart-a29e476c-ff37-49c8-b8a5-62c4ece6fbf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1505336119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1505336119 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.3160673249
Short name T399
Test name
Test status
Simulation time 87193609443 ps
CPU time 915.49 seconds
Started Aug 08 06:27:25 PM PDT 24
Finished Aug 08 06:42:41 PM PDT 24
Peak memory 704836 kb
Host smart-a6007637-5066-4433-a73f-6561e530eb59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3160673249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.3160673249 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.2607260989
Short name T843
Test name
Test status
Simulation time 44808206681 ps
CPU time 4431.57 seconds
Started Aug 08 06:27:26 PM PDT 24
Finished Aug 08 07:41:18 PM PDT 24
Peak memory 2204612 kb
Host smart-ab706168-1ed7-44ed-b534-6cfba250e247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2607260989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.2607260989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.1633192716
Short name T340
Test name
Test status
Simulation time 94944573 ps
CPU time 0.81 seconds
Started Aug 08 06:27:40 PM PDT 24
Finished Aug 08 06:27:41 PM PDT 24
Peak memory 205128 kb
Host smart-1978bbed-9003-4248-81ea-85d3238c269f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633192716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1633192716 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.3938748078
Short name T596
Test name
Test status
Simulation time 33750586989 ps
CPU time 250.63 seconds
Started Aug 08 06:27:42 PM PDT 24
Finished Aug 08 06:31:53 PM PDT 24
Peak memory 319452 kb
Host smart-a2786a04-7e83-4819-b3af-2a08f50b25dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938748078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3938748078 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.3059334198
Short name T903
Test name
Test status
Simulation time 96644833497 ps
CPU time 983.18 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 06:43:56 PM PDT 24
Peak memory 258760 kb
Host smart-606b7d11-b2ca-42c8-baad-360270326e20
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059334198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.305933419
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1575080481
Short name T895
Test name
Test status
Simulation time 7572092847 ps
CPU time 183.7 seconds
Started Aug 08 06:27:40 PM PDT 24
Finished Aug 08 06:30:43 PM PDT 24
Peak memory 301544 kb
Host smart-014bc479-2144-40bf-a79e-406d6104bd99
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575080481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1
575080481 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.291221056
Short name T697
Test name
Test status
Simulation time 20875819672 ps
CPU time 119.25 seconds
Started Aug 08 06:27:43 PM PDT 24
Finished Aug 08 06:29:42 PM PDT 24
Peak memory 332268 kb
Host smart-9d2f5ab1-738b-418d-b40e-959825c0abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291221056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.291221056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.1717345064
Short name T646
Test name
Test status
Simulation time 523601788 ps
CPU time 2.95 seconds
Started Aug 08 06:27:41 PM PDT 24
Finished Aug 08 06:27:44 PM PDT 24
Peak memory 217556 kb
Host smart-6a98e792-7614-4b6f-b9be-0d1f855b497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717345064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1717345064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.1928988283
Short name T88
Test name
Test status
Simulation time 171934421 ps
CPU time 4.94 seconds
Started Aug 08 06:27:41 PM PDT 24
Finished Aug 08 06:27:46 PM PDT 24
Peak memory 222148 kb
Host smart-bc35db98-7c6b-4f8e-bfb9-ee79cfb29825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928988283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1928988283 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.2851591734
Short name T425
Test name
Test status
Simulation time 49469458740 ps
CPU time 212.84 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 06:31:06 PM PDT 24
Peak memory 498960 kb
Host smart-e0bda74a-00c2-4680-8a69-16151d08a100
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851591734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.2851591734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.4114230162
Short name T982
Test name
Test status
Simulation time 8796411158 ps
CPU time 252.62 seconds
Started Aug 08 06:27:34 PM PDT 24
Finished Aug 08 06:31:47 PM PDT 24
Peak memory 459400 kb
Host smart-3735ac11-fa38-4c2f-84e1-8320b5392709
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114230162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.4114230162 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.316784480
Short name T538
Test name
Test status
Simulation time 6455391210 ps
CPU time 33.5 seconds
Started Aug 08 06:27:32 PM PDT 24
Finished Aug 08 06:28:06 PM PDT 24
Peak memory 224108 kb
Host smart-8efe9b84-1dac-4d35-9b2c-6e40164f4244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316784480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.316784480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.553492286
Short name T659
Test name
Test status
Simulation time 52029827221 ps
CPU time 1890.11 seconds
Started Aug 08 06:27:41 PM PDT 24
Finished Aug 08 06:59:11 PM PDT 24
Peak memory 1270484 kb
Host smart-4c234d2d-21b6-4a84-a983-a6e3dbc9eecc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=553492286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.553492286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.957353760
Short name T314
Test name
Test status
Simulation time 168913098 ps
CPU time 4.54 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 06:27:38 PM PDT 24
Peak memory 218100 kb
Host smart-8380c152-3ef1-4c79-aa87-55d96c8cce39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957353760 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.kmac_test_vectors_kmac.957353760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.4244109808
Short name T680
Test name
Test status
Simulation time 141664412 ps
CPU time 4.09 seconds
Started Aug 08 06:27:40 PM PDT 24
Finished Aug 08 06:27:44 PM PDT 24
Peak memory 218028 kb
Host smart-e038ac39-f2c9-4008-94bf-4245c418e9bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244109808 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.4244109808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.257070472
Short name T933
Test name
Test status
Simulation time 221529168409 ps
CPU time 3004 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 07:17:38 PM PDT 24
Peak memory 3195972 kb
Host smart-c4677618-a3c7-44a8-87ef-607120516399
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=257070472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.257070472 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.2743467598
Short name T86
Test name
Test status
Simulation time 402819069398 ps
CPU time 3566.18 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 07:27:00 PM PDT 24
Peak memory 3090056 kb
Host smart-bc2190dd-59f4-4049-a6f3-005e23af1c8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2743467598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.2743467598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.290214877
Short name T203
Test name
Test status
Simulation time 132668955024 ps
CPU time 2349.97 seconds
Started Aug 08 06:27:32 PM PDT 24
Finished Aug 08 07:06:42 PM PDT 24
Peak memory 2344084 kb
Host smart-05bfd023-b295-497b-b0d4-08f812f518a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=290214877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.290214877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.1645407009
Short name T559
Test name
Test status
Simulation time 19125072224 ps
CPU time 881.34 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 06:42:15 PM PDT 24
Peak memory 703300 kb
Host smart-c395c8ee-6bce-4512-9217-c65ef5f92aa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1645407009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1645407009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.2494794047
Short name T383
Test name
Test status
Simulation time 280162268327 ps
CPU time 5859.65 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 08:05:13 PM PDT 24
Peak memory 2661348 kb
Host smart-f9834d1a-c06a-4b93-878b-40d34dbd195b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2494794047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2494794047 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.1108192241
Short name T748
Test name
Test status
Simulation time 219830053335 ps
CPU time 9263.69 seconds
Started Aug 08 06:27:33 PM PDT 24
Finished Aug 08 09:01:58 PM PDT 24
Peak memory 6426608 kb
Host smart-3664e433-bdd1-4bff-ba77-2d03f33963cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1108192241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1108192241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.2008211870
Short name T403
Test name
Test status
Simulation time 69969738 ps
CPU time 0.8 seconds
Started Aug 08 06:27:59 PM PDT 24
Finished Aug 08 06:28:00 PM PDT 24
Peak memory 205176 kb
Host smart-89988605-65f7-41cf-9964-c6c4578d4453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008211870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2008211870 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.3728798865
Short name T730
Test name
Test status
Simulation time 31724508403 ps
CPU time 181.23 seconds
Started Aug 08 06:27:49 PM PDT 24
Finished Aug 08 06:30:50 PM PDT 24
Peak memory 361276 kb
Host smart-7b0469f1-4cc0-4ca6-a8e3-2e8f26d6ba56
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728798865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3728798865 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.739488236
Short name T714
Test name
Test status
Simulation time 34080768188 ps
CPU time 899.35 seconds
Started Aug 08 06:27:43 PM PDT 24
Finished Aug 08 06:42:42 PM PDT 24
Peak memory 243152 kb
Host smart-92645b50-7cc7-4203-9192-6b45f4ccc531
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739488236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.739488236
+enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.3828117451
Short name T29
Test name
Test status
Simulation time 17580401006 ps
CPU time 319.03 seconds
Started Aug 08 06:27:52 PM PDT 24
Finished Aug 08 06:33:11 PM PDT 24
Peak memory 453212 kb
Host smart-a825532e-4694-46af-9b79-354fb4823143
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828117451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3
828117451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.4273175892
Short name T961
Test name
Test status
Simulation time 7817296123 ps
CPU time 246.53 seconds
Started Aug 08 06:27:57 PM PDT 24
Finished Aug 08 06:32:04 PM PDT 24
Peak memory 436860 kb
Host smart-445cabe9-0256-4244-a735-9dfaeeaf01df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273175892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.4273175892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.18448710
Short name T660
Test name
Test status
Simulation time 812428238 ps
CPU time 4.8 seconds
Started Aug 08 06:27:56 PM PDT 24
Finished Aug 08 06:28:01 PM PDT 24
Peak memory 217928 kb
Host smart-3821435f-9f73-4ef5-af84-b47c14176a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18448710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.18448710 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.1070238827
Short name T8
Test name
Test status
Simulation time 111574541 ps
CPU time 1.41 seconds
Started Aug 08 06:27:58 PM PDT 24
Finished Aug 08 06:28:00 PM PDT 24
Peak memory 219040 kb
Host smart-20026a9d-da77-4299-990e-3d3b27d8b5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070238827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1070238827 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.974038502
Short name T477
Test name
Test status
Simulation time 39381988044 ps
CPU time 478.4 seconds
Started Aug 08 06:27:42 PM PDT 24
Finished Aug 08 06:35:40 PM PDT 24
Peak memory 805696 kb
Host smart-a2342f08-c2e5-42ad-9edc-3089c8d20829
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974038502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_an
d_output.974038502 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.3908403344
Short name T1027
Test name
Test status
Simulation time 46183157922 ps
CPU time 285.19 seconds
Started Aug 08 06:27:47 PM PDT 24
Finished Aug 08 06:32:32 PM PDT 24
Peak memory 488880 kb
Host smart-9a8aa10e-a0a1-4654-af51-94c04850eed3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908403344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3908403344 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.665461752
Short name T968
Test name
Test status
Simulation time 656849630 ps
CPU time 33.89 seconds
Started Aug 08 06:27:42 PM PDT 24
Finished Aug 08 06:28:15 PM PDT 24
Peak memory 221496 kb
Host smart-3d7343e9-308b-46d0-b81d-ff256a64e6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665461752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.665461752 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.1465995841
Short name T565
Test name
Test status
Simulation time 96968170492 ps
CPU time 869.46 seconds
Started Aug 08 06:27:58 PM PDT 24
Finished Aug 08 06:42:28 PM PDT 24
Peak memory 854392 kb
Host smart-b4a13a3b-e421-4522-bf52-8e19f323e3b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1465995841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1465995841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.2103095875
Short name T191
Test name
Test status
Simulation time 69859373 ps
CPU time 4.34 seconds
Started Aug 08 06:27:52 PM PDT 24
Finished Aug 08 06:27:57 PM PDT 24
Peak memory 217712 kb
Host smart-bb994acf-9530-4822-9084-0d9ed51211b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103095875 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.2103095875 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3110303259
Short name T924
Test name
Test status
Simulation time 1194820766 ps
CPU time 4.66 seconds
Started Aug 08 06:27:49 PM PDT 24
Finished Aug 08 06:27:53 PM PDT 24
Peak memory 218116 kb
Host smart-fc09672c-e8b7-4a48-ac13-80c42af50c05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110303259 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3110303259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.2541090733
Short name T781
Test name
Test status
Simulation time 75543249888 ps
CPU time 1798.36 seconds
Started Aug 08 06:27:41 PM PDT 24
Finished Aug 08 06:57:40 PM PDT 24
Peak memory 1149260 kb
Host smart-7a6434a0-374f-4c15-aa06-d86e2232c174
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2541090733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.2541090733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.1471412328
Short name T524
Test name
Test status
Simulation time 77970020521 ps
CPU time 2684.31 seconds
Started Aug 08 06:27:41 PM PDT 24
Finished Aug 08 07:12:26 PM PDT 24
Peak memory 2992440 kb
Host smart-fcab0b97-a245-4053-8871-15f429738f35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1471412328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.1471412328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.2793031745
Short name T79
Test name
Test status
Simulation time 70001382846 ps
CPU time 2407.73 seconds
Started Aug 08 06:27:49 PM PDT 24
Finished Aug 08 07:07:57 PM PDT 24
Peak memory 2385568 kb
Host smart-dd4ba0b7-9650-4ec7-8eb0-1b392dcbaf17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2793031745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2793031745 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.1294332308
Short name T822
Test name
Test status
Simulation time 9902728774 ps
CPU time 870.4 seconds
Started Aug 08 06:27:49 PM PDT 24
Finished Aug 08 06:42:19 PM PDT 24
Peak memory 694812 kb
Host smart-ae4e9631-df7d-4657-8641-14f9b4f6ec7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1294332308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.1294332308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3713351080
Short name T301
Test name
Test status
Simulation time 1467489512923 ps
CPU time 9442.72 seconds
Started Aug 08 06:27:49 PM PDT 24
Finished Aug 08 09:05:13 PM PDT 24
Peak memory 6465196 kb
Host smart-f853b7ba-8847-4c5f-a5e5-9ac61fe2902c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3713351080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3713351080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.3073207365
Short name T496
Test name
Test status
Simulation time 23440237 ps
CPU time 0.86 seconds
Started Aug 08 06:23:41 PM PDT 24
Finished Aug 08 06:23:47 PM PDT 24
Peak memory 205220 kb
Host smart-276c4aa1-5704-43b0-95e8-2fa1e5c15ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073207365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3073207365 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.638179007
Short name T199
Test name
Test status
Simulation time 20481332230 ps
CPU time 189.9 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 06:26:46 PM PDT 24
Peak memory 388528 kb
Host smart-a2b31ad3-b106-45fe-b403-02136c50c834
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638179007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.638179007 +enable_masking=0
+sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.747349831
Short name T692
Test name
Test status
Simulation time 4050325020 ps
CPU time 84.98 seconds
Started Aug 08 06:23:27 PM PDT 24
Finished Aug 08 06:24:53 PM PDT 24
Peak memory 256392 kb
Host smart-54bf41d6-93b4-4568-8488-7102e9570b7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747349831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_part
ial_data.747349831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.1868483692
Short name T146
Test name
Test status
Simulation time 34647584487 ps
CPU time 1053.65 seconds
Started Aug 08 06:23:19 PM PDT 24
Finished Aug 08 06:40:53 PM PDT 24
Peak memory 260996 kb
Host smart-6c66b34b-a80e-4c3a-a2b3-93aff15f6d34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868483692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1868483692
+enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.2205559472
Short name T384
Test name
Test status
Simulation time 125148305 ps
CPU time 3.55 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 06:23:29 PM PDT 24
Peak memory 216660 kb
Host smart-65422645-830d-4b3f-8699-83ec025d9d53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2205559472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2205559472 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1353802328
Short name T706
Test name
Test status
Simulation time 58872433 ps
CPU time 3.33 seconds
Started Aug 08 06:23:16 PM PDT 24
Finished Aug 08 06:23:20 PM PDT 24
Peak memory 216540 kb
Host smart-3366e02a-a05f-4e21-b407-b626251ca6a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1353802328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1353802328 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.871618363
Short name T1006
Test name
Test status
Simulation time 3413884020 ps
CPU time 42.08 seconds
Started Aug 08 06:23:41 PM PDT 24
Finished Aug 08 06:24:28 PM PDT 24
Peak memory 218868 kb
Host smart-f8aa1ef5-36a8-4bfe-90b7-160cd4094d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871618363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.871618363 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.3914196397
Short name T438
Test name
Test status
Simulation time 78078931493 ps
CPU time 258.39 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 06:27:43 PM PDT 24
Peak memory 441500 kb
Host smart-82787382-9777-456c-ba9c-211c4beff1b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914196397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.39
14196397 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.3001842087
Short name T663
Test name
Test status
Simulation time 49411499775 ps
CPU time 289.63 seconds
Started Aug 08 06:23:28 PM PDT 24
Finished Aug 08 06:28:17 PM PDT 24
Peak memory 472792 kb
Host smart-ed05968f-9e3d-4a4f-a05f-52f5aa52b1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001842087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3001842087 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.3799964730
Short name T780
Test name
Test status
Simulation time 1372815087 ps
CPU time 6.66 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:23:21 PM PDT 24
Peak memory 217700 kb
Host smart-568c31d3-1439-43a6-b9ff-af5265e95044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799964730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3799964730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.1760146676
Short name T84
Test name
Test status
Simulation time 33094837 ps
CPU time 1.19 seconds
Started Aug 08 06:23:28 PM PDT 24
Finished Aug 08 06:23:29 PM PDT 24
Peak memory 219300 kb
Host smart-b4798120-2284-4295-9d55-4652e22e0dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760146676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1760146676 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1792941430
Short name T313
Test name
Test status
Simulation time 7962132678 ps
CPU time 199.24 seconds
Started Aug 08 06:23:23 PM PDT 24
Finished Aug 08 06:26:45 PM PDT 24
Peak memory 338636 kb
Host smart-cb001d3b-3a87-4cbf-9f03-8818c388338a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792941430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1792941430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.4281197468
Short name T91
Test name
Test status
Simulation time 597487543 ps
CPU time 15.86 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:23:50 PM PDT 24
Peak memory 228516 kb
Host smart-42ece4d3-4213-45eb-8ae6-a227ab1238b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281197468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.4281197468 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.3017970137
Short name T615
Test name
Test status
Simulation time 13339325949 ps
CPU time 391.93 seconds
Started Aug 08 06:23:14 PM PDT 24
Finished Aug 08 06:29:46 PM PDT 24
Peak memory 579088 kb
Host smart-90f80cd1-f02e-420d-a370-9bd738aca424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017970137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3017970137 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.4010540251
Short name T1029
Test name
Test status
Simulation time 9439742504 ps
CPU time 42.05 seconds
Started Aug 08 06:23:18 PM PDT 24
Finished Aug 08 06:24:05 PM PDT 24
Peak memory 218244 kb
Host smart-3892ee40-4b65-4edf-8076-2e260261ef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010540251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.4010540251 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.811231296
Short name T448
Test name
Test status
Simulation time 32700872107 ps
CPU time 377.39 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 06:29:53 PM PDT 24
Peak memory 369940 kb
Host smart-65370d90-c751-4095-be8d-1d12815d5167
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=811231296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.811231296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.4162901844
Short name T36
Test name
Test status
Simulation time 443276853895 ps
CPU time 1893.95 seconds
Started Aug 08 06:23:41 PM PDT 24
Finished Aug 08 06:55:16 PM PDT 24
Peak memory 417940 kb
Host smart-5779ad08-1747-496f-9540-7bffdef46de7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162901844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.4162901844 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.3796456964
Short name T1001
Test name
Test status
Simulation time 251822974 ps
CPU time 5.43 seconds
Started Aug 08 06:23:23 PM PDT 24
Finished Aug 08 06:23:33 PM PDT 24
Peak memory 217716 kb
Host smart-85a574fd-d39b-48fb-b4a7-fdabbea0b115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796456964 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.3796456964 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.2227190319
Short name T291
Test name
Test status
Simulation time 78966084 ps
CPU time 3.49 seconds
Started Aug 08 06:23:19 PM PDT 24
Finished Aug 08 06:23:22 PM PDT 24
Peak memory 217876 kb
Host smart-0dc17a5e-6748-4dc5-9f9e-bb168fc4ae95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227190319 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.2227190319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.4245543070
Short name T969
Test name
Test status
Simulation time 276479435694 ps
CPU time 3037.92 seconds
Started Aug 08 06:23:43 PM PDT 24
Finished Aug 08 07:14:21 PM PDT 24
Peak memory 3305420 kb
Host smart-9cf9fb80-f93f-476e-9386-713d9d66b478
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4245543070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.4245543070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.413502214
Short name T133
Test name
Test status
Simulation time 125169477014 ps
CPU time 2914.16 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 07:11:58 PM PDT 24
Peak memory 3125424 kb
Host smart-8f6aba13-4174-41e6-b796-c77e2fefb3f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=413502214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.413502214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.1465356821
Short name T649
Test name
Test status
Simulation time 189115016713 ps
CPU time 2079.28 seconds
Started Aug 08 06:23:13 PM PDT 24
Finished Aug 08 06:57:53 PM PDT 24
Peak memory 2310124 kb
Host smart-6fc8f45f-a38b-4d8f-8856-3ce7bfb225eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1465356821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.1465356821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.648420122
Short name T766
Test name
Test status
Simulation time 191242692634 ps
CPU time 1518.41 seconds
Started Aug 08 06:23:16 PM PDT 24
Finished Aug 08 06:48:35 PM PDT 24
Peak memory 1687884 kb
Host smart-1f36cee0-e31d-45ed-a643-a166889c0d11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=648420122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.648420122 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.681245308
Short name T956
Test name
Test status
Simulation time 146558741050 ps
CPU time 8202.62 seconds
Started Aug 08 06:23:15 PM PDT 24
Finished Aug 08 08:39:59 PM PDT 24
Peak memory 6455492 kb
Host smart-255fba78-054b-4b81-837b-78ea8a155243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=681245308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.681245308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.3613412620
Short name T371
Test name
Test status
Simulation time 45471893 ps
CPU time 0.78 seconds
Started Aug 08 06:23:26 PM PDT 24
Finished Aug 08 06:23:27 PM PDT 24
Peak memory 205252 kb
Host smart-8abb354a-0d5b-4e8a-b9e7-baf401982561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613412620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3613412620 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.3057937127
Short name T991
Test name
Test status
Simulation time 4480527641 ps
CPU time 119.43 seconds
Started Aug 08 06:23:25 PM PDT 24
Finished Aug 08 06:25:24 PM PDT 24
Peak memory 327840 kb
Host smart-059a255d-2009-4aeb-82bb-9ca6e6c2f940
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057937127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3057937127 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1267615589
Short name T761
Test name
Test status
Simulation time 4707572816 ps
CPU time 218.58 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 06:27:01 PM PDT 24
Peak memory 304800 kb
Host smart-1da0ccac-900e-430f-9944-cb0bf663668f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267615589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.1267615589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.3612073111
Short name T379
Test name
Test status
Simulation time 6185574699 ps
CPU time 236.02 seconds
Started Aug 08 06:23:45 PM PDT 24
Finished Aug 08 06:27:41 PM PDT 24
Peak memory 232148 kb
Host smart-fa7f9c03-c8d8-4260-8f65-a705fcff532a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612073111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3612073111
+enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.1119128829
Short name T388
Test name
Test status
Simulation time 132514537 ps
CPU time 8.45 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:23:29 PM PDT 24
Peak memory 215652 kb
Host smart-d7b13e6f-7b1c-437b-9ab9-859d4fb213af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1119128829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1119128829 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.634859531
Short name T997
Test name
Test status
Simulation time 73618346 ps
CPU time 5.28 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:23:38 PM PDT 24
Peak memory 216716 kb
Host smart-8a700672-2156-40ff-9366-ab9cb83a1667
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=634859531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.634859531 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.832188498
Short name T50
Test name
Test status
Simulation time 27326941519 ps
CPU time 66.83 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:24:40 PM PDT 24
Peak memory 219088 kb
Host smart-c58c31e6-4627-4ce2-85d6-6e19ea367fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832188498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.832188498 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.3782439301
Short name T836
Test name
Test status
Simulation time 18516042593 ps
CPU time 182 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:26:35 PM PDT 24
Peak memory 362332 kb
Host smart-ef2be3ed-bdcc-4bee-a62c-1a34baa01706
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782439301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.37
82439301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.2324182535
Short name T328
Test name
Test status
Simulation time 2199333272 ps
CPU time 30.54 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 06:23:54 PM PDT 24
Peak memory 251952 kb
Host smart-e1813179-3a9a-417d-bf0c-3bd2e2753ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324182535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2324182535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.852629940
Short name T469
Test name
Test status
Simulation time 763186038 ps
CPU time 4.01 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 06:23:30 PM PDT 24
Peak memory 217580 kb
Host smart-d7e84c80-ad0b-4149-a44f-d5137373dc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852629940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.852629940 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.734380977
Short name T1028
Test name
Test status
Simulation time 115379920 ps
CPU time 1.15 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:23:23 PM PDT 24
Peak memory 219212 kb
Host smart-1fefc1ff-4cc3-4ed6-af32-c1be2a1aca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734380977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.734380977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.1845304862
Short name T494
Test name
Test status
Simulation time 86585053967 ps
CPU time 453.49 seconds
Started Aug 08 06:23:23 PM PDT 24
Finished Aug 08 06:30:59 PM PDT 24
Peak memory 807328 kb
Host smart-73361ac9-90ff-4b80-bfdc-d929dd641198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845304862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.1845304862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.3913045218
Short name T757
Test name
Test status
Simulation time 16721182965 ps
CPU time 214.3 seconds
Started Aug 08 06:23:26 PM PDT 24
Finished Aug 08 06:27:00 PM PDT 24
Peak memory 307432 kb
Host smart-c3121d67-3916-4062-8db3-f918af1ae655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913045218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3913045218 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.1510227957
Short name T932
Test name
Test status
Simulation time 976043361 ps
CPU time 82.01 seconds
Started Aug 08 06:23:37 PM PDT 24
Finished Aug 08 06:24:59 PM PDT 24
Peak memory 254856 kb
Host smart-62123bf2-25a0-4942-8fd0-67905eb56f79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510227957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1510227957 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.631235895
Short name T507
Test name
Test status
Simulation time 1977258699 ps
CPU time 32.02 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:24:07 PM PDT 24
Peak memory 218132 kb
Host smart-10fa4d5e-c2de-4c00-a5fc-b96a6e95bedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631235895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.631235895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.1016335500
Short name T54
Test name
Test status
Simulation time 3774176249 ps
CPU time 25.9 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 06:23:55 PM PDT 24
Peak memory 233592 kb
Host smart-40984aa9-3894-48c4-b786-67f522f3d266
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1016335500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1016335500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.1352564293
Short name T549
Test name
Test status
Simulation time 257638923 ps
CPU time 4.07 seconds
Started Aug 08 06:23:25 PM PDT 24
Finished Aug 08 06:23:29 PM PDT 24
Peak memory 217932 kb
Host smart-b62ccd45-7cb5-4a1b-985d-1b34c499c97e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352564293 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.1352564293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.2135577343
Short name T683
Test name
Test status
Simulation time 986306183 ps
CPU time 4.8 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:23:40 PM PDT 24
Peak memory 218004 kb
Host smart-e92c1391-ff17-4f6c-9fb7-52bcd4dfb901
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135577343 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.2135577343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.1092992185
Short name T522
Test name
Test status
Simulation time 70461869406 ps
CPU time 1819.86 seconds
Started Aug 08 06:23:23 PM PDT 24
Finished Aug 08 06:53:43 PM PDT 24
Peak memory 1162776 kb
Host smart-a12d68f3-0196-4b81-91f2-db88ff2ce21b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1092992185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.1092992185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.3393327864
Short name T221
Test name
Test status
Simulation time 70417642175 ps
CPU time 1761.3 seconds
Started Aug 08 06:23:27 PM PDT 24
Finished Aug 08 06:52:49 PM PDT 24
Peak memory 1128216 kb
Host smart-09c68c30-4784-44b4-a7a7-3238996abfab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3393327864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3393327864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.1067598966
Short name T368
Test name
Test status
Simulation time 61576643806 ps
CPU time 2082.94 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:58:15 PM PDT 24
Peak memory 2418336 kb
Host smart-79516b4d-1dda-4e95-932c-8055fc27e7d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1067598966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.1067598966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.4204273206
Short name T691
Test name
Test status
Simulation time 33985705179 ps
CPU time 1318.25 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:45:19 PM PDT 24
Peak memory 1755540 kb
Host smart-7ec738e4-e656-40d5-b3be-adab8cc4d91f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4204273206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.4204273206 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.2294321991
Short name T492
Test name
Test status
Simulation time 213896279177 ps
CPU time 5521.02 seconds
Started Aug 08 06:23:30 PM PDT 24
Finished Aug 08 07:55:31 PM PDT 24
Peak memory 2723932 kb
Host smart-3bd53645-f7a1-4946-bb2d-6d1c1ea62b1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2294321991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.2294321991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1333280015
Short name T881
Test name
Test status
Simulation time 574064798423 ps
CPU time 8258.32 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 08:41:11 PM PDT 24
Peak memory 6302680 kb
Host smart-4c81f4a1-3426-4581-b65f-5208a180dd93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1333280015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1333280015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.1263685359
Short name T532
Test name
Test status
Simulation time 16954141 ps
CPU time 0.77 seconds
Started Aug 08 06:23:28 PM PDT 24
Finished Aug 08 06:23:29 PM PDT 24
Peak memory 205128 kb
Host smart-c3a172aa-d685-497b-bad3-4b08fdf46d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263685359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1263685359 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.2187218209
Short name T134
Test name
Test status
Simulation time 15295682844 ps
CPU time 202.97 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:26:54 PM PDT 24
Peak memory 366780 kb
Host smart-5b2d9545-9e06-4436-ab47-1a181c714f54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187218209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2187218209 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.932383595
Short name T1024
Test name
Test status
Simulation time 47480786607 ps
CPU time 202.42 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:26:56 PM PDT 24
Peak memory 362628 kb
Host smart-a95dc921-0041-43fc-924f-42ad7cda2483
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932383595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_part
ial_data.932383595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.1588454133
Short name T645
Test name
Test status
Simulation time 11489246308 ps
CPU time 380.26 seconds
Started Aug 08 06:23:18 PM PDT 24
Finished Aug 08 06:29:43 PM PDT 24
Peak memory 237404 kb
Host smart-eaf46cec-8227-4ef6-bf68-4208ffcb92da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588454133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1588454133
+enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.181122856
Short name T482
Test name
Test status
Simulation time 1319241703 ps
CPU time 9.14 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:23:40 PM PDT 24
Peak memory 221872 kb
Host smart-719b9218-3038-4e19-9234-33b631fced7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=181122856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.181122856 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.233011685
Short name T329
Test name
Test status
Simulation time 1191585320 ps
CPU time 14.5 seconds
Started Aug 08 06:23:52 PM PDT 24
Finished Aug 08 06:24:07 PM PDT 24
Peak memory 219388 kb
Host smart-22d6673d-a472-42cb-b71e-80377f914900
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=233011685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.233011685 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.476492895
Short name T963
Test name
Test status
Simulation time 6228802874 ps
CPU time 148.58 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 06:25:57 PM PDT 24
Peak memory 347668 kb
Host smart-3a2fe6d5-5e46-46ff-9a1f-b860e5153444
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476492895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.476
492895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.1746177909
Short name T668
Test name
Test status
Simulation time 19759255709 ps
CPU time 360.99 seconds
Started Aug 08 06:23:27 PM PDT 24
Finished Aug 08 06:29:29 PM PDT 24
Peak memory 377092 kb
Host smart-42f1b6f0-9963-41a0-8a30-6e849b6f05b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746177909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1746177909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.422248244
Short name T64
Test name
Test status
Simulation time 2769056442 ps
CPU time 4.52 seconds
Started Aug 08 06:23:50 PM PDT 24
Finished Aug 08 06:23:55 PM PDT 24
Peak memory 217680 kb
Host smart-970da62d-6df4-4457-aaa5-915d9f3867b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422248244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.422248244 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.2106430569
Short name T300
Test name
Test status
Simulation time 2460535547 ps
CPU time 9.37 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:23:41 PM PDT 24
Peak memory 228844 kb
Host smart-181c292d-1f07-4c66-8c22-ba74cb2e7eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106430569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.2106430569 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.1068891657
Short name T77
Test name
Test status
Simulation time 436831687552 ps
CPU time 3704.76 seconds
Started Aug 08 06:23:19 PM PDT 24
Finished Aug 08 07:25:05 PM PDT 24
Peak memory 3100704 kb
Host smart-329f1eae-e0eb-4bec-9931-9797fc2824cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068891657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.1068891657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.275655400
Short name T431
Test name
Test status
Simulation time 1101358460 ps
CPU time 68.87 seconds
Started Aug 08 06:23:20 PM PDT 24
Finished Aug 08 06:24:29 PM PDT 24
Peak memory 248864 kb
Host smart-96823853-2c44-4d75-a069-dd7c21222649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275655400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.275655400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.609066378
Short name T372
Test name
Test status
Simulation time 3094222569 ps
CPU time 85.6 seconds
Started Aug 08 06:23:20 PM PDT 24
Finished Aug 08 06:24:46 PM PDT 24
Peak memory 302816 kb
Host smart-f12e0780-5012-4171-92f4-68bd7632171b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609066378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.609066378 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.745558812
Short name T934
Test name
Test status
Simulation time 9882035002 ps
CPU time 49.11 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 06:24:25 PM PDT 24
Peak memory 220408 kb
Host smart-b92ef29d-6684-4c7b-a689-ca58c63b1527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745558812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.745558812 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.1363022576
Short name T460
Test name
Test status
Simulation time 10351667449 ps
CPU time 202.75 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:26:57 PM PDT 24
Peak memory 292936 kb
Host smart-5e545387-1761-4535-8fb5-afaba6faac25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1363022576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1363022576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.3867777098
Short name T400
Test name
Test status
Simulation time 68058964 ps
CPU time 3.87 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:23:38 PM PDT 24
Peak memory 218132 kb
Host smart-ef7b8997-90aa-45fd-9b95-f4c05240e63a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867777098 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.3867777098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3450792606
Short name T1008
Test name
Test status
Simulation time 183642805 ps
CPU time 4.61 seconds
Started Aug 08 06:23:30 PM PDT 24
Finished Aug 08 06:23:35 PM PDT 24
Peak memory 218080 kb
Host smart-d0701eff-e42b-4da2-bf66-992aeba126a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450792606 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3450792606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.1539059588
Short name T282
Test name
Test status
Simulation time 543128237522 ps
CPU time 3475.64 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 07:21:30 PM PDT 24
Peak memory 3254832 kb
Host smart-42e32763-0408-444a-a104-0d034b1b68a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1539059588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.1539059588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.2629716380
Short name T629
Test name
Test status
Simulation time 76718543643 ps
CPU time 1790.1 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 06:53:16 PM PDT 24
Peak memory 1130720 kb
Host smart-d2887513-8d3a-4cd8-905a-7a74669f0772
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2629716380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.2629716380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.2142441343
Short name T598
Test name
Test status
Simulation time 161879115753 ps
CPU time 2229.93 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 07:00:39 PM PDT 24
Peak memory 2315672 kb
Host smart-3da83cb1-38dc-4d18-aee7-0e52e0085b87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2142441343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.2142441343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.3982598730
Short name T793
Test name
Test status
Simulation time 38389575479 ps
CPU time 922.98 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 06:38:45 PM PDT 24
Peak memory 704904 kb
Host smart-ac0b9ceb-fd5a-485c-9ce0-fd71371064ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3982598730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.3982598730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.1138036263
Short name T909
Test name
Test status
Simulation time 111492223096 ps
CPU time 5843.66 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 08:00:46 PM PDT 24
Peak memory 2716684 kb
Host smart-c06d5875-a434-4ded-92d1-7d760a220cf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1138036263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.1138036263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.2425203527
Short name T366
Test name
Test status
Simulation time 396267928606 ps
CPU time 4971.76 seconds
Started Aug 08 06:23:16 PM PDT 24
Finished Aug 08 07:46:09 PM PDT 24
Peak memory 2243856 kb
Host smart-792a2bf1-11bf-443f-aa64-5a8753407077
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2425203527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2425203527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.2055042
Short name T378
Test name
Test status
Simulation time 26267712 ps
CPU time 0.79 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:23:36 PM PDT 24
Peak memory 205236 kb
Host smart-45fed871-2321-48b3-839b-632d88f043fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2055042 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.3373497866
Short name T360
Test name
Test status
Simulation time 5113464526 ps
CPU time 241.8 seconds
Started Aug 08 06:23:28 PM PDT 24
Finished Aug 08 06:27:30 PM PDT 24
Peak memory 323892 kb
Host smart-8342f964-4dff-403a-9f3b-88b660a07599
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373497866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3373497866 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.543398504
Short name T528
Test name
Test status
Simulation time 13629361163 ps
CPU time 72.72 seconds
Started Aug 08 06:23:32 PM PDT 24
Finished Aug 08 06:24:45 PM PDT 24
Peak memory 246576 kb
Host smart-54e4e894-dabf-4fbb-8f49-03f56b9fb909
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543398504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_part
ial_data.543398504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.464809311
Short name T1041
Test name
Test status
Simulation time 5442800948 ps
CPU time 211.88 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:27:03 PM PDT 24
Peak memory 229952 kb
Host smart-b28d1a72-3068-418a-85dd-51533bab0533
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464809311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.464809311 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2192142079
Short name T201
Test name
Test status
Simulation time 1768059800 ps
CPU time 36.87 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 06:24:06 PM PDT 24
Peak memory 223832 kb
Host smart-8a71206b-8698-451a-ba12-51b311632511
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2192142079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2192142079 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2174326367
Short name T312
Test name
Test status
Simulation time 1970016712 ps
CPU time 17.01 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 06:23:56 PM PDT 24
Peak memory 222532 kb
Host smart-5ae22326-9c9d-4112-8e90-dd5dddcbe789
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2174326367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2174326367 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.1214575538
Short name T616
Test name
Test status
Simulation time 3303865123 ps
CPU time 45.1 seconds
Started Aug 08 06:23:25 PM PDT 24
Finished Aug 08 06:24:10 PM PDT 24
Peak memory 218600 kb
Host smart-422f9150-162b-401c-9f31-1eb17bcdb269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214575538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1214575538 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.2080169064
Short name T94
Test name
Test status
Simulation time 11702369880 ps
CPU time 175.69 seconds
Started Aug 08 06:23:46 PM PDT 24
Finished Aug 08 06:26:41 PM PDT 24
Peak memory 287104 kb
Host smart-56d2d6ca-72a3-4805-b7f5-b8b2f1e7f0de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080169064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.20
80169064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.1412454854
Short name T755
Test name
Test status
Simulation time 1766452660 ps
CPU time 63.52 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:24:38 PM PDT 24
Peak memory 254588 kb
Host smart-478101ce-a214-4e10-b594-07f514428e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412454854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1412454854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.2508654656
Short name T607
Test name
Test status
Simulation time 3601390137 ps
CPU time 5.07 seconds
Started Aug 08 06:23:28 PM PDT 24
Finished Aug 08 06:23:33 PM PDT 24
Peak memory 219140 kb
Host smart-0cb8804c-835c-440f-b73d-80b38e1c2c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508654656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2508654656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.4031598306
Short name T96
Test name
Test status
Simulation time 458695875 ps
CPU time 12.63 seconds
Started Aug 08 06:23:24 PM PDT 24
Finished Aug 08 06:23:37 PM PDT 24
Peak memory 232232 kb
Host smart-53ab911f-606c-44ed-91c5-b592893a7811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031598306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.4031598306 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.1431602076
Short name T317
Test name
Test status
Simulation time 4792116592 ps
CPU time 220.25 seconds
Started Aug 08 06:23:27 PM PDT 24
Finished Aug 08 06:27:08 PM PDT 24
Peak memory 364164 kb
Host smart-ad147905-b732-4f3f-96f4-28d4c37f8351
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431602076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.1431602076 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.1801672817
Short name T25
Test name
Test status
Simulation time 7806707394 ps
CPU time 185.87 seconds
Started Aug 08 06:23:26 PM PDT 24
Finished Aug 08 06:26:32 PM PDT 24
Peak memory 389500 kb
Host smart-e64f8fe2-064f-491b-ac88-83cbf329b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801672817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1801672817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.2868777182
Short name T834
Test name
Test status
Simulation time 8521274404 ps
CPU time 163.44 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 06:26:04 PM PDT 24
Peak memory 300380 kb
Host smart-26cb0163-e106-4fec-9225-2aff2b38ae7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868777182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2868777182 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.885549349
Short name T966
Test name
Test status
Simulation time 351219142 ps
CPU time 17.49 seconds
Started Aug 08 06:23:42 PM PDT 24
Finished Aug 08 06:24:00 PM PDT 24
Peak memory 218172 kb
Host smart-babc8306-1402-45f0-a4bc-ec34eb976667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885549349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.885549349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.2267553275
Short name T777
Test name
Test status
Simulation time 8011564113 ps
CPU time 780.35 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 06:36:29 PM PDT 24
Peak memory 590960 kb
Host smart-9600b626-505f-4d61-8d95-ea7354cbca0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2267553275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2267553275 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.1514618131
Short name T809
Test name
Test status
Simulation time 898650357 ps
CPU time 5.06 seconds
Started Aug 08 06:23:40 PM PDT 24
Finished Aug 08 06:23:45 PM PDT 24
Peak memory 217836 kb
Host smart-42f3c801-a59c-450a-bee6-f0068cade1fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514618131 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.1514618131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1279866156
Short name T475
Test name
Test status
Simulation time 65136741 ps
CPU time 4.05 seconds
Started Aug 08 06:23:52 PM PDT 24
Finished Aug 08 06:23:56 PM PDT 24
Peak memory 217812 kb
Host smart-333e1005-13d8-4f8a-9949-d583027f8450
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279866156 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1279866156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2779275166
Short name T1022
Test name
Test status
Simulation time 204656956394 ps
CPU time 3716.97 seconds
Started Aug 08 06:23:21 PM PDT 24
Finished Aug 08 07:25:19 PM PDT 24
Peak memory 3266540 kb
Host smart-7e2587c1-a9f1-4c45-9197-c986047d6fcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2779275166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2779275166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.3770890672
Short name T299
Test name
Test status
Simulation time 619403691199 ps
CPU time 3326.88 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 07:18:58 PM PDT 24
Peak memory 3097404 kb
Host smart-c910db5f-678d-4641-ba67-a4aaadeb8c86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3770890672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.3770890672 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.2511957335
Short name T786
Test name
Test status
Simulation time 13659222005 ps
CPU time 1236.03 seconds
Started Aug 08 06:23:25 PM PDT 24
Finished Aug 08 06:44:02 PM PDT 24
Peak memory 919496 kb
Host smart-9e6bf7f8-5ca2-4c7c-af47-336aea805cba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2511957335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2511957335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.1934315359
Short name T883
Test name
Test status
Simulation time 32706285313 ps
CPU time 1308.42 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:45:41 PM PDT 24
Peak memory 1721412 kb
Host smart-c34b7203-cb25-4cfb-a4ad-112658f70af4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1934315359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.1934315359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.1067357956
Short name T292
Test name
Test status
Simulation time 180537057396 ps
CPU time 10591.6 seconds
Started Aug 08 06:23:26 PM PDT 24
Finished Aug 08 09:19:59 PM PDT 24
Peak memory 7890180 kb
Host smart-59926d2a-5910-4ffa-a84c-511d84c986ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1067357956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.1067357956 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.1737365494
Short name T169
Test name
Test status
Simulation time 2179834437869 ps
CPU time 10161.6 seconds
Started Aug 08 06:23:22 PM PDT 24
Finished Aug 08 09:12:45 PM PDT 24
Peak memory 6435112 kb
Host smart-36947589-c2fe-4d15-a608-8879ec4273a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1737365494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.1737365494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.1659669677
Short name T712
Test name
Test status
Simulation time 31202413 ps
CPU time 0.81 seconds
Started Aug 08 06:23:38 PM PDT 24
Finished Aug 08 06:23:39 PM PDT 24
Peak memory 205172 kb
Host smart-0adf90d2-d58c-4259-9cdd-43779deb8395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659669677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1659669677 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.3307200984
Short name T82
Test name
Test status
Simulation time 6539559411 ps
CPU time 193.97 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:26:48 PM PDT 24
Peak memory 376048 kb
Host smart-cb5ac446-6519-43ba-97a8-cb63d4d9cc46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307200984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3307200984 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3018755406
Short name T260
Test name
Test status
Simulation time 71771210249 ps
CPU time 329.65 seconds
Started Aug 08 06:23:43 PM PDT 24
Finished Aug 08 06:29:13 PM PDT 24
Peak memory 496724 kb
Host smart-15bc807d-d2dc-4831-96d3-df1f001e189e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018755406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.3018755406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.3749446223
Short name T620
Test name
Test status
Simulation time 15239319203 ps
CPU time 167.26 seconds
Started Aug 08 06:23:36 PM PDT 24
Finished Aug 08 06:26:23 PM PDT 24
Peak memory 226412 kb
Host smart-3a7ee90a-6a4a-4326-bc1e-a9731fd44ca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749446223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3749446223
+enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.14750898
Short name T744
Test name
Test status
Simulation time 1986792754 ps
CPU time 38.42 seconds
Started Aug 08 06:23:43 PM PDT 24
Finished Aug 08 06:24:22 PM PDT 24
Peak memory 223836 kb
Host smart-44f1e0f6-bea5-4ed5-855f-563663756fdd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=14750898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.14750898 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.3228854938
Short name T866
Test name
Test status
Simulation time 2290015248 ps
CPU time 21.22 seconds
Started Aug 08 06:23:31 PM PDT 24
Finished Aug 08 06:23:52 PM PDT 24
Peak memory 223788 kb
Host smart-94dc773c-7e97-4058-b2b3-bca97d84c923
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3228854938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3228854938 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.3322613355
Short name T650
Test name
Test status
Simulation time 11192791175 ps
CPU time 54.83 seconds
Started Aug 08 06:23:42 PM PDT 24
Finished Aug 08 06:24:36 PM PDT 24
Peak memory 218940 kb
Host smart-52621d2d-371f-44c9-9a28-09490c237117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322613355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3322613355 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.916841207
Short name T570
Test name
Test status
Simulation time 10098494901 ps
CPU time 36.52 seconds
Started Aug 08 06:23:32 PM PDT 24
Finished Aug 08 06:24:08 PM PDT 24
Peak memory 240736 kb
Host smart-d79532e5-3281-4c46-a3ff-cc32196a1681
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916841207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.916
841207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.4124683718
Short name T35
Test name
Test status
Simulation time 2079809677 ps
CPU time 151.76 seconds
Started Aug 08 06:23:45 PM PDT 24
Finished Aug 08 06:26:17 PM PDT 24
Peak memory 305752 kb
Host smart-f7017260-d147-4134-b138-735270347ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124683718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.4124683718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.429652657
Short name T68
Test name
Test status
Simulation time 138521293 ps
CPU time 1.75 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 06:23:37 PM PDT 24
Peak memory 217668 kb
Host smart-10e0d23e-5d63-4ef2-954a-1f5499c8b3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429652657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.429652657 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.2391375455
Short name T831
Test name
Test status
Simulation time 5420230860 ps
CPU time 10.74 seconds
Started Aug 08 06:23:37 PM PDT 24
Finished Aug 08 06:23:48 PM PDT 24
Peak memory 240340 kb
Host smart-73439a32-4962-4738-8030-5256f1a977d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391375455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2391375455 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.1036573939
Short name T826
Test name
Test status
Simulation time 1511338003 ps
CPU time 133.37 seconds
Started Aug 08 06:23:26 PM PDT 24
Finished Aug 08 06:25:39 PM PDT 24
Peak memory 302248 kb
Host smart-7ab683dc-4687-45e1-8143-c1ea7db628ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036573939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.1036573939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.3560183557
Short name T473
Test name
Test status
Simulation time 24482536200 ps
CPU time 300.7 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:28:33 PM PDT 24
Peak memory 500792 kb
Host smart-a393b17e-cce4-4c01-94f6-7e3d97c9fc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560183557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3560183557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.193976558
Short name T698
Test name
Test status
Simulation time 5320283145 ps
CPU time 162.57 seconds
Started Aug 08 06:23:39 PM PDT 24
Finished Aug 08 06:26:22 PM PDT 24
Peak memory 374516 kb
Host smart-14965820-c549-4c34-b6a3-3461a4c009cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193976558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.193976558 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.4243719790
Short name T562
Test name
Test status
Simulation time 6835946648 ps
CPU time 64.62 seconds
Started Aug 08 06:23:33 PM PDT 24
Finished Aug 08 06:24:37 PM PDT 24
Peak memory 222420 kb
Host smart-a3e882fc-6a1a-41fa-a8e5-98a51fce0729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243719790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.4243719790 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.600495345
Short name T703
Test name
Test status
Simulation time 23859535226 ps
CPU time 2320.24 seconds
Started Aug 08 06:23:35 PM PDT 24
Finished Aug 08 07:02:16 PM PDT 24
Peak memory 840404 kb
Host smart-7ad74940-3abb-4e36-bd0f-cd903e312e57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=600495345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.600495345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3395979445
Short name T499
Test name
Test status
Simulation time 632481045 ps
CPU time 4.77 seconds
Started Aug 08 06:23:53 PM PDT 24
Finished Aug 08 06:23:58 PM PDT 24
Peak memory 218144 kb
Host smart-532f8222-5af6-4ea4-8335-9a5aeaf4a550
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395979445 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3395979445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.818864800
Short name T921
Test name
Test status
Simulation time 473753069 ps
CPU time 4.99 seconds
Started Aug 08 06:23:34 PM PDT 24
Finished Aug 08 06:23:39 PM PDT 24
Peak memory 218000 kb
Host smart-4ea4c936-57dc-426e-9a9e-b4ac9eedf7a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818864800 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.kmac_test_vectors_kmac_xof.818864800 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.3700286018
Short name T405
Test name
Test status
Simulation time 37009642993 ps
CPU time 1780.48 seconds
Started Aug 08 06:23:42 PM PDT 24
Finished Aug 08 06:53:23 PM PDT 24
Peak memory 1175100 kb
Host smart-33ba5f99-81d4-41aa-ab45-b13d74b8e4e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3700286018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.3700286018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.248106197
Short name T167
Test name
Test status
Simulation time 179927429744 ps
CPU time 2774.41 seconds
Started Aug 08 06:23:45 PM PDT 24
Finished Aug 08 07:10:00 PM PDT 24
Peak memory 3055636 kb
Host smart-d533a553-4f4b-4df8-bf05-0c070de40ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=248106197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.248106197 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3007925818
Short name T785
Test name
Test status
Simulation time 49564598556 ps
CPU time 1889.69 seconds
Started Aug 08 06:23:49 PM PDT 24
Finished Aug 08 06:55:19 PM PDT 24
Peak memory 2397268 kb
Host smart-13d9e262-0845-4e4a-bd2a-188e52b22e6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3007925818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3007925818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.2725365989
Short name T937
Test name
Test status
Simulation time 9364671632 ps
CPU time 878.5 seconds
Started Aug 08 06:23:51 PM PDT 24
Finished Aug 08 06:38:29 PM PDT 24
Peak memory 684008 kb
Host smart-e4657bcf-3218-4c43-ab76-7af7c0d56430
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2725365989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.2725365989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.2044533929
Short name T764
Test name
Test status
Simulation time 462787940188 ps
CPU time 5408.99 seconds
Started Aug 08 06:23:29 PM PDT 24
Finished Aug 08 07:53:39 PM PDT 24
Peak memory 2694888 kb
Host smart-9a2d2aaf-b63c-4a48-82fe-70fcaa60df51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2044533929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.2044533929 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest
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