Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81590119	1			T1	280		T2	330		T3	16332
all_values[1]	81590119	1			T1	280		T2	330		T3	16332
all_values[2]	81590119	1			T1	280		T2	330		T3	16332

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

474779

1

T2

9

T3

936

T13

7

auto[1]

244295578

1

T1

840

T2

981

T3

48060

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243550707

1

T1

798

T2

951

T3

48525

auto[1]

1219650

1

T1

42

T2

39

T3

471

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	186202	1			T2	7		T13	3		T14	17
all_values[0]	auto[0]	auto[1]	2052	1			T2	2		T13	4		T14	4
all_values[0]	auto[1]	auto[0]	80997367	1			T1	266		T2	310		T3	16175
all_values[0]	auto[1]	auto[1]	404498	1			T1	14		T2	11		T3	157
all_values[1]	auto[0]	auto[0]	143525	1			T3	463		T14	8		T16	944
all_values[1]	auto[0]	auto[1]	1408	1			T3	5		T14	2		T16	2
all_values[1]	auto[1]	auto[0]	81040044	1			T1	266		T2	317		T3	15712
all_values[1]	auto[1]	auto[1]	405142	1			T1	14		T2	13		T3	152
all_values[2]	auto[0]	auto[0]	140110	1			T3	463		T14	8		T15	1
all_values[2]	auto[0]	auto[1]	1482	1			T3	5		T14	2		T15	2
all_values[2]	auto[1]	auto[0]	81043459	1			T1	266		T2	317		T3	15712
all_values[2]	auto[1]	auto[1]	405068	1			T1	14		T2	13		T3	152