Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.63 96.17 92.75 66.52 65.15 93.39 99.79


Total modules in report: 54
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tlul_err_resp 57.14 71.43 50.00 50.00
keccak_round 74.39 65.98 100.00 26.67 79.31 100.00
kmac_app 80.49 90.99 84.93 40.00 86.52 100.00
keccak_2share 81.25 100.00 75.00 50.00 100.00
kmac_staterd 90.00 100.00 70.00 100.00
  prim_intr_hw 90.35 95.00 76.39 90.00 100.00
kmac 91.19 96.27 93.33 63.67 100.00 93.85 100.00
kmac_errchk 92.60 96.83 96.67 73.33 96.15 100.00
  prim_fifo_sync 93.36 100.00 73.44 100.00 100.00
  tlul_adapter_sram 93.71 98.58 80.12 96.15 100.00
sha3pad 93.83 99.38 88.37 85.71 95.70 100.00
sha3 94.14 97.56 88.89 90.91 93.33 100.00
kmac_core 94.46 98.55 92.86 100.00 92.00 88.89
prim_arbiter_fixed 95.05 87.50 92.68 100.00 100.00
  prim_fifo_sync_cnt 95.33 96.00 90.00 100.00
  tlul_rsp_intg_gen 95.83 91.67 100.00
prim_subreg_shadow 97.12 100.00 88.46 100.00 100.00
tlul_socket_1n 97.25 100.00 93.33 95.65 100.00
prim_packer 97.50 100.00 100.00 90.00 100.00
kmac_msgfifo 97.92 100.00 100.00 91.67 100.00
tlul_adapter_reg 98.98 100.00 95.92 100.00 100.00
kmac_reg_top 99.90 100.00 99.60 100.00 100.00
prim_lc_sync 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
prim_sparse_fsm_flop 100.00 100.00 100.00
prim_count 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
sha3pad_assert_if 100.00 100.00
prim_mubi4_sender 100.00 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_onehot_check 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_slicer 100.00 100.00 100.00
  prim_subreg_arb 100.00 100.00 100.00 100.00
kmac_csr_assert_fpv 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_sram_byte 100.00 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb
prim_sec_anchor_buf