Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
259740 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
296000 |
1 |
|
|
T1 |
16 |
|
T2 |
16 |
|
T3 |
214 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
139508 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
48 |
lower_val |
138237 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T3 |
75 |
zero_val |
1639 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
278286 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
106 |
lower_val |
277442 |
1 |
|
|
T1 |
8 |
|
T2 |
8 |
|
T3 |
110 |
zero_val |
12 |
1 |
|
|
T158 |
2 |
|
T159 |
2 |
|
T160 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
32163 |
1 |
|
|
T14 |
12 |
|
T15 |
71 |
|
T16 |
1 |
higher_val |
higher_val |
auto[1] |
37668 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
25 |
higher_val |
lower_val |
auto[0] |
32376 |
1 |
|
|
T3 |
1 |
|
T14 |
14 |
|
T15 |
91 |
higher_val |
lower_val |
auto[1] |
37297 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
22 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T159 |
1 |
|
T161 |
1 |
|
T162 |
1 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T160 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
32459 |
1 |
|
|
T13 |
1 |
|
T14 |
8 |
|
T15 |
83 |
lower_val |
higher_val |
auto[1] |
36756 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
32 |
lower_val |
lower_val |
auto[0] |
32059 |
1 |
|
|
T14 |
8 |
|
T15 |
85 |
|
T18 |
49 |
lower_val |
lower_val |
auto[1] |
36960 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
43 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T162 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T160 |
1 |
|
T163 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
623 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
197 |
1 |
|
|
T24 |
1 |
|
T96 |
2 |
|
T97 |
2 |
zero_val |
lower_val |
auto[0] |
594 |
1 |
|
|
T3 |
1 |
|
T14 |
1 |
|
T15 |
1 |
zero_val |
lower_val |
auto[1] |
225 |
1 |
|
|
T96 |
4 |
|
T158 |
3 |
|
T164 |
1 |