Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	9559133	1			T1	261		T2	311		T3	13830
shake	38325656	1			T3	3802		T13	466917		T14	41
sha3	35362915	1			T3	74		T14	51		T15	208051

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73687515

1

T3

3876

T13

466917

T14

92

auto[1]

9560189

1

T1

261

T2

311

T3

13830

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	81856795	1			T1	261		T2	310		T3	17672
depth[0x01]	904383	1			T2	1		T3	34		T13	7867
depth[0x02]	157129	1			T17	8		T18	1		T42	10
depth[0x03]	128681	1			T17	8		T42	9		T44	9
depth[0x04]	81753	1			T17	8		T42	6		T44	4
depth[0x05]	49227	1			T17	6		T42	2		T44	1
depth[0x06]	19092	1			T50	1429		T51	1030		T52	223
depth[0x07]	467	1			T52	9		T172	51		T183	16
depth[0x08]	1571	1			T50	127		T51	94		T52	19
depth[0x09]	1502	1			T50	54		T51	46		T52	21
depth[0x0a]	47104	1			T50	3000		T51	2206		T52	655

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1390909

1

T2

1

T3

34

T13

7867

auto[1]

81856795

1

T1

261

T2

310

T3

17672

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83200600

1

T1

261

T2

311

T3

17706

auto[1]

47104

1

T50

3000

T51

2206

T52

655