Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81590119	1			T1	280		T2	330		T3	16332
all_pins[1]	81590119	1			T1	280		T2	330		T3	16332
all_pins[2]	81590119	1			T1	280		T2	330		T3	16332

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	244096043	1			T1	826		T2	979		T3	48839
values[0x1]	674314	1			T1	14		T2	11		T3	157
transitions[0x0=>0x1]	672659	1			T1	14		T2	11		T3	157
transitions[0x1=>0x0]	672687	1			T1	14		T2	11		T3	157

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	81185621	1			T1	266		T2	319		T3	16175
all_pins[0]	values[0x1]	404498	1			T1	14		T2	11		T3	157
all_pins[0]	transitions[0x0=>0x1]	404488	1			T1	14		T2	11		T3	157
all_pins[0]	transitions[0x1=>0x0]	65	1			T51	4		T172	4		T173	2
all_pins[1]	values[0x0]	81590044	1			T1	280		T2	330		T3	16332
all_pins[1]	values[0x1]	75	1			T51	4		T172	4		T173	2
all_pins[1]	transitions[0x0=>0x1]	64	1			T51	4		T172	4		T173	2
all_pins[1]	transitions[0x1=>0x0]	269730	1			T24	8455		T28	1240		T25	4705
all_pins[2]	values[0x0]	81320378	1			T1	280		T2	330		T3	16332
all_pins[2]	values[0x1]	269741	1			T24	8455		T28	1240		T25	4705
all_pins[2]	transitions[0x0=>0x1]	268107	1			T24	8400		T28	1239		T25	4672
all_pins[2]	transitions[0x1=>0x0]	402892	1			T1	14		T2	11		T3	157