Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	607	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5265	1			T3	13		T16	17		T18	35
len_601_800	11999	1			T3	45		T16	37		T18	75
len_401_600	7913	1			T3	20		T16	22		T18	45
len_201_400	15967	1			T3	16		T13	251		T16	8
len_65_200	54011	1			T3	8		T13	680		T14	25
len_min_for_xof_require_squeeze	740	1			T13	10		T89	1		T96	10
len_keccak_block_sizes[72]	504	1			T3	1		T13	5		T18	1
len_keccak_block_sizes[104]	489	1			T13	5		T96	5		T158	9
len_keccak_block_sizes[136]	478	1			T13	5		T89	1		T96	5
len_keccak_block_sizes[144]	280	1			T13	5		T24	1		T89	1
len_keccak_block_sizes[168]	285	1			T13	5		T89	1		T96	5
len_datapath_width	13703	1			T1	3		T2	3		T13	5
len_2_63	167118	1			T1	6		T2	6		T3	3
len_1	53	1			T14	1		T89	1		T25	1