Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	210254807	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

169448740

1

T1

42510

T2

1412

T3

359383

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	200386894	1			T1	45898		T2	1167		T3	464651
values[0x0]	86255535	1			T1	11580		T2	537		T3	213752
values[0x1]	93061118	1			T1	12267		T2	543		T3	232041

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	163941881	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

215761666

1

T1

48576

T2

1615

T3

479467

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1127802	1			T1	16		T3	3633		T12	29
valid_sources[0x01]	2940683	1			T1	17		T3	3459		T12	34
valid_sources[0x02]	1136155	1			T1	24		T3	3592		T12	34
valid_sources[0x03]	1129311	1			T1	20		T3	3600		T12	44
valid_sources[0x04]	1127149	1			T1	23		T3	3576		T12	32
valid_sources[0x05]	1131425	1			T1	10		T3	3571		T12	36
valid_sources[0x06]	1145815	1			T1	19		T3	3532		T12	26
valid_sources[0x07]	1131954	1			T1	20		T3	3477		T12	39
valid_sources[0x08]	1127016	1			T1	19		T3	3440		T12	29
valid_sources[0x09]	1592751	1			T1	14		T3	3627		T12	31
valid_sources[0x0a]	1130473	1			T1	15		T3	3550		T12	32
valid_sources[0x0b]	1980326	1			T1	23		T3	3550		T12	42
valid_sources[0x0c]	1136038	1			T1	16		T3	3616		T12	31
valid_sources[0x0d]	1150104	1			T1	17		T3	3543		T12	27
valid_sources[0x0e]	1138685	1			T1	16		T3	3445		T12	31
valid_sources[0x0f]	1591433	1			T1	21		T3	3544		T12	46
valid_sources[0x10]	1132772	1			T1	11		T3	3675		T12	24
valid_sources[0x11]	1264520	1			T1	11		T3	3579		T12	23
valid_sources[0x12]	1125837	1			T1	25		T3	3498		T12	41
valid_sources[0x13]	5700590	1			T1	18		T3	3567		T12	32
valid_sources[0x14]	1198631	1			T1	15		T3	3705		T12	29
valid_sources[0x15]	1164390	1			T1	12		T3	3568		T12	30
valid_sources[0x16]	1133206	1			T1	11		T3	3592		T12	32
valid_sources[0x17]	1252389	1			T1	26		T3	3632		T12	23
valid_sources[0x18]	1131489	1			T1	21		T3	3681		T12	39
valid_sources[0x19]	1839217	1			T1	17		T3	3561		T12	32
valid_sources[0x1a]	2936608	1			T1	18		T3	3523		T12	38
valid_sources[0x1b]	1195395	1			T1	21		T3	3682		T12	41
valid_sources[0x1c]	1127947	1			T1	19		T3	3490		T12	28
valid_sources[0x1d]	1128473	1			T1	14		T3	3500		T12	40
valid_sources[0x1e]	1202078	1			T1	12		T3	3563		T12	36
valid_sources[0x1f]	1130539	1			T1	21		T3	3600		T12	36
valid_sources[0x20]	1201352	1			T1	65059		T3	3563		T12	36
valid_sources[0x21]	1630499	1			T1	21		T3	3379		T12	38
valid_sources[0x22]	4025088	1			T1	25		T3	3507		T12	40
valid_sources[0x23]	1289066	1			T1	23		T3	3564		T12	31
valid_sources[0x24]	1135567	1			T1	16		T3	3519		T12	40
valid_sources[0x25]	3017151	1			T1	16		T3	3542		T12	42
valid_sources[0x26]	1130490	1			T1	17		T3	3509		T12	39
valid_sources[0x27]	1583402	1			T1	17		T3	3424		T12	49
valid_sources[0x28]	1158322	1			T1	20		T3	3490		T12	36
valid_sources[0x29]	1129261	1			T1	14		T3	3525		T12	35
valid_sources[0x2a]	2056580	1			T1	19		T3	3499		T12	36
valid_sources[0x2b]	1134745	1			T1	25		T3	3545		T12	32
valid_sources[0x2c]	1129509	1			T1	24		T3	3510		T12	43
valid_sources[0x2d]	1148602	1			T1	20		T3	3521		T12	24
valid_sources[0x2e]	1186519	1			T1	23		T3	3577		T12	37
valid_sources[0x2f]	2039384	1			T1	17		T3	3516		T12	31
valid_sources[0x30]	1140768	1			T1	22		T3	3671		T12	37
valid_sources[0x31]	1800725	1			T1	18		T3	3532		T12	35
valid_sources[0x32]	1803248	1			T1	21		T3	3528		T12	34
valid_sources[0x33]	1132143	1			T1	20		T3	3537		T12	41
valid_sources[0x34]	1125543	1			T1	13		T3	3639		T12	46
valid_sources[0x35]	1133782	1			T1	13		T3	3518		T12	40
valid_sources[0x36]	1128467	1			T1	25		T3	3584		T12	25
valid_sources[0x37]	1135477	1			T1	22		T3	3509		T12	35
valid_sources[0x38]	1130016	1			T1	15		T3	3564		T12	38
valid_sources[0x39]	1457130	1			T1	19		T3	3537		T12	36
valid_sources[0x3a]	1123497	1			T1	13		T3	3541		T12	31
valid_sources[0x3b]	3085890	1			T1	21		T3	3577		T12	32
valid_sources[0x3c]	1129239	1			T1	22		T3	3440		T12	44
valid_sources[0x3d]	1130492	1			T1	16		T3	3581		T12	28
valid_sources[0x3e]	1161616	1			T1	25		T3	3514		T12	39
valid_sources[0x3f]	1124597	1			T1	17		T3	3352		T12	34
valid_sources[0x40]	1128712	1			T1	15		T3	3498		T12	31
valid_sources[0x41]	1260292	1			T1	18		T3	3526		T12	34
valid_sources[0x42]	1287668	1			T1	23		T3	3529		T12	36
valid_sources[0x43]	1128771	1			T1	14		T3	3609		T12	29
valid_sources[0x44]	1138281	1			T1	22		T3	3521		T12	42
valid_sources[0x45]	1128836	1			T1	23		T3	3660		T12	28
valid_sources[0x46]	1290452	1			T1	13		T3	3475		T12	33
valid_sources[0x47]	1131814	1			T1	27		T3	3478		T12	31
valid_sources[0x48]	1125934	1			T1	21		T3	3440		T12	37
valid_sources[0x49]	1180481	1			T1	15		T3	3467		T12	39
valid_sources[0x4a]	1134707	1			T1	20		T3	3555		T12	43
valid_sources[0x4b]	2068134	1			T1	9		T3	3632		T12	31
valid_sources[0x4c]	1809886	1			T1	22		T3	3569		T12	39
valid_sources[0x4d]	3160622	1			T1	23		T3	3416		T12	35
valid_sources[0x4e]	1129485	1			T1	26		T3	3533		T12	28
valid_sources[0x4f]	1128650	1			T1	14		T3	3576		T12	40
valid_sources[0x50]	1179375	1			T1	20		T3	3629		T12	37
valid_sources[0x51]	1133700	1			T1	20		T3	3398		T12	36
valid_sources[0x52]	1132764	1			T1	22		T3	3582		T12	39
valid_sources[0x53]	1140339	1			T1	18		T3	3566		T12	34
valid_sources[0x54]	3633413	1			T1	18		T3	3555		T12	30
valid_sources[0x55]	1129714	1			T1	13		T3	3560		T12	38
valid_sources[0x56]	1133258	1			T1	20		T3	3523		T12	42
valid_sources[0x57]	1148415	1			T1	20		T3	3582		T12	45
valid_sources[0x58]	1129202	1			T1	22		T3	3592		T12	41
valid_sources[0x59]	2052584	1			T1	22		T3	3562		T12	42
valid_sources[0x5a]	1130755	1			T1	11		T3	3540		T12	39
valid_sources[0x5b]	1197732	1			T1	14		T3	3650		T12	34
valid_sources[0x5c]	1165018	1			T1	17		T3	3500		T12	39
valid_sources[0x5d]	1141240	1			T1	12		T3	3589		T12	40
valid_sources[0x5e]	1134895	1			T1	20		T3	3425		T12	24
valid_sources[0x5f]	3151122	1			T1	23		T3	3572		T12	29
valid_sources[0x60]	1135257	1			T1	21		T3	3566		T12	32
valid_sources[0x61]	1134027	1			T1	27		T3	3677		T12	33
valid_sources[0x62]	1134582	1			T1	13		T3	3559		T12	33
valid_sources[0x63]	1158283	1			T1	18		T3	3522		T12	31
valid_sources[0x64]	1133917	1			T1	25		T3	3540		T12	43
valid_sources[0x65]	1136538	1			T1	20		T3	3419		T12	35
valid_sources[0x66]	1151744	1			T1	18		T3	3681		T12	34
valid_sources[0x67]	1775736	1			T1	28		T3	3474		T12	35
valid_sources[0x68]	1164739	1			T1	11		T3	3652		T12	25
valid_sources[0x69]	3151891	1			T1	21		T3	3614		T12	32
valid_sources[0x6a]	1132826	1			T1	16		T3	3660		T12	36
valid_sources[0x6b]	1140919	1			T1	16		T3	3588		T12	38
valid_sources[0x6c]	1129030	1			T1	24		T3	3608		T12	31
valid_sources[0x6d]	1280472	1			T1	18		T3	3633		T12	36
valid_sources[0x6e]	1771952	1			T1	24		T3	3574		T12	47
valid_sources[0x6f]	1145291	1			T1	24		T3	3656		T12	46
valid_sources[0x70]	1126752	1			T1	24		T3	3604		T12	38
valid_sources[0x71]	2070720	1			T1	22		T3	3566		T12	28
valid_sources[0x72]	3226865	1			T1	20		T3	3666		T12	39
valid_sources[0x73]	2055987	1			T1	16		T3	3481		T12	21
valid_sources[0x74]	1145184	1			T1	20		T3	3568		T12	49
valid_sources[0x75]	1698868	1			T1	24		T3	3541		T12	41
valid_sources[0x76]	1913506	1			T1	14		T3	3608		T12	31
valid_sources[0x77]	1466426	1			T1	22		T3	3545		T12	35
valid_sources[0x78]	1130564	1			T1	22		T3	3607		T12	19
valid_sources[0x79]	1143302	1			T1	23		T3	3526		T12	33
valid_sources[0x7a]	1136479	1			T1	18		T3	3560		T12	28
valid_sources[0x7b]	1136538	1			T1	16		T3	3602		T12	31
valid_sources[0x7c]	3146766	1			T1	19		T3	3678		T12	28
valid_sources[0x7d]	2070219	1			T1	18		T3	3533		T12	25
valid_sources[0x7e]	1163783	1			T1	20		T3	3485		T12	48
valid_sources[0x7f]	1338963	1			T1	15		T3	3569		T12	39
valid_sources[0x80]	2011337	1			T1	14		T3	3495		T12	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73906642

1

T1

29588

T2

722

T3

133033

values[0x0]

all_enables

biggest_size

51304531

1

T1

7011

T2

378

T3

122171

values[0x1]

all_enables

biggest_size

44237567

1

T1

5911

T2

312

T3

104179