Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

210474927

1

T1

27235

T2

835

T3

551061

full_word

169462370

1

T1

42510

T2

1412

T3

359383

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	379937007	1			T1	69745		T2	2247		T3	910444
auto[TlIntgErrCmd]	100	1			T113	6		T114	3		T115	4
auto[TlIntgErrData]	93	1			T113	4		T114	6		T115	4
auto[TlIntgErrBoth]	97	1			T113	10		T114	1		T115	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200439908

1

T1

45898

T2

1167

T3

464651

auto[1]

179497389

1

T1

23847

T2

1080

T3

445793

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	126529144	1			T1	16310		T2	445		T3	331618
auto[TlIntgErrNone]	partial	auto[1]	83945518	1			T1	10925		T2	390		T3	219443
auto[TlIntgErrNone]	full_word	auto[0]	73910641	1			T1	29588		T2	722		T3	133033
auto[TlIntgErrNone]	full_word	auto[1]	95551704	1			T1	12922		T2	690		T3	226350
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T113	3		T114	1		T115	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T113	3		T114	2		T115	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T175	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T128	1		T176	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T113	3		T114	2		T115	1
auto[TlIntgErrData]	partial	auto[1]	49	1			T113	1		T114	4		T115	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T177	1		T174	1		T175	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T127	2		T178	1		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T113	5		T127	2		T128	3
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T113	3		T114	1		T115	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T113	1		T177	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T113	1		T178	1		T176	1