Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2100490494	38612	0	0
entropy_period_rd_A	2100490494	1380	0	0
intr_enable_rd_A	2100490494	2080	0	0
prefix_0_rd_A	2100490494	1530	0	0
prefix_10_rd_A	2100490494	1604	0	0
prefix_1_rd_A	2100490494	1465	0	0
prefix_2_rd_A	2100490494	1552	0	0
prefix_3_rd_A	2100490494	1479	0	0
prefix_4_rd_A	2100490494	1495	0	0
prefix_5_rd_A	2100490494	1538	0	0
prefix_6_rd_A	2100490494	1396	0	0
prefix_7_rd_A	2100490494	1365	0	0
prefix_8_rd_A	2100490494	1580	0	0
prefix_9_rd_A	2100490494	1512	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	38612	0	0
T7	1284	0	0	0
T26	114994	0	0	0
T53	156397	0	0	0
T60	281460	19896	0	0
T61	0	15213	0	0
T62	0	166	0	0
T113	0	2	0	0
T114	0	1	0	0
T115	0	2	0	0
T122	0	41	0	0
T123	0	111	0	0
T127	0	4	0	0
T128	0	2	0	0
T130	475952	0	0	0
T131	17055	0	0	0
T132	164635	0	0	0
T133	496375	0	0	0
T134	61958	0	0	0
T135	40129	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1380	0	0
T93	11083	38	0	0
T94	2620	6	0	0
T115	12500	45	0	0
T137	20654	63	0	0
T148	6473	21	0	0
T149	1609	3	0	0
T150	43805	241	0	0
T151	11193	31	0	0
T152	144271	211	0	0
T153	22922	126	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	2080	0	0
T115	12500	35	0	0
T117	1292	10	0	0
T137	20654	57	0	0
T148	6473	15	0	0
T149	1609	3	0	0
T150	43805	227	0	0
T154	1125	10	0	0
T155	854	13	0	0
T156	1816	6	0	0
T157	2009	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1530	0	0
T93	11083	34	0	0
T94	2620	9	0	0
T115	12500	17	0	0
T124	5734	1	0	0
T137	20654	42	0	0
T148	6473	50	0	0
T150	43805	238	0	0
T151	11193	74	0	0
T152	144271	442	0	0
T153	22922	96	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1604	0	0
T93	11083	39	0	0
T94	2620	10	0	0
T115	12500	18	0	0
T137	20654	60	0	0
T148	6473	19	0	0
T149	1609	3	0	0
T150	43805	256	0	0
T151	11193	59	0	0
T152	144271	456	0	0
T156	1816	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1465	0	0
T93	11083	19	0	0
T94	2620	10	0	0
T115	12500	15	0	0
T137	20654	31	0	0
T148	6473	16	0	0
T149	1609	6	0	0
T150	43805	269	0	0
T151	11193	16	0	0
T152	144271	444	0	0
T153	22922	71	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1552	0	0
T93	11083	24	0	0
T94	2620	14	0	0
T115	12500	20	0	0
T137	20654	71	0	0
T148	6473	15	0	0
T149	1609	2	0	0
T150	43805	264	0	0
T151	11193	48	0	0
T152	144271	460	0	0
T153	22922	78	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1479	0	0
T93	11083	12	0	0
T94	2620	14	0	0
T115	12500	27	0	0
T137	20654	42	0	0
T148	6473	41	0	0
T149	1609	10	0	0
T150	43805	211	0	0
T151	11193	49	0	0
T152	144271	482	0	0
T153	22922	56	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1495	0	0
T93	11083	20	0	0
T94	2620	3	0	0
T115	12500	19	0	0
T137	20654	42	0	0
T148	6473	34	0	0
T149	1609	9	0	0
T150	43805	199	0	0
T151	11193	60	0	0
T156	1816	4	0	0
T158	6329	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1538	0	0
T93	11083	30	0	0
T94	2620	10	0	0
T115	12500	19	0	0
T137	20654	28	0	0
T148	6473	33	0	0
T150	43805	243	0	0
T151	11193	37	0	0
T152	144271	466	0	0
T153	22922	88	0	0
T156	1816	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1396	0	0
T93	11083	23	0	0
T94	2620	3	0	0
T98	5310	24	0	0
T115	12500	25	0	0
T137	20654	33	0	0
T148	6473	40	0	0
T150	43805	223	0	0
T151	11193	14	0	0
T152	144271	451	0	0
T153	22922	73	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1365	0	0
T93	11083	23	0	0
T94	2620	7	0	0
T115	12500	15	0	0
T137	20654	47	0	0
T148	6473	35	0	0
T149	1609	1	0	0
T150	43805	191	0	0
T151	11193	22	0	0
T152	144271	418	0	0
T156	1816	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1580	0	0
T93	11083	16	0	0
T94	2620	10	0	0
T115	12500	14	0	0
T137	20654	36	0	0
T148	6473	46	0	0
T149	1609	1	0	0
T150	43805	196	0	0
T151	11193	69	0	0
T152	144271	447	0	0
T156	1816	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100490494	1512	0	0
T93	11083	15	0	0
T94	2620	13	0	0
T98	5310	18	0	0
T115	12500	26	0	0
T137	20654	56	0	0
T148	6473	11	0	0
T150	43805	263	0	0
T151	11193	81	0	0
T152	144271	465	0	0
T153	22922	84	0	0