Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	227830816	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

180996002

1

T1

100329

T2

36697

T3

203764

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	215959431	1			T1	126808		T2	41875		T3	59308
values[0x0]	92745113	1			T1	549497		T2	9915		T3	79234
values[0x1]	100122274	1			T1	594704		T2	10793		T3	79982

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	177644786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

231182032

1

T1

131234

T2

42815

T3

207545

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1197774	1			T1	9335		T2	240		T3	784
valid_sources[0x01]	1271152	1			T1	9508		T2	240		T3	497
valid_sources[0x02]	1588177	1			T1	9436		T2	269		T3	534
valid_sources[0x03]	1869697	1			T1	9470		T2	228		T3	595
valid_sources[0x04]	1194538	1			T1	9343		T2	254		T3	602
valid_sources[0x05]	1194596	1			T1	9535		T2	263		T3	1312
valid_sources[0x06]	1191325	1			T1	9391		T2	249		T3	669
valid_sources[0x07]	1840397	1			T1	9489		T2	228		T3	1257
valid_sources[0x08]	1392758	1			T1	9702		T2	259		T3	611
valid_sources[0x09]	1655826	1			T1	9385		T2	259		T3	587
valid_sources[0x0a]	1685396	1			T1	9452		T2	254		T3	1046
valid_sources[0x0b]	1189627	1			T1	9399		T2	239		T3	1194
valid_sources[0x0c]	1190401	1			T1	9388		T2	231		T3	633
valid_sources[0x0d]	2389368	1			T1	9324		T2	229		T3	1090
valid_sources[0x0e]	2528253	1			T1	9370		T2	260		T3	578
valid_sources[0x0f]	1189700	1			T1	9441		T2	208		T3	2000
valid_sources[0x10]	1194944	1			T1	9391		T2	229		T3	647
valid_sources[0x11]	1203448	1			T1	9545		T2	235		T3	3184
valid_sources[0x12]	1193896	1			T1	9446		T2	221		T3	1170
valid_sources[0x13]	1193782	1			T1	9211		T2	254		T3	545
valid_sources[0x14]	1196656	1			T1	9420		T2	271		T3	706
valid_sources[0x15]	1224427	1			T1	9535		T2	230		T3	530
valid_sources[0x16]	1192123	1			T1	9479		T2	254		T3	1413
valid_sources[0x17]	3685667	1			T1	9325		T2	240		T3	621
valid_sources[0x18]	1196424	1			T1	9596		T2	277		T3	1142
valid_sources[0x19]	2054921	1			T1	9532		T2	249		T3	573
valid_sources[0x1a]	1219796	1			T1	9180		T2	238		T3	1121
valid_sources[0x1b]	2044655	1			T1	9511		T2	228		T3	657
valid_sources[0x1c]	3238536	1			T1	9453		T2	219		T3	720
valid_sources[0x1d]	3767527	1			T1	9460		T2	243		T3	564
valid_sources[0x1e]	1206755	1			T1	9502		T2	260		T3	698
valid_sources[0x1f]	1194353	1			T1	9376		T2	242		T3	1361
valid_sources[0x20]	2134588	1			T1	9364		T2	219		T3	1393
valid_sources[0x21]	1845054	1			T1	9362		T2	257		T3	610
valid_sources[0x22]	1190093	1			T1	9370		T2	215		T3	823
valid_sources[0x23]	1231943	1			T1	9367		T2	234		T3	655
valid_sources[0x24]	1841526	1			T1	9511		T2	244		T3	563
valid_sources[0x25]	1885660	1			T1	9430		T2	262		T3	659
valid_sources[0x26]	1199096	1			T1	9364		T2	241		T3	975
valid_sources[0x27]	1187602	1			T1	9428		T2	273		T3	1977
valid_sources[0x28]	1188965	1			T1	9541		T2	241		T3	651
valid_sources[0x29]	1190113	1			T1	9474		T2	234		T3	641
valid_sources[0x2a]	1854701	1			T1	9526		T2	252		T3	575
valid_sources[0x2b]	1194442	1			T1	9377		T2	255		T3	750
valid_sources[0x2c]	1192950	1			T1	9224		T2	206		T3	2030
valid_sources[0x2d]	2191136	1			T1	9310		T2	230		T3	2567
valid_sources[0x2e]	1195483	1			T1	9582		T2	248		T3	1838
valid_sources[0x2f]	3267623	1			T1	9672		T2	216		T3	1275
valid_sources[0x30]	1197487	1			T1	9349		T2	280		T3	587
valid_sources[0x31]	1191756	1			T1	9404		T2	235		T3	472
valid_sources[0x32]	2128866	1			T1	9361		T2	246		T3	560
valid_sources[0x33]	1190114	1			T1	9468		T2	274		T3	1134
valid_sources[0x34]	1317503	1			T1	9283		T2	251		T3	577
valid_sources[0x35]	2121583	1			T1	9486		T2	253		T3	591
valid_sources[0x36]	1200830	1			T1	9357		T2	243		T3	909
valid_sources[0x37]	1191082	1			T1	9481		T2	230		T3	592
valid_sources[0x38]	2097009	1			T1	9579		T2	260		T3	1349
valid_sources[0x39]	1189612	1			T1	9327		T2	226		T3	1194
valid_sources[0x3a]	1223078	1			T1	9378		T2	233		T3	2037
valid_sources[0x3b]	1194565	1			T1	9427		T2	214		T3	682
valid_sources[0x3c]	1187303	1			T1	9534		T2	207		T3	1294
valid_sources[0x3d]	1608573	1			T1	9506		T2	238		T3	1198
valid_sources[0x3e]	1227386	1			T1	9343		T2	219		T3	653
valid_sources[0x3f]	1228914	1			T1	9446		T2	264		T3	980
valid_sources[0x40]	1869211	1			T1	9361		T2	253		T3	634
valid_sources[0x41]	1193320	1			T1	9416		T2	242		T3	1495
valid_sources[0x42]	4108794	1			T1	9443		T2	238		T3	582
valid_sources[0x43]	1517018	1			T1	9311		T2	242		T3	1170
valid_sources[0x44]	1208724	1			T1	9470		T2	261		T3	828
valid_sources[0x45]	1193445	1			T1	9307		T2	250		T3	630
valid_sources[0x46]	1193461	1			T1	9486		T2	257		T3	702
valid_sources[0x47]	1206046	1			T1	9428		T2	254		T3	1761
valid_sources[0x48]	2665212	1			T1	9512		T2	253		T3	723
valid_sources[0x49]	1196895	1			T1	9573		T2	240		T3	668
valid_sources[0x4a]	1752613	1			T1	9609		T2	226		T3	1379
valid_sources[0x4b]	1193228	1			T1	9407		T2	231		T3	1464
valid_sources[0x4c]	1858412	1			T1	9305		T2	233		T3	969
valid_sources[0x4d]	1192166	1			T1	9351		T2	242		T3	617
valid_sources[0x4e]	1195341	1			T1	9410		T2	217		T3	571
valid_sources[0x4f]	1236129	1			T1	9229		T2	247		T3	593
valid_sources[0x50]	1190200	1			T1	9329		T2	239		T3	674
valid_sources[0x51]	1268997	1			T1	9256		T2	246		T3	696
valid_sources[0x52]	1198783	1			T1	9467		T2	258		T3	693
valid_sources[0x53]	3699720	1			T1	9164		T2	251		T3	686
valid_sources[0x54]	3201144	1			T1	9495		T2	247		T3	688
valid_sources[0x55]	1364467	1			T1	9294		T2	225		T3	586
valid_sources[0x56]	1192884	1			T1	9590		T2	239		T3	568
valid_sources[0x57]	1192539	1			T1	9380		T2	236		T3	499
valid_sources[0x58]	1195428	1			T1	9284		T2	248		T3	642
valid_sources[0x59]	1189283	1			T1	9355		T2	243		T3	835
valid_sources[0x5a]	1193872	1			T1	9512		T2	274		T3	629
valid_sources[0x5b]	1350511	1			T1	9712		T2	250		T3	800
valid_sources[0x5c]	1193454	1			T1	9398		T2	239		T3	676
valid_sources[0x5d]	1856374	1			T1	9325		T2	242		T3	1328
valid_sources[0x5e]	1382293	1			T1	9373		T2	245		T3	650
valid_sources[0x5f]	1412447	1			T1	9451		T2	236		T3	572
valid_sources[0x60]	2130383	1			T1	9564		T2	230		T3	641
valid_sources[0x61]	2099840	1			T1	9410		T2	262		T3	604
valid_sources[0x62]	2950242	1			T1	9561		T2	252		T3	1956
valid_sources[0x63]	1192160	1			T1	9297		T2	290		T3	655
valid_sources[0x64]	1275041	1			T1	9521		T2	226		T3	679
valid_sources[0x65]	3604731	1			T1	9320		T2	241		T3	644
valid_sources[0x66]	1192766	1			T1	9484		T2	265		T3	794
valid_sources[0x67]	3219941	1			T1	9342		T2	248		T3	629
valid_sources[0x68]	1197195	1			T1	9271		T2	243		T3	784
valid_sources[0x69]	1206013	1			T1	9620		T2	242		T3	551
valid_sources[0x6a]	4365479	1			T1	9607		T2	236		T3	575
valid_sources[0x6b]	1212433	1			T1	9501		T2	238		T3	636
valid_sources[0x6c]	1194926	1			T1	9535		T2	259		T3	816
valid_sources[0x6d]	1204887	1			T1	9290		T2	260		T3	668
valid_sources[0x6e]	1454776	1			T1	9733		T2	221		T3	591
valid_sources[0x6f]	1807739	1			T1	9441		T2	233		T3	624
valid_sources[0x70]	1300419	1			T1	9535		T2	226		T3	651
valid_sources[0x71]	2057606	1			T1	9320		T2	257		T3	575
valid_sources[0x72]	1197732	1			T1	9386		T2	262		T3	1248
valid_sources[0x73]	1207625	1			T1	9520		T2	257		T3	609
valid_sources[0x74]	1195401	1			T1	9171		T2	226		T3	580
valid_sources[0x75]	1368448	1			T1	9602		T2	247		T3	616
valid_sources[0x76]	1228060	1			T1	9445		T2	240		T3	1128
valid_sources[0x77]	2066690	1			T1	9332		T2	230		T3	955
valid_sources[0x78]	2152594	1			T1	9480		T2	243		T3	1354
valid_sources[0x79]	3689000	1			T1	9247		T2	233		T3	1144
valid_sources[0x7a]	1190445	1			T1	9549		T2	255		T3	608
valid_sources[0x7b]	1196524	1			T1	9331		T2	247		T3	650
valid_sources[0x7c]	1948749	1			T1	9418		T2	243		T3	568
valid_sources[0x7d]	1194840	1			T1	9395		T2	246		T3	695
valid_sources[0x7e]	2382166	1			T1	9468		T2	225		T3	726
valid_sources[0x7f]	1864686	1			T1	9442		T2	244		T3	668
valid_sources[0x80]	1205306	1			T1	9400		T2	255		T3	707

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79072045

1

T1

426331

T2

25869

T3

46797

values[0x0]

all_enables

biggest_size

54801774

1

T1

312735

T2

5830

T3

78292

values[0x1]

all_enables

biggest_size

47122183

1

T1

264232

T2

4998

T3

78675