Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

228091918

1

T1

140899

T2

25886

T3

14760

full_word

181012156

1

T1

100329

T2

36697

T3

203764

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	409103744	1			T1	241228		T2	62583		T3	218524
auto[TlIntgErrCmd]	106	1			T124	5		T125	3		T126	4
auto[TlIntgErrData]	107	1			T124	8		T125	1		T126	9
auto[TlIntgErrBoth]	117	1			T124	7		T125	6		T126	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

216020678

1

T1

126808

T2

41875

T3

59308

auto[1]

193083396

1

T1

114420

T2

20708

T3

159216

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	136943849	1			T1	841757		T2	16006		T3	12511
auto[TlIntgErrNone]	partial	auto[1]	91147775	1			T1	567234		T2	9880		T3	2249
auto[TlIntgErrNone]	full_word	auto[0]	79076683	1			T1	426331		T2	25869		T3	46797
auto[TlIntgErrNone]	full_word	auto[1]	101935437	1			T1	576967		T2	10828		T3	156967
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T124	2		T125	1		T126	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T124	3		T125	2		T126	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T182	1		T185	1		T186	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T182	1		T187	1		T188	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T124	4		T126	4		T182	3
auto[TlIntgErrData]	partial	auto[1]	44	1			T124	3		T125	1		T126	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T124	1		T126	2		T185	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T126	1		T187	1		T186	2
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T124	1		T125	1		T126	3
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T124	4		T125	5		T126	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T187	2		T189	1		T190	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T124	2		T126	1		T181	1