Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	45881	0	0
entropy_period_rd_A	2147483647	2410	0	0
intr_enable_rd_A	2147483647	3671	0	0
prefix_0_rd_A	2147483647	2728	0	0
prefix_10_rd_A	2147483647	2640	0	0
prefix_1_rd_A	2147483647	2609	0	0
prefix_2_rd_A	2147483647	2604	0	0
prefix_3_rd_A	2147483647	2690	0	0
prefix_4_rd_A	2147483647	2779	0	0
prefix_5_rd_A	2147483647	2623	0	0
prefix_6_rd_A	2147483647	2685	0	0
prefix_7_rd_A	2147483647	2778	0	0
prefix_8_rd_A	2147483647	2728	0	0
prefix_9_rd_A	2147483647	2596	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45881	0	0
T55	262171	15847	0	0
T56	0	27261	0	0
T57	0	121	0	0
T64	3591	0	0	0
T123	0	231	0	0
T133	0	6	0	0
T134	0	45	0	0
T138	0	6	0	0
T139	0	4	0	0
T140	0	3	0	0
T142	0	8	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2410	0	0
T55	262171	64	0	0
T64	3591	0	0	0
T108	0	11	0	0
T138	0	18	0	0
T139	0	23	0	0
T142	0	16	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	265	0	0
T157	0	2	0	0
T158	0	14	0	0
T159	0	1	0	0
T160	0	205	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3671	0	0
T55	262171	68	0	0
T64	3591	0	0	0
T108	0	2	0	0
T138	0	26	0	0
T139	0	6	0	0
T142	0	26	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	236	0	0
T157	0	1	0	0
T158	0	14	0	0
T161	0	18	0	0
T162	0	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2728	0	0
T55	262171	55	0	0
T64	3591	0	0	0
T108	0	11	0	0
T138	0	24	0	0
T139	0	14	0	0
T142	0	10	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	261	0	0
T157	0	10	0	0
T158	0	6	0	0
T159	0	49	0	0
T160	0	461	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2640	0	0
T55	262171	26	0	0
T64	3591	0	0	0
T108	0	8	0	0
T138	0	22	0	0
T139	0	19	0	0
T142	0	15	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	181	0	0
T157	0	7	0	0
T158	0	13	0	0
T159	0	9	0	0
T160	0	474	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2609	0	0
T55	262171	36	0	0
T64	3591	0	0	0
T108	0	10	0	0
T125	0	13	0	0
T138	0	17	0	0
T139	0	14	0	0
T142	0	25	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	210	0	0
T157	0	4	0	0
T159	0	14	0	0
T160	0	467	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2604	0	0
T55	262171	55	0	0
T64	3591	0	0	0
T108	0	8	0	0
T138	0	9	0	0
T139	0	16	0	0
T142	0	14	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	211	0	0
T157	0	16	0	0
T158	0	6	0	0
T159	0	35	0	0
T160	0	439	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2690	0	0
T55	262171	67	0	0
T64	3591	0	0	0
T108	0	15	0	0
T125	0	35	0	0
T138	0	20	0	0
T139	0	8	0	0
T142	0	17	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	189	0	0
T157	0	4	0	0
T159	0	14	0	0
T160	0	449	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2779	0	0
T55	262171	29	0	0
T64	3591	0	0	0
T108	0	4	0	0
T138	0	16	0	0
T139	0	15	0	0
T142	0	14	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	233	0	0
T157	0	5	0	0
T158	0	7	0	0
T159	0	28	0	0
T160	0	482	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2623	0	0
T55	262171	58	0	0
T64	3591	0	0	0
T108	0	3	0	0
T138	0	14	0	0
T139	0	13	0	0
T142	0	17	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	217	0	0
T157	0	15	0	0
T158	0	6	0	0
T159	0	1	0	0
T160	0	489	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2685	0	0
T55	262171	65	0	0
T64	3591	0	0	0
T108	0	1	0	0
T125	0	16	0	0
T138	0	17	0	0
T139	0	18	0	0
T142	0	14	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	204	0	0
T157	0	14	0	0
T159	0	46	0	0
T160	0	418	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2778	0	0
T55	262171	46	0	0
T64	3591	0	0	0
T108	0	9	0	0
T138	0	29	0	0
T139	0	6	0	0
T142	0	12	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	225	0	0
T157	0	8	0	0
T158	0	8	0	0
T159	0	18	0	0
T160	0	439	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2728	0	0
T55	262171	37	0	0
T64	3591	0	0	0
T108	0	5	0	0
T138	0	12	0	0
T139	0	12	0	0
T142	0	20	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	193	0	0
T157	0	5	0	0
T158	0	8	0	0
T159	0	43	0	0
T160	0	491	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2596	0	0
T55	262171	39	0	0
T64	3591	0	0	0
T108	0	10	0	0
T138	0	10	0	0
T139	0	15	0	0
T142	0	13	0	0
T143	125247	0	0	0
T144	329933	0	0	0
T145	938263	0	0	0
T146	20204	0	0	0
T147	155772	0	0	0
T148	7317	0	0	0
T149	33145	0	0	0
T150	1423	0	0	0
T156	0	221	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	0	38	0	0
T160	0	439	0	0