Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42283546

1

T1

40713

T2

282607

T3

43670

full_word

51075033

1

T1

67527

T2

170231

T3

69036

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	93358279	1			T1	108240		T2	452838		T3	112706
auto[TlIntgErrCmd]	106	1			T103	6		T104	8		T106	6
auto[TlIntgErrData]	94	1			T103	11		T104	5		T106	3
auto[TlIntgErrBoth]	100	1			T103	3		T104	7		T106	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50188922

1

T1

75403

T2

229289

T3

74195

auto[1]

43169657

1

T1

32837

T2

223549

T3

38511

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26065273	1			T1	26015		T2	166967		T3	26102
auto[TlIntgErrNone]	partial	auto[1]	16217995	1			T1	14698		T2	115640		T3	17568
auto[TlIntgErrNone]	full_word	auto[0]	24123518	1			T1	49388		T2	62322		T3	48093
auto[TlIntgErrNone]	full_word	auto[1]	26951493	1			T1	18139		T2	107909		T3	20943
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T103	1		T104	6		T106	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T103	3		T104	2		T106	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T103	1		T106	1		T157	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T103	1		T158	1		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1			T103	4		T104	3		T106	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T103	6		T104	2		T106	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T155	1		T159	1		T160	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T103	1		T123	1		T154	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T103	2		T104	4		T106	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T103	1		T104	3		T123	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T154	1		T152	1		T155	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T154	1		T152	1		T161	1