Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	521156924	3113	0	0
entropy_period_rd_A	521156924	1552	0	0
intr_enable_rd_A	521156924	2477	0	0
prefix_0_rd_A	521156924	1281	0	0
prefix_10_rd_A	521156924	1353	0	0
prefix_1_rd_A	521156924	1523	0	0
prefix_2_rd_A	521156924	1229	0	0
prefix_3_rd_A	521156924	1350	0	0
prefix_4_rd_A	521156924	1296	0	0
prefix_5_rd_A	521156924	1317	0	0
prefix_6_rd_A	521156924	1410	0	0
prefix_7_rd_A	521156924	1260	0	0
prefix_8_rd_A	521156924	1357	0	0
prefix_9_rd_A	521156924	1392	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	3113	0	0
T49	2896	68	0	0
T50	2619	69	0	0
T103	24367	1	0	0
T106	12923	2	0	0
T107	2220	3	0	0
T108	4898	258	0	0
T109	11697	157	0	0
T119	3765	103	0	0
T123	5029	1	0	0
T125	4154	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1552	0	0
T48	4550	2	0	0
T91	10530	43	0	0
T93	5099	29	0	0
T96	9631	21	0	0
T103	24367	115	0	0
T106	12923	69	0	0
T135	1827	1	0	0
T136	2480	9	0	0
T137	9912	26	0	0
T138	6089	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	2477	0	0
T48	4550	18	0	0
T91	10530	25	0	0
T93	5099	14	0	0
T103	24367	185	0	0
T106	12923	94	0	0
T113	1481	8	0	0
T135	1827	8	0	0
T136	2480	26	0	0
T137	9912	30	0	0
T139	1086	11	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1281	0	0
T48	4550	6	0	0
T91	10530	19	0	0
T93	5099	26	0	0
T96	9631	17	0	0
T103	24367	77	0	0
T106	12923	38	0	0
T136	2480	9	0	0
T137	9912	25	0	0
T138	6089	8	0	0
T140	2689	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1353	0	0
T48	4550	6	0	0
T91	10530	24	0	0
T93	5099	20	0	0
T96	9631	21	0	0
T103	24367	77	0	0
T106	12923	46	0	0
T136	2480	8	0	0
T137	9912	37	0	0
T138	6089	8	0	0
T140	2689	12	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1523	0	0
T48	4550	2	0	0
T91	10530	26	0	0
T93	5099	20	0	0
T96	9631	35	0	0
T103	24367	85	0	0
T106	12923	29	0	0
T135	1827	5	0	0
T136	2480	10	0	0
T137	9912	25	0	0
T138	6089	39	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1229	0	0
T48	4550	7	0	0
T91	10530	22	0	0
T93	5099	31	0	0
T96	9631	36	0	0
T103	24367	66	0	0
T106	12923	33	0	0
T135	1827	2	0	0
T136	2480	2	0	0
T137	9912	12	0	0
T138	6089	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1350	0	0
T48	4550	6	0	0
T91	10530	18	0	0
T93	5099	11	0	0
T96	9631	15	0	0
T103	24367	78	0	0
T106	12923	49	0	0
T136	2480	3	0	0
T137	9912	20	0	0
T138	6089	15	0	0
T140	2689	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1296	0	0
T48	4550	13	0	0
T91	10530	21	0	0
T93	5099	15	0	0
T96	9631	22	0	0
T103	24367	93	0	0
T106	12923	45	0	0
T135	1827	3	0	0
T136	2480	8	0	0
T137	9912	15	0	0
T138	6089	13	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1317	0	0
T48	4550	10	0	0
T91	10530	21	0	0
T93	5099	29	0	0
T96	9631	26	0	0
T103	24367	78	0	0
T106	12923	37	0	0
T136	2480	8	0	0
T137	9912	16	0	0
T138	6089	17	0	0
T140	2689	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1410	0	0
T48	4550	8	0	0
T91	10530	53	0	0
T93	5099	16	0	0
T96	9631	32	0	0
T103	24367	90	0	0
T106	12923	58	0	0
T135	1827	3	0	0
T136	2480	5	0	0
T137	9912	10	0	0
T138	6089	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1260	0	0
T48	4550	9	0	0
T91	10530	33	0	0
T93	5099	13	0	0
T96	9631	25	0	0
T103	24367	52	0	0
T106	12923	36	0	0
T135	1827	5	0	0
T136	2480	3	0	0
T137	9912	20	0	0
T138	6089	11	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1357	0	0
T48	4550	5	0	0
T91	10530	30	0	0
T93	5099	22	0	0
T96	9631	33	0	0
T103	24367	80	0	0
T106	12923	48	0	0
T136	2480	12	0	0
T137	9912	1	0	0
T138	6089	3	0	0
T140	2689	10	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521156924	1392	0	0
T48	4550	5	0	0
T91	10530	27	0	0
T93	5099	10	0	0
T96	9631	13	0	0
T103	24367	100	0	0
T106	12923	47	0	0
T135	1827	8	0	0
T136	2480	8	0	0
T137	9912	44	0	0
T138	6089	4	0	0