Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15628559	1			T1	287422		T5	4		T15	1585
all_values[1]	15628559	1			T1	287422		T5	4		T15	1585
all_values[2]	15628559	1			T1	287422		T5	4		T15	1585

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

440801

1

T1

2274

T5

8

T15

20

auto[1]

46444876

1

T1

859992

T5

4

T15

4735

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46666329

1

T1

860364

T5

12

T15

4320

auto[1]

219348

1

T1

1902

T15

435

T16

336

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	152455	1			T1	509		T5	4		T15	8
all_values[0]	auto[0]	auto[1]	1254	1			T1	18		T15	2		T17	2
all_values[0]	auto[1]	auto[0]	15402988	1			T1	286279		T15	1432		T16	668
all_values[0]	auto[1]	auto[1]	71862	1			T1	616		T15	143		T16	112
all_values[1]	auto[0]	auto[0]	154733	1			T1	406		T17	5		T18	224
all_values[1]	auto[0]	auto[1]	975	1			T1	10		T17	2		T18	1
all_values[1]	auto[1]	auto[0]	15400710	1			T1	286382		T5	4		T15	1440
all_values[1]	auto[1]	auto[1]	72141	1			T1	624		T15	145		T16	112
all_values[2]	auto[0]	auto[0]	130481	1			T1	1320		T5	4		T15	8
all_values[2]	auto[0]	auto[1]	903	1			T1	11		T15	2		T16	4
all_values[2]	auto[1]	auto[0]	15424962	1			T1	285468		T15	1432		T16	642
all_values[2]	auto[1]	auto[1]	72213	1			T1	623		T15	143		T16	108