Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 61688 | 1 |  |  | T1 | 404 |  | T5 | 2 |  | T15 | 2 | 
| auto[1] | 49874 | 1 |  |  | T1 | 558 |  | T15 | 190 |  | T17 | 70 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 28114 | 1 |  |  | T1 | 242 |  | T5 | 1 |  | T15 | 44 | 
| lower_val | 27506 | 1 |  |  | T1 | 220 |  | T15 | 49 |  | T16 | 39 | 
| zero_val | 872 | 1 |  |  | T1 | 11 |  | T5 | 1 |  | T15 | 1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 1 | 2 | 66.67 | 
User Defined Bins for wait_timer_val
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| zero_val | 0 | 1 | 1 |  | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 55804 | 1 |  |  | T1 | 480 |  | T15 | 92 |  | T16 | 78 | 
| lower_val | 55758 | 1 |  |  | T1 | 482 |  | T5 | 2 |  | T15 | 100 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 18 | 6 | 12 | 66.67 | 6 | 
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| * | [zero_val] | * | -- | -- | 6 |  | 
Covered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | higher_val | auto[0] | 7712 | 1 |  |  | T1 | 41 |  | T16 | 14 |  | T18 | 45 | 
| higher_val | higher_val | auto[1] | 6342 | 1 |  |  | T1 | 80 |  | T15 | 22 |  | T17 | 4 | 
| higher_val | lower_val | auto[0] | 7772 | 1 |  |  | T1 | 44 |  | T5 | 1 |  | T16 | 14 | 
| higher_val | lower_val | auto[1] | 6288 | 1 |  |  | T1 | 77 |  | T15 | 22 |  | T17 | 8 | 
| lower_val | higher_val | auto[0] | 7589 | 1 |  |  | T1 | 52 |  | T16 | 19 |  | T18 | 29 | 
| lower_val | higher_val | auto[1] | 6147 | 1 |  |  | T1 | 68 |  | T15 | 19 |  | T17 | 6 | 
| lower_val | lower_val | auto[0] | 7481 | 1 |  |  | T1 | 38 |  | T16 | 20 |  | T17 | 1 | 
| lower_val | lower_val | auto[1] | 6289 | 1 |  |  | T1 | 62 |  | T15 | 30 |  | T17 | 9 | 
| zero_val | higher_val | auto[0] | 336 | 1 |  |  | T1 | 3 |  | T16 | 1 |  | T18 | 1 | 
| zero_val | higher_val | auto[1] | 104 | 1 |  |  | T1 | 1 |  | T27 | 1 |  | T23 | 2 | 
| zero_val | lower_val | auto[0] | 351 | 1 |  |  | T1 | 4 |  | T5 | 1 |  | T15 | 1 | 
| zero_val | lower_val | auto[1] | 81 | 1 |  |  | T1 | 3 |  | T27 | 1 |  | T23 | 2 |