Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15628559	1			T1	287422		T5	4		T15	1585
all_pins[1]	15628559	1			T1	287422		T5	4		T15	1585
all_pins[2]	15628559	1			T1	287422		T5	4		T15	1585

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46516575	1			T1	848285		T5	12		T15	4612
values[0x1]	369102	1			T1	13981		T15	143		T16	112
transitions[0x0=>0x1]	367341	1			T1	13907		T15	143		T16	112
transitions[0x1=>0x0]	367361	1			T1	13907		T15	143		T16	112

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15556697	1			T1	286806		T5	4		T15	1442
all_pins[0]	values[0x1]	71862	1			T1	616		T15	143		T16	112
all_pins[0]	transitions[0x0=>0x1]	71852	1			T1	616		T15	143		T16	112
all_pins[0]	transitions[0x1=>0x0]	52	1			T64	3		T71	2		T177	2
all_pins[1]	values[0x0]	15628497	1			T1	287422		T5	4		T15	1585
all_pins[1]	values[0x1]	62	1			T64	3		T71	2		T177	2
all_pins[1]	transitions[0x0=>0x1]	50	1			T64	3		T71	2		T177	2
all_pins[1]	transitions[0x1=>0x0]	297166	1			T1	13365		T18	18361		T27	518
all_pins[2]	values[0x0]	15331381	1			T1	274057		T5	4		T15	1585
all_pins[2]	values[0x1]	297178	1			T1	13365		T18	18361		T27	518
all_pins[2]	transitions[0x0=>0x1]	295439	1			T1	13291		T18	18251		T27	518
all_pins[2]	transitions[0x1=>0x0]	70143	1			T1	542		T15	143		T16	112