Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58605 |
1 |
|
|
T1 |
515 |
|
T5 |
1 |
|
T15 |
94 |
auto[1] |
3452 |
1 |
|
|
T1 |
33 |
|
T3 |
1 |
|
T18 |
16 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
27435 |
1 |
|
|
T1 |
201 |
|
T15 |
21 |
|
T16 |
17 |
auto[1] |
34622 |
1 |
|
|
T1 |
347 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48680 |
1 |
|
|
T1 |
432 |
|
T15 |
94 |
|
T16 |
75 |
auto[1] |
13377 |
1 |
|
|
T1 |
116 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13377 |
1 |
|
|
T1 |
116 |
|
T3 |
1 |
|
T5 |
1 |
sw_kmac_invalid_sideload |
48680 |
1 |
|
|
T1 |
432 |
|
T15 |
94 |
|
T16 |
75 |
app_valid_sideload |
13377 |
1 |
|
|
T1 |
116 |
|
T3 |
1 |
|
T5 |
1 |
app_invalid_sideload |
48680 |
1 |
|
|
T1 |
432 |
|
T15 |
94 |
|
T16 |
75 |