Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6247903 |
1 |
|
|
T1 |
66707 |
|
T15 |
15614 |
|
T16 |
2660 |
auto[1] |
9587999 |
1 |
|
|
T1 |
98342 |
|
T15 |
22560 |
|
T16 |
5082 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15802697 |
1 |
|
|
T1 |
164753 |
|
T15 |
38101 |
|
T16 |
7693 |
triple_byte_access |
10945 |
1 |
|
|
T1 |
115 |
|
T15 |
25 |
|
T16 |
14 |
halfword_access |
11124 |
1 |
|
|
T1 |
86 |
|
T15 |
23 |
|
T16 |
16 |
byte_access |
11136 |
1 |
|
|
T1 |
95 |
|
T15 |
25 |
|
T16 |
19 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6214698 |
1 |
|
|
T1 |
66411 |
|
T15 |
15541 |
|
T16 |
2611 |
auto[0] |
triple_byte_access |
10945 |
1 |
|
|
T1 |
115 |
|
T15 |
25 |
|
T16 |
14 |
auto[0] |
halfword_access |
11124 |
1 |
|
|
T1 |
86 |
|
T15 |
23 |
|
T16 |
16 |
auto[0] |
byte_access |
11136 |
1 |
|
|
T1 |
95 |
|
T15 |
25 |
|
T16 |
19 |
auto[1] |
word_access |
9587999 |
1 |
|
|
T1 |
98342 |
|
T15 |
22560 |
|
T16 |
5082 |