Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 281 1 T126 7 T127 4 T170 7
all_values[1] 281 1 T126 7 T127 4 T170 7
all_values[2] 281 1 T126 7 T127 4 T170 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 472 1 T126 9 T127 4 T170 15
auto[1] 371 1 T126 12 T127 8 T170 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 397 1 T126 8 T127 9 T170 11
auto[1] 446 1 T126 13 T127 3 T170 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 513 1 T126 10 T127 10 T170 12
auto[1] 330 1 T126 11 T127 2 T170 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 64 1 T126 1 T170 3 T171 1
all_values[0] auto[0] auto[0] auto[1] 32 1 T170 1 T156 3 T171 2
all_values[0] auto[0] auto[1] auto[0] 43 1 T127 2 T172 1 T158 1
all_values[0] auto[0] auto[1] auto[1] 30 1 T126 2 T127 1 T156 1
all_values[0] auto[1] auto[0] auto[1] 65 1 T126 3 T170 1 T156 3
all_values[0] auto[1] auto[1] auto[1] 47 1 T126 1 T127 1 T170 2
all_values[1] auto[0] auto[0] auto[0] 92 1 T126 1 T127 3 T170 1
all_values[1] auto[0] auto[1] auto[0] 76 1 T126 2 T170 2 T171 1
all_values[1] auto[1] auto[0] auto[1] 69 1 T126 2 T127 1 T170 3
all_values[1] auto[1] auto[1] auto[1] 44 1 T126 2 T170 1 T156 2
all_values[2] auto[0] auto[0] auto[0] 58 1 T126 1 T170 4 T156 1
all_values[2] auto[0] auto[0] auto[1] 24 1 T156 2 T157 1 T173 2
all_values[2] auto[0] auto[1] auto[0] 64 1 T126 3 T127 4 T170 1
all_values[2] auto[0] auto[1] auto[1] 30 1 T171 1 T174 1 T175 1
all_values[2] auto[1] auto[0] auto[1] 68 1 T126 1 T170 2 T156 2
all_values[2] auto[1] auto[1] auto[1] 37 1 T126 2 T156 1 T171 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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