Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.97 95.80 90.62 100.00 68.60 93.74 99.00 96.01


Total test records in report: 873
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T125 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2109863422 Aug 13 06:24:08 PM PDT 24 Aug 13 06:24:11 PM PDT 24 395508052 ps
T767 /workspace/coverage/cover_reg_top/12.kmac_intr_test.3615026548 Aug 13 06:23:57 PM PDT 24 Aug 13 06:23:58 PM PDT 24 226475418 ps
T182 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.4206545571 Aug 13 06:23:45 PM PDT 24 Aug 13 06:23:49 PM PDT 24 738237361 ps
T768 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4217824892 Aug 13 06:23:53 PM PDT 24 Aug 13 06:23:55 PM PDT 24 173479091 ps
T181 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2843811037 Aug 13 06:23:53 PM PDT 24 Aug 13 06:23:57 PM PDT 24 98487606 ps
T132 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2658067470 Aug 13 06:23:56 PM PDT 24 Aug 13 06:24:00 PM PDT 24 808018630 ps
T769 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1705436629 Aug 13 06:23:48 PM PDT 24 Aug 13 06:23:49 PM PDT 24 24318030 ps
T770 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2177898179 Aug 13 06:24:15 PM PDT 24 Aug 13 06:24:17 PM PDT 24 123024294 ps
T771 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1398983599 Aug 13 06:23:55 PM PDT 24 Aug 13 06:23:57 PM PDT 24 258475798 ps
T772 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3860456381 Aug 13 06:23:43 PM PDT 24 Aug 13 06:23:45 PM PDT 24 40969194 ps
T773 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.2547676017 Aug 13 06:23:41 PM PDT 24 Aug 13 06:23:45 PM PDT 24 948267601 ps
T774 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3655476861 Aug 13 06:23:47 PM PDT 24 Aug 13 06:23:49 PM PDT 24 468098168 ps
T131 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2333581765 Aug 13 06:23:28 PM PDT 24 Aug 13 06:23:31 PM PDT 24 145551286 ps
T775 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2947879205 Aug 13 06:24:13 PM PDT 24 Aug 13 06:24:15 PM PDT 24 53191704 ps
T776 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3707697782 Aug 13 06:23:55 PM PDT 24 Aug 13 06:23:57 PM PDT 24 56401633 ps
T777 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.4248883140 Aug 13 06:24:15 PM PDT 24 Aug 13 06:24:16 PM PDT 24 66526056 ps
T778 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3961696552 Aug 13 06:23:57 PM PDT 24 Aug 13 06:23:59 PM PDT 24 47775728 ps
T97 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3096494443 Aug 13 06:23:57 PM PDT 24 Aug 13 06:24:00 PM PDT 24 286558811 ps
T779 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2777555501 Aug 13 06:23:47 PM PDT 24 Aug 13 06:23:53 PM PDT 24 251237315 ps
T780 /workspace/coverage/cover_reg_top/19.kmac_intr_test.370201927 Aug 13 06:24:18 PM PDT 24 Aug 13 06:24:19 PM PDT 24 48135442 ps
T91 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2770179001 Aug 13 06:23:48 PM PDT 24 Aug 13 06:23:50 PM PDT 24 815117772 ps
T781 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.493031229 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:08 PM PDT 24 187619803 ps
T782 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.766681237 Aug 13 06:24:05 PM PDT 24 Aug 13 06:24:07 PM PDT 24 118058932 ps
T783 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1746101457 Aug 13 06:23:29 PM PDT 24 Aug 13 06:23:31 PM PDT 24 98334378 ps
T784 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2789354964 Aug 13 06:23:41 PM PDT 24 Aug 13 06:23:43 PM PDT 24 96832678 ps
T785 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3909019855 Aug 13 06:23:56 PM PDT 24 Aug 13 06:23:58 PM PDT 24 77041652 ps
T786 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4132647416 Aug 13 06:24:05 PM PDT 24 Aug 13 06:24:07 PM PDT 24 33954663 ps
T787 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.321160365 Aug 13 06:24:03 PM PDT 24 Aug 13 06:24:04 PM PDT 24 38692655 ps
T788 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2453435063 Aug 13 06:23:46 PM PDT 24 Aug 13 06:23:47 PM PDT 24 60853867 ps
T129 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2331304100 Aug 13 06:23:37 PM PDT 24 Aug 13 06:23:40 PM PDT 24 507513798 ps
T92 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3725822902 Aug 13 06:23:46 PM PDT 24 Aug 13 06:23:49 PM PDT 24 1030051271 ps
T789 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1448352291 Aug 13 06:23:35 PM PDT 24 Aug 13 06:23:50 PM PDT 24 301562966 ps
T790 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.646117033 Aug 13 06:23:32 PM PDT 24 Aug 13 06:23:34 PM PDT 24 58622505 ps
T791 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.744700799 Aug 13 06:23:58 PM PDT 24 Aug 13 06:24:01 PM PDT 24 691161665 ps
T792 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1979374117 Aug 13 06:24:00 PM PDT 24 Aug 13 06:24:02 PM PDT 24 107833304 ps
T793 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3949303059 Aug 13 06:23:41 PM PDT 24 Aug 13 06:23:50 PM PDT 24 3348194469 ps
T794 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1803403111 Aug 13 06:23:54 PM PDT 24 Aug 13 06:23:57 PM PDT 24 71281831 ps
T795 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.105685179 Aug 13 06:23:54 PM PDT 24 Aug 13 06:23:55 PM PDT 24 54451177 ps
T796 /workspace/coverage/cover_reg_top/38.kmac_intr_test.2859618145 Aug 13 06:24:18 PM PDT 24 Aug 13 06:24:19 PM PDT 24 43202378 ps
T797 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.890518293 Aug 13 06:24:05 PM PDT 24 Aug 13 06:24:06 PM PDT 24 19400159 ps
T798 /workspace/coverage/cover_reg_top/28.kmac_intr_test.977399836 Aug 13 06:24:16 PM PDT 24 Aug 13 06:24:17 PM PDT 24 39962422 ps
T799 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4013579925 Aug 13 06:23:48 PM PDT 24 Aug 13 06:23:49 PM PDT 24 58506581 ps
T800 /workspace/coverage/cover_reg_top/11.kmac_intr_test.2738076058 Aug 13 06:23:55 PM PDT 24 Aug 13 06:23:56 PM PDT 24 42297229 ps
T801 /workspace/coverage/cover_reg_top/40.kmac_intr_test.3056633075 Aug 13 06:24:17 PM PDT 24 Aug 13 06:24:18 PM PDT 24 35610610 ps
T802 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1489767762 Aug 13 06:24:14 PM PDT 24 Aug 13 06:24:16 PM PDT 24 78249318 ps
T803 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2270093883 Aug 13 06:23:37 PM PDT 24 Aug 13 06:23:40 PM PDT 24 298282590 ps
T804 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.228113289 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:08 PM PDT 24 119896386 ps
T805 /workspace/coverage/cover_reg_top/17.kmac_intr_test.1027190435 Aug 13 06:24:13 PM PDT 24 Aug 13 06:24:14 PM PDT 24 13692945 ps
T806 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3265604179 Aug 13 06:24:07 PM PDT 24 Aug 13 06:24:08 PM PDT 24 19881578 ps
T807 /workspace/coverage/cover_reg_top/6.kmac_intr_test.2946697921 Aug 13 06:23:45 PM PDT 24 Aug 13 06:23:46 PM PDT 24 25736926 ps
T808 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3213901419 Aug 13 06:23:48 PM PDT 24 Aug 13 06:23:49 PM PDT 24 32805270 ps
T809 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1637975310 Aug 13 06:23:40 PM PDT 24 Aug 13 06:23:55 PM PDT 24 286272785 ps
T810 /workspace/coverage/cover_reg_top/5.kmac_intr_test.778246037 Aug 13 06:23:48 PM PDT 24 Aug 13 06:23:48 PM PDT 24 28889961 ps
T811 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.114463275 Aug 13 06:23:29 PM PDT 24 Aug 13 06:23:31 PM PDT 24 114846912 ps
T812 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.4274452183 Aug 13 06:23:39 PM PDT 24 Aug 13 06:23:40 PM PDT 24 32491601 ps
T813 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2636498374 Aug 13 06:23:55 PM PDT 24 Aug 13 06:23:56 PM PDT 24 125575674 ps
T814 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3092481222 Aug 13 06:23:57 PM PDT 24 Aug 13 06:23:59 PM PDT 24 75819570 ps
T815 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1566965950 Aug 13 06:23:44 PM PDT 24 Aug 13 06:23:55 PM PDT 24 766661267 ps
T816 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.614453415 Aug 13 06:23:44 PM PDT 24 Aug 13 06:23:47 PM PDT 24 148653763 ps
T817 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2462588114 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:08 PM PDT 24 153602349 ps
T818 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3307667375 Aug 13 06:23:41 PM PDT 24 Aug 13 06:23:41 PM PDT 24 40477114 ps
T819 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2256823837 Aug 13 06:24:07 PM PDT 24 Aug 13 06:24:08 PM PDT 24 40403488 ps
T820 /workspace/coverage/cover_reg_top/39.kmac_intr_test.3475887564 Aug 13 06:24:18 PM PDT 24 Aug 13 06:24:19 PM PDT 24 15592096 ps
T821 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.852558558 Aug 13 06:23:40 PM PDT 24 Aug 13 06:23:49 PM PDT 24 279270403 ps
T822 /workspace/coverage/cover_reg_top/42.kmac_intr_test.2121424898 Aug 13 06:24:19 PM PDT 24 Aug 13 06:24:20 PM PDT 24 18812332 ps
T823 /workspace/coverage/cover_reg_top/9.kmac_intr_test.982252009 Aug 13 06:23:55 PM PDT 24 Aug 13 06:23:56 PM PDT 24 13350016 ps
T824 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2429447207 Aug 13 06:23:38 PM PDT 24 Aug 13 06:23:40 PM PDT 24 182307002 ps
T146 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1565437215 Aug 13 06:23:39 PM PDT 24 Aug 13 06:23:40 PM PDT 24 57549643 ps
T825 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1736420213 Aug 13 06:24:01 PM PDT 24 Aug 13 06:24:02 PM PDT 24 105827311 ps
T826 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3313341815 Aug 13 06:24:13 PM PDT 24 Aug 13 06:24:14 PM PDT 24 61058834 ps
T93 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1083757444 Aug 13 06:23:46 PM PDT 24 Aug 13 06:23:49 PM PDT 24 472290582 ps
T827 /workspace/coverage/cover_reg_top/45.kmac_intr_test.3271284476 Aug 13 06:24:15 PM PDT 24 Aug 13 06:24:16 PM PDT 24 12312777 ps
T828 /workspace/coverage/cover_reg_top/22.kmac_intr_test.376858298 Aug 13 06:24:14 PM PDT 24 Aug 13 06:24:15 PM PDT 24 30754415 ps
T179 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2780115938 Aug 13 06:23:55 PM PDT 24 Aug 13 06:23:58 PM PDT 24 190739110 ps
T829 /workspace/coverage/cover_reg_top/30.kmac_intr_test.2352697792 Aug 13 06:24:16 PM PDT 24 Aug 13 06:24:17 PM PDT 24 34947625 ps
T830 /workspace/coverage/cover_reg_top/44.kmac_intr_test.81753819 Aug 13 06:24:15 PM PDT 24 Aug 13 06:24:16 PM PDT 24 15694071 ps
T831 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3274649499 Aug 13 06:23:39 PM PDT 24 Aug 13 06:23:49 PM PDT 24 1483252341 ps
T832 /workspace/coverage/cover_reg_top/7.kmac_intr_test.3724825888 Aug 13 06:23:44 PM PDT 24 Aug 13 06:23:45 PM PDT 24 13465801 ps
T833 /workspace/coverage/cover_reg_top/34.kmac_intr_test.635862357 Aug 13 06:24:14 PM PDT 24 Aug 13 06:24:15 PM PDT 24 55894829 ps
T834 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.660001575 Aug 13 06:23:41 PM PDT 24 Aug 13 06:23:43 PM PDT 24 148234436 ps
T835 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2360880692 Aug 13 06:23:35 PM PDT 24 Aug 13 06:23:37 PM PDT 24 49940809 ps
T836 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.667402932 Aug 13 06:23:55 PM PDT 24 Aug 13 06:23:57 PM PDT 24 45102305 ps
T837 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.772343124 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:08 PM PDT 24 118017392 ps
T838 /workspace/coverage/cover_reg_top/16.kmac_intr_test.3252554535 Aug 13 06:24:04 PM PDT 24 Aug 13 06:24:05 PM PDT 24 44907117 ps
T134 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3524014490 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:08 PM PDT 24 282010844 ps
T839 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1628543932 Aug 13 06:23:41 PM PDT 24 Aug 13 06:23:43 PM PDT 24 67726050 ps
T840 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.771379245 Aug 13 06:24:03 PM PDT 24 Aug 13 06:24:05 PM PDT 24 70986316 ps
T841 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3290315984 Aug 13 06:23:43 PM PDT 24 Aug 13 06:23:45 PM PDT 24 38470322 ps
T842 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1904187274 Aug 13 06:23:45 PM PDT 24 Aug 13 06:23:49 PM PDT 24 228438554 ps
T180 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2112084346 Aug 13 06:23:40 PM PDT 24 Aug 13 06:23:44 PM PDT 24 444915756 ps
T843 /workspace/coverage/cover_reg_top/37.kmac_intr_test.942738682 Aug 13 06:24:15 PM PDT 24 Aug 13 06:24:16 PM PDT 24 55619727 ps
T95 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2701248429 Aug 13 06:24:04 PM PDT 24 Aug 13 06:24:05 PM PDT 24 73707305 ps
T844 /workspace/coverage/cover_reg_top/48.kmac_intr_test.2452917443 Aug 13 06:24:18 PM PDT 24 Aug 13 06:24:19 PM PDT 24 13910584 ps
T845 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.27751527 Aug 13 06:24:04 PM PDT 24 Aug 13 06:24:07 PM PDT 24 307041625 ps
T183 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3382525121 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:10 PM PDT 24 184131166 ps
T846 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.739639388 Aug 13 06:23:27 PM PDT 24 Aug 13 06:23:33 PM PDT 24 3778000331 ps
T847 /workspace/coverage/cover_reg_top/46.kmac_intr_test.2706767311 Aug 13 06:24:18 PM PDT 24 Aug 13 06:24:19 PM PDT 24 34746842 ps
T848 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.4248476571 Aug 13 06:24:15 PM PDT 24 Aug 13 06:24:17 PM PDT 24 38032127 ps
T849 /workspace/coverage/cover_reg_top/2.kmac_intr_test.1563038465 Aug 13 06:23:41 PM PDT 24 Aug 13 06:23:42 PM PDT 24 19629466 ps
T850 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3230295613 Aug 13 06:23:35 PM PDT 24 Aug 13 06:23:37 PM PDT 24 182198760 ps
T851 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1972998880 Aug 13 06:23:45 PM PDT 24 Aug 13 06:23:46 PM PDT 24 154613701 ps
T852 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2921242635 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:08 PM PDT 24 90636897 ps
T853 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.916907916 Aug 13 06:23:29 PM PDT 24 Aug 13 06:23:31 PM PDT 24 255861455 ps
T854 /workspace/coverage/cover_reg_top/33.kmac_intr_test.1288165858 Aug 13 06:24:16 PM PDT 24 Aug 13 06:24:17 PM PDT 24 15206964 ps
T855 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1850118478 Aug 13 06:23:27 PM PDT 24 Aug 13 06:23:28 PM PDT 24 50674888 ps
T856 /workspace/coverage/cover_reg_top/36.kmac_intr_test.1836607897 Aug 13 06:24:13 PM PDT 24 Aug 13 06:24:14 PM PDT 24 42283015 ps
T857 /workspace/coverage/cover_reg_top/49.kmac_intr_test.2005149774 Aug 13 06:24:17 PM PDT 24 Aug 13 06:24:18 PM PDT 24 21610332 ps
T858 /workspace/coverage/cover_reg_top/3.kmac_intr_test.3714423455 Aug 13 06:23:43 PM PDT 24 Aug 13 06:23:44 PM PDT 24 166264830 ps
T859 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4067329873 Aug 13 06:24:03 PM PDT 24 Aug 13 06:24:04 PM PDT 24 45208669 ps
T860 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3202790482 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:07 PM PDT 24 44396082 ps
T861 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2289656692 Aug 13 06:23:55 PM PDT 24 Aug 13 06:23:57 PM PDT 24 195397139 ps
T862 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2112674335 Aug 13 06:23:57 PM PDT 24 Aug 13 06:23:59 PM PDT 24 132567404 ps
T863 /workspace/coverage/cover_reg_top/0.kmac_intr_test.4221047460 Aug 13 06:23:27 PM PDT 24 Aug 13 06:23:28 PM PDT 24 26050384 ps
T864 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1511227514 Aug 13 06:23:34 PM PDT 24 Aug 13 06:23:36 PM PDT 24 95536207 ps
T865 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1006377565 Aug 13 06:23:29 PM PDT 24 Aug 13 06:23:30 PM PDT 24 15560020 ps
T866 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2095030272 Aug 13 06:23:44 PM PDT 24 Aug 13 06:23:47 PM PDT 24 354537184 ps
T867 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.653633283 Aug 13 06:23:39 PM PDT 24 Aug 13 06:23:40 PM PDT 24 22792038 ps
T868 /workspace/coverage/cover_reg_top/15.kmac_intr_test.3688477120 Aug 13 06:24:05 PM PDT 24 Aug 13 06:24:06 PM PDT 24 14740439 ps
T869 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3317841247 Aug 13 06:23:52 PM PDT 24 Aug 13 06:23:55 PM PDT 24 182965381 ps
T870 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.440750356 Aug 13 06:23:48 PM PDT 24 Aug 13 06:23:50 PM PDT 24 56782007 ps
T871 /workspace/coverage/cover_reg_top/8.kmac_intr_test.3404526372 Aug 13 06:23:42 PM PDT 24 Aug 13 06:23:43 PM PDT 24 25498617 ps
T872 /workspace/coverage/cover_reg_top/35.kmac_intr_test.3443670094 Aug 13 06:24:18 PM PDT 24 Aug 13 06:24:19 PM PDT 24 32801250 ps
T873 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1157631749 Aug 13 06:24:06 PM PDT 24 Aug 13 06:24:07 PM PDT 24 27792574 ps

Test location /workspace/coverage/default/21.kmac_stress_all.2413920997
Short name T1
Test name
Test status
Simulation time 139678275375 ps
CPU time 2814.98 seconds
Started Aug 13 05:56:28 PM PDT 24
Finished Aug 13 06:43:23 PM PDT 24
Peak memory 1155196 kb
Host smart-5892c5c7-2dc4-483a-9dfa-cbf4865b9543
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2413920997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2413920997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.945612467
Short name T47
Test name
Test status
Simulation time 255849857 ps
CPU time 5.24 seconds
Started Aug 13 06:24:05 PM PDT 24
Finished Aug 13 06:24:10 PM PDT 24
Peak memory 215064 kb
Host smart-44a51121-61ce-4167-ad9b-c2fa85c2243f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945612467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.94561
2467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.93051061
Short name T11
Test name
Test status
Simulation time 3116121370 ps
CPU time 53.08 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 05:56:09 PM PDT 24
Peak memory 254340 kb
Host smart-f3c2bb76-833c-4fc1-aab4-f52a1430e511
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93051061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.93051061 +enable_masking=0
+sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/7.kmac_key_error.1878482694
Short name T3
Test name
Test status
Simulation time 4250254010 ps
CPU time 5.5 seconds
Started Aug 13 05:55:30 PM PDT 24
Finished Aug 13 05:55:36 PM PDT 24
Peak memory 217772 kb
Host smart-ef6f46b6-b57f-4422-9365-0d1bd21d49dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878482694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1878482694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.727179884
Short name T5
Test name
Test status
Simulation time 208148816 ps
CPU time 1.26 seconds
Started Aug 13 05:55:40 PM PDT 24
Finished Aug 13 05:55:41 PM PDT 24
Peak memory 223596 kb
Host smart-9bd4489c-08bf-4aeb-b8ea-3e7fd9c12cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727179884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.727179884 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_error.2619760594
Short name T27
Test name
Test status
Simulation time 13040206734 ps
CPU time 297.71 seconds
Started Aug 13 05:59:02 PM PDT 24
Finished Aug 13 06:03:59 PM PDT 24
Peak memory 492240 kb
Host smart-0a471951-2e61-4253-812b-cb3fa8d8547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619760594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2619760594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.4288910769
Short name T114
Test name
Test status
Simulation time 130738634 ps
CPU time 3.24 seconds
Started Aug 13 06:24:10 PM PDT 24
Finished Aug 13 06:24:13 PM PDT 24
Peak memory 215068 kb
Host smart-f2b8f1b7-83d8-44fb-92a9-dd6e9d685aaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288910769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.4288910769 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.3868468736
Short name T8
Test name
Test status
Simulation time 45040426 ps
CPU time 1.35 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 05:57:03 PM PDT 24
Peak memory 218832 kb
Host smart-b6d30c50-66ab-4bd6-95ce-bb260ea411bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868468736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3868468736 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2655160292
Short name T126
Test name
Test status
Simulation time 15304408 ps
CPU time 0.77 seconds
Started Aug 13 06:24:16 PM PDT 24
Finished Aug 13 06:24:17 PM PDT 24
Peak memory 206488 kb
Host smart-f56a2834-9fb4-494a-887c-2cb756c47dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655160292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2655160292 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3725822902
Short name T92
Test name
Test status
Simulation time 1030051271 ps
CPU time 2.68 seconds
Started Aug 13 06:23:46 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 215476 kb
Host smart-d4e06cdb-3a1a-4518-9d4c-026cc1ef2849
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725822902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.3725822902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.351570638
Short name T709
Test name
Test status
Simulation time 56219255 ps
CPU time 1.58 seconds
Started Aug 13 05:55:02 PM PDT 24
Finished Aug 13 05:55:03 PM PDT 24
Peak memory 218900 kb
Host smart-78db2216-4fb8-41f1-b08c-4252858a5635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351570638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.351570638 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.796239603
Short name T50
Test name
Test status
Simulation time 51129783 ps
CPU time 1.4 seconds
Started Aug 13 05:55:47 PM PDT 24
Finished Aug 13 05:55:49 PM PDT 24
Peak memory 217124 kb
Host smart-e3f7a215-2d5e-414f-900f-e87c3810d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796239603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.796239603 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.3745778134
Short name T34
Test name
Test status
Simulation time 36656258 ps
CPU time 1.37 seconds
Started Aug 13 05:58:14 PM PDT 24
Finished Aug 13 05:58:16 PM PDT 24
Peak memory 219092 kb
Host smart-20bbf5d1-747f-4049-ba6e-d4a134dbcef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745778134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3745778134 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1249622820
Short name T82
Test name
Test status
Simulation time 175878128 ps
CPU time 1.35 seconds
Started Aug 13 06:23:53 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 215504 kb
Host smart-b25298c5-7e49-4f7e-9975-d40510c1aead
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249622820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.1249622820 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.kmac_alert_test.3837740865
Short name T110
Test name
Test status
Simulation time 49035369 ps
CPU time 0.82 seconds
Started Aug 13 05:54:55 PM PDT 24
Finished Aug 13 05:54:56 PM PDT 24
Peak memory 204832 kb
Host smart-9a7b40d0-4b5a-4348-b5e6-fa6473aec9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837740865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3837740865 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_stress_all.1899152643
Short name T23
Test name
Test status
Simulation time 25163715707 ps
CPU time 635.68 seconds
Started Aug 13 05:58:12 PM PDT 24
Finished Aug 13 06:08:48 PM PDT 24
Peak memory 593088 kb
Host smart-376c0451-9c14-48f6-adfe-ceb8ada1e63c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1899152643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1899152643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3003945281
Short name T144
Test name
Test status
Simulation time 25298138 ps
CPU time 1.12 seconds
Started Aug 13 06:23:28 PM PDT 24
Finished Aug 13 06:23:29 PM PDT 24
Peak memory 214992 kb
Host smart-4378bdc6-5040-400a-91e0-af95aa6c0b4a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003945281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3003945281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/39.kmac_smoke.2503690803
Short name T143
Test name
Test status
Simulation time 4191324719 ps
CPU time 43.13 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 05:59:22 PM PDT 24
Peak memory 219708 kb
Host smart-67f2a13a-3f09-41da-b5c6-c37fb4b1e7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503690803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2503690803 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1083757444
Short name T93
Test name
Test status
Simulation time 472290582 ps
CPU time 2.93 seconds
Started Aug 13 06:23:46 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 215508 kb
Host smart-23b75095-9c84-41b1-9124-58d62239a9e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083757444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.1083757444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.1340504000
Short name T756
Test name
Test status
Simulation time 45636076 ps
CPU time 0.74 seconds
Started Aug 13 06:24:05 PM PDT 24
Finished Aug 13 06:24:05 PM PDT 24
Peak memory 206528 kb
Host smart-c2d4df50-a278-43be-9584-61f23d93c512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340504000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1340504000 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/default/3.kmac_mubi.1646621062
Short name T18
Test name
Test status
Simulation time 20986442312 ps
CPU time 327.37 seconds
Started Aug 13 05:55:13 PM PDT 24
Finished Aug 13 06:00:41 PM PDT 24
Peak memory 487196 kb
Host smart-923c4bb5-7ba6-4f20-9638-aeca198e4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646621062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1646621062 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2333581765
Short name T131
Test name
Test status
Simulation time 145551286 ps
CPU time 2.85 seconds
Started Aug 13 06:23:28 PM PDT 24
Finished Aug 13 06:23:31 PM PDT 24
Peak memory 215120 kb
Host smart-d65e32c0-5360-4f59-b648-75139ff0773e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333581765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2333581765 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/default/20.kmac_stress_all.4036222213
Short name T67
Test name
Test status
Simulation time 29438577896 ps
CPU time 587.2 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 06:06:25 PM PDT 24
Peak memory 351888 kb
Host smart-18f42c72-7f3a-43f2-b741-81298529039d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4036222213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.4036222213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_error.2940679075
Short name T323
Test name
Test status
Simulation time 120074360421 ps
CPU time 376.83 seconds
Started Aug 13 05:57:41 PM PDT 24
Finished Aug 13 06:03:58 PM PDT 24
Peak memory 550832 kb
Host smart-dae7038c-fa5f-499f-a355-5485b53e2bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940679075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2940679075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.1774892995
Short name T56
Test name
Test status
Simulation time 307067248 ps
CPU time 2.46 seconds
Started Aug 13 05:55:19 PM PDT 24
Finished Aug 13 05:55:22 PM PDT 24
Peak memory 217308 kb
Host smart-aeac98b3-056a-484b-9916-64f41150ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774892995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1774892995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2331304100
Short name T129
Test name
Test status
Simulation time 507513798 ps
CPU time 2.82 seconds
Started Aug 13 06:23:37 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 207036 kb
Host smart-82dfd5c7-f261-417f-a618-ea8aba91a119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331304100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.23313
04100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2112084346
Short name T180
Test name
Test status
Simulation time 444915756 ps
CPU time 4.4 seconds
Started Aug 13 06:23:40 PM PDT 24
Finished Aug 13 06:23:44 PM PDT 24
Peak memory 215112 kb
Host smart-ce90cec6-c9c0-4544-984d-254390ef4644
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112084346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.21120
84346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/28.kmac_stress_all.4271164530
Short name T75
Test name
Test status
Simulation time 88105456330 ps
CPU time 593.16 seconds
Started Aug 13 05:57:05 PM PDT 24
Finished Aug 13 06:06:58 PM PDT 24
Peak memory 542776 kb
Host smart-13e86152-eef1-41f3-bb3e-f547fcdfec67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4271164530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.4271164530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2405446799
Short name T83
Test name
Test status
Simulation time 31312979 ps
CPU time 1.14 seconds
Started Aug 13 06:23:28 PM PDT 24
Finished Aug 13 06:23:29 PM PDT 24
Peak memory 215448 kb
Host smart-f7667a02-4d20-4b54-a8b0-95bd8b21c9a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405446799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2405446799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2843811037
Short name T181
Test name
Test status
Simulation time 98487606 ps
CPU time 3.96 seconds
Started Aug 13 06:23:53 PM PDT 24
Finished Aug 13 06:23:57 PM PDT 24
Peak memory 214964 kb
Host smart-28c0e783-e294-452f-880f-59b636a434a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843811037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.28438
11037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2109863422
Short name T125
Test name
Test status
Simulation time 395508052 ps
CPU time 2.51 seconds
Started Aug 13 06:24:08 PM PDT 24
Finished Aug 13 06:24:11 PM PDT 24
Peak memory 215048 kb
Host smart-34bd54e8-438c-4969-988d-1ba9d1d4b710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109863422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2109863422 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.2806457938
Short name T287
Test name
Test status
Simulation time 1658127810 ps
CPU time 16.79 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:55:13 PM PDT 24
Peak memory 217520 kb
Host smart-b20a39be-c8e0-44ef-91f4-4905b35652a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806457938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2806457938 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_error.3387679495
Short name T32
Test name
Test status
Simulation time 4306094583 ps
CPU time 206.2 seconds
Started Aug 13 05:55:00 PM PDT 24
Finished Aug 13 05:58:27 PM PDT 24
Peak memory 313808 kb
Host smart-7a2fe8ac-5582-40de-88a5-2657fcc0b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387679495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3387679495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.739639388
Short name T846
Test name
Test status
Simulation time 3778000331 ps
CPU time 6.34 seconds
Started Aug 13 06:23:27 PM PDT 24
Finished Aug 13 06:23:33 PM PDT 24
Peak memory 214920 kb
Host smart-9f47f0e0-f3b0-49a2-9d31-c41b8f970c5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739639388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.73963938
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1559705706
Short name T154
Test name
Test status
Simulation time 5699792550 ps
CPU time 18.37 seconds
Started Aug 13 06:23:29 PM PDT 24
Finished Aug 13 06:23:47 PM PDT 24
Peak memory 206780 kb
Host smart-3e48610b-87cf-47b2-a523-b078d8080cb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559705706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1559705
706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1850118478
Short name T855
Test name
Test status
Simulation time 50674888 ps
CPU time 0.94 seconds
Started Aug 13 06:23:27 PM PDT 24
Finished Aug 13 06:23:28 PM PDT 24
Peak memory 206524 kb
Host smart-821e7c88-7098-4d35-9527-9a19e995fa65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850118478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1850118
478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.114463275
Short name T811
Test name
Test status
Simulation time 114846912 ps
CPU time 1.79 seconds
Started Aug 13 06:23:29 PM PDT 24
Finished Aug 13 06:23:31 PM PDT 24
Peak memory 223144 kb
Host smart-4f868314-dbe7-406a-9437-7aad952de547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114463275 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.114463275 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2254537590
Short name T85
Test name
Test status
Simulation time 16642028 ps
CPU time 0.89 seconds
Started Aug 13 06:23:30 PM PDT 24
Finished Aug 13 06:23:31 PM PDT 24
Peak memory 206468 kb
Host smart-c3a0f3e3-adc6-4001-87de-82f48f17cac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254537590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2254537590 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.4221047460
Short name T863
Test name
Test status
Simulation time 26050384 ps
CPU time 0.79 seconds
Started Aug 13 06:23:27 PM PDT 24
Finished Aug 13 06:23:28 PM PDT 24
Peak memory 206504 kb
Host smart-6e7a5ca2-b7f2-43da-9280-0fbb89fec6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221047460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.4221047460 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2351324550
Short name T748
Test name
Test status
Simulation time 10895399 ps
CPU time 0.72 seconds
Started Aug 13 06:23:27 PM PDT 24
Finished Aug 13 06:23:28 PM PDT 24
Peak memory 206480 kb
Host smart-4db5a334-57ae-472a-a785-dedce8d5f66f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351324550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2351324550
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.916907916
Short name T853
Test name
Test status
Simulation time 255861455 ps
CPU time 1.88 seconds
Started Aug 13 06:23:29 PM PDT 24
Finished Aug 13 06:23:31 PM PDT 24
Peak memory 215276 kb
Host smart-3d3e5aad-e614-49e4-a8d2-b6082f23638b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916907916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_
outstanding.916907916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.847735126
Short name T118
Test name
Test status
Simulation time 908157002 ps
CPU time 1.94 seconds
Started Aug 13 06:23:30 PM PDT 24
Finished Aug 13 06:23:32 PM PDT 24
Peak memory 215104 kb
Host smart-d56f4406-cc1d-4a00-b847-3c756bfaf930
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847735126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_
shadow_reg_errors_with_csr_rw.847735126 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3119867617
Short name T178
Test name
Test status
Simulation time 203284699 ps
CPU time 2.4 seconds
Started Aug 13 06:23:29 PM PDT 24
Finished Aug 13 06:23:32 PM PDT 24
Peak memory 214992 kb
Host smart-7c573276-18f1-48bc-a92d-a11cd6ac9152
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119867617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.31198
67617 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3274649499
Short name T831
Test name
Test status
Simulation time 1483252341 ps
CPU time 9.94 seconds
Started Aug 13 06:23:39 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 206652 kb
Host smart-caa84055-0a47-4d2c-9b28-4c919e850d9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274649499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3274649
499 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1637975310
Short name T809
Test name
Test status
Simulation time 286272785 ps
CPU time 15.12 seconds
Started Aug 13 06:23:40 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 206776 kb
Host smart-0ed4e474-a6a8-4a29-b3f1-96d65a5859d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637975310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1637975
310 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1845338343
Short name T733
Test name
Test status
Simulation time 34796802 ps
CPU time 1.11 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:43 PM PDT 24
Peak memory 206176 kb
Host smart-a3a5bc9f-0c51-4a22-a622-b8345fa1a84a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845338343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1845338
343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4094714593
Short name T120
Test name
Test status
Simulation time 173018809 ps
CPU time 1.69 seconds
Started Aug 13 06:23:37 PM PDT 24
Finished Aug 13 06:23:39 PM PDT 24
Peak memory 215296 kb
Host smart-cde18177-f654-4b62-be09-6827167620a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094714593 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.4094714593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.653633283
Short name T867
Test name
Test status
Simulation time 22792038 ps
CPU time 0.95 seconds
Started Aug 13 06:23:39 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 206388 kb
Host smart-35236de3-7be5-4313-a8e6-72dc3151dc9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653633283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.653633283 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.1224263175
Short name T745
Test name
Test status
Simulation time 15290724 ps
CPU time 0.77 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:41 PM PDT 24
Peak memory 206540 kb
Host smart-b0506042-0511-4726-897e-65e0890189c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224263175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1224263175 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1746101457
Short name T783
Test name
Test status
Simulation time 98334378 ps
CPU time 1.4 seconds
Started Aug 13 06:23:29 PM PDT 24
Finished Aug 13 06:23:31 PM PDT 24
Peak memory 214964 kb
Host smart-94555c0a-c0b4-4171-9872-f2ea703651c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746101457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.1746101457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1006377565
Short name T865
Test name
Test status
Simulation time 15560020 ps
CPU time 0.72 seconds
Started Aug 13 06:23:29 PM PDT 24
Finished Aug 13 06:23:30 PM PDT 24
Peak memory 206512 kb
Host smart-c6aa9eb8-399d-4f58-9ea1-31f86f199a27
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006377565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1006377565
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3621607226
Short name T153
Test name
Test status
Simulation time 105255169 ps
CPU time 1.61 seconds
Started Aug 13 06:23:42 PM PDT 24
Finished Aug 13 06:23:44 PM PDT 24
Peak memory 215704 kb
Host smart-be3771d7-cb9c-4876-bd07-403c9be3a7f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621607226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.3621607226 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3172812609
Short name T94
Test name
Test status
Simulation time 74220847 ps
CPU time 1.04 seconds
Started Aug 13 06:23:27 PM PDT 24
Finished Aug 13 06:23:28 PM PDT 24
Peak memory 215196 kb
Host smart-b2802177-7424-460b-95de-d6a0119d84f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172812609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.3172812609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.646117033
Short name T790
Test name
Test status
Simulation time 58622505 ps
CPU time 1.6 seconds
Started Aug 13 06:23:32 PM PDT 24
Finished Aug 13 06:23:34 PM PDT 24
Peak memory 215104 kb
Host smart-9cca56fd-8122-44fe-9765-018c202bebf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646117033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_
shadow_reg_errors_with_csr_rw.646117033 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.43687992
Short name T124
Test name
Test status
Simulation time 48000825 ps
CPU time 2.89 seconds
Started Aug 13 06:23:28 PM PDT 24
Finished Aug 13 06:23:31 PM PDT 24
Peak memory 223144 kb
Host smart-695f9b85-2b22-48ee-9a71-de2784ca656f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43687992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.43687992 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.21377841
Short name T121
Test name
Test status
Simulation time 68991423 ps
CPU time 1.67 seconds
Started Aug 13 06:24:01 PM PDT 24
Finished Aug 13 06:24:03 PM PDT 24
Peak memory 215072 kb
Host smart-f9e023f3-fc4b-4780-a301-0f0610551ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21377841 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.21377841 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.3055129658
Short name T155
Test name
Test status
Simulation time 61661816 ps
CPU time 0.91 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 206500 kb
Host smart-5a2f8cdd-a9e8-4fe4-baf2-6890b89b9201
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055129658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3055129658 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.390818811
Short name T156
Test name
Test status
Simulation time 114891024 ps
CPU time 0.76 seconds
Started Aug 13 06:23:54 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 206520 kb
Host smart-306af29a-95ac-4a7d-985e-d011f8b8e725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390818811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.390818811 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3961696552
Short name T778
Test name
Test status
Simulation time 47775728 ps
CPU time 1.33 seconds
Started Aug 13 06:23:57 PM PDT 24
Finished Aug 13 06:23:59 PM PDT 24
Peak memory 214948 kb
Host smart-2966a6d3-2947-4fc7-8f5c-03b142b98cd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961696552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3961696552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4217824892
Short name T768
Test name
Test status
Simulation time 173479091 ps
CPU time 1.35 seconds
Started Aug 13 06:23:53 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 215360 kb
Host smart-c40ea722-478c-4ad5-9718-561ae13ab8ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217824892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.4217824892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3317841247
Short name T869
Test name
Test status
Simulation time 182965381 ps
CPU time 2.53 seconds
Started Aug 13 06:23:52 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 215492 kb
Host smart-11053b98-3827-40e5-9a79-1c58643c4c52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317841247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.3317841247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3909019855
Short name T785
Test name
Test status
Simulation time 77041652 ps
CPU time 1.55 seconds
Started Aug 13 06:23:56 PM PDT 24
Finished Aug 13 06:23:58 PM PDT 24
Peak memory 223204 kb
Host smart-d2dcfd80-41d5-4439-b4d7-72345b9c0e42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909019855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3909019855 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2780115938
Short name T179
Test name
Test status
Simulation time 190739110 ps
CPU time 2.39 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:58 PM PDT 24
Peak memory 215024 kb
Host smart-ab735229-a4d8-4dff-8c4f-e867d3b4879c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780115938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2780
115938 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1803403111
Short name T794
Test name
Test status
Simulation time 71281831 ps
CPU time 2.5 seconds
Started Aug 13 06:23:54 PM PDT 24
Finished Aug 13 06:23:57 PM PDT 24
Peak memory 216136 kb
Host smart-86eafa83-cae5-4512-9e45-dc6ceffa064f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803403111 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1803403111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2636498374
Short name T813
Test name
Test status
Simulation time 125575674 ps
CPU time 0.92 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 206432 kb
Host smart-1e69bad5-33ab-4566-a408-78a1e57191a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636498374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2636498374 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.2738076058
Short name T800
Test name
Test status
Simulation time 42297229 ps
CPU time 0.74 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 206520 kb
Host smart-e9df114d-3290-4d7e-b228-248bd8b1e466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738076058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2738076058 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3787621366
Short name T749
Test name
Test status
Simulation time 89798301 ps
CPU time 2.17 seconds
Started Aug 13 06:23:54 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 214940 kb
Host smart-7db521d6-6d5b-4603-9320-1196ca52df3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787621366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.3787621366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.650586660
Short name T90
Test name
Test status
Simulation time 111427851 ps
CPU time 1.2 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 215412 kb
Host smart-c70a709e-0550-4a35-84f2-3599fd05cdd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650586660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_
errors.650586660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1398983599
Short name T771
Test name
Test status
Simulation time 258475798 ps
CPU time 1.58 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:57 PM PDT 24
Peak memory 215428 kb
Host smart-7095fd11-b4cd-439b-85ec-d2221d069af9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398983599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.1398983599 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1346682068
Short name T123
Test name
Test status
Simulation time 538113015 ps
CPU time 3.73 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:58 PM PDT 24
Peak memory 215084 kb
Host smart-97a41caa-f402-4a97-be5d-a7bc441c8aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346682068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1346682068 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.4138252460
Short name T136
Test name
Test status
Simulation time 78656007 ps
CPU time 2.5 seconds
Started Aug 13 06:24:01 PM PDT 24
Finished Aug 13 06:24:04 PM PDT 24
Peak memory 214912 kb
Host smart-00df4e70-324f-405d-b3c4-b4e7b022f60b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138252460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.4138
252460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1010644124
Short name T133
Test name
Test status
Simulation time 77789572 ps
CPU time 2.45 seconds
Started Aug 13 06:23:54 PM PDT 24
Finished Aug 13 06:23:57 PM PDT 24
Peak memory 216172 kb
Host smart-26495406-707c-45cd-89aa-81d84a95c4bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010644124 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1010644124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.295768468
Short name T732
Test name
Test status
Simulation time 44872278 ps
CPU time 1.06 seconds
Started Aug 13 06:24:00 PM PDT 24
Finished Aug 13 06:24:01 PM PDT 24
Peak memory 206652 kb
Host smart-2b534539-0ada-4c62-83e1-0a8eaf80a7fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295768468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.295768468 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.3615026548
Short name T767
Test name
Test status
Simulation time 226475418 ps
CPU time 0.82 seconds
Started Aug 13 06:23:57 PM PDT 24
Finished Aug 13 06:23:58 PM PDT 24
Peak memory 206468 kb
Host smart-bd0fb9b9-9225-4a54-b1a5-084d369a2f9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615026548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3615026548 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2025212953
Short name T734
Test name
Test status
Simulation time 57120870 ps
CPU time 1.64 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:57 PM PDT 24
Peak memory 215204 kb
Host smart-eb314af5-ecb3-4330-97ca-a13500adc3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025212953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.2025212953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1736420213
Short name T825
Test name
Test status
Simulation time 105827311 ps
CPU time 1.04 seconds
Started Aug 13 06:24:01 PM PDT 24
Finished Aug 13 06:24:02 PM PDT 24
Peak memory 215188 kb
Host smart-7d694d2f-d125-45fb-9544-200fe92f469e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736420213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1736420213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1979374117
Short name T792
Test name
Test status
Simulation time 107833304 ps
CPU time 1.75 seconds
Started Aug 13 06:24:00 PM PDT 24
Finished Aug 13 06:24:02 PM PDT 24
Peak memory 215460 kb
Host smart-46e9e4ab-ae0e-4ece-a655-20b327b31fac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979374117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.1979374117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3092481222
Short name T814
Test name
Test status
Simulation time 75819570 ps
CPU time 2.22 seconds
Started Aug 13 06:23:57 PM PDT 24
Finished Aug 13 06:23:59 PM PDT 24
Peak memory 215072 kb
Host smart-4c64c3cd-56dc-45f2-8320-0a248aa950f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092481222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3092481222 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2289656692
Short name T861
Test name
Test status
Simulation time 195397139 ps
CPU time 2.17 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:57 PM PDT 24
Peak memory 214924 kb
Host smart-4140f8b7-8356-4821-9706-cba66a1b7909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289656692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2289
656692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3202790482
Short name T860
Test name
Test status
Simulation time 44396082 ps
CPU time 1.46 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:07 PM PDT 24
Peak memory 215036 kb
Host smart-6e8aec28-58ca-4997-979a-94f9668a95f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202790482 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3202790482 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.3597817754
Short name T735
Test name
Test status
Simulation time 56581008 ps
CPU time 1 seconds
Started Aug 13 06:24:03 PM PDT 24
Finished Aug 13 06:24:04 PM PDT 24
Peak memory 206768 kb
Host smart-d2c9b104-e47a-41c6-877a-b348caf66e86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597817754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3597817754 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.574672930
Short name T740
Test name
Test status
Simulation time 36784363 ps
CPU time 0.76 seconds
Started Aug 13 06:23:56 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 206480 kb
Host smart-8a2f731e-200b-4f4b-ae65-e4b93dedea77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574672930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.574672930 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.771379245
Short name T840
Test name
Test status
Simulation time 70986316 ps
CPU time 1.37 seconds
Started Aug 13 06:24:03 PM PDT 24
Finished Aug 13 06:24:05 PM PDT 24
Peak memory 215372 kb
Host smart-75320cae-aa7c-4d5d-b9ef-31e22e8b5672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771379245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr
_outstanding.771379245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3096494443
Short name T97
Test name
Test status
Simulation time 286558811 ps
CPU time 2.79 seconds
Started Aug 13 06:23:57 PM PDT 24
Finished Aug 13 06:24:00 PM PDT 24
Peak memory 215476 kb
Host smart-840fc298-6e8f-42b9-8962-06454fb91a26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096494443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.3096494443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2696498022
Short name T122
Test name
Test status
Simulation time 79847544 ps
CPU time 2.47 seconds
Started Aug 13 06:23:54 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 214968 kb
Host smart-0e04274a-8682-498a-990f-fa90b710375e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696498022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2696498022 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.744700799
Short name T791
Test name
Test status
Simulation time 691161665 ps
CPU time 2.92 seconds
Started Aug 13 06:23:58 PM PDT 24
Finished Aug 13 06:24:01 PM PDT 24
Peak memory 215136 kb
Host smart-7503184e-ba9d-48f6-bd6b-f24544a05990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744700799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.74470
0799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2462588114
Short name T817
Test name
Test status
Simulation time 153602349 ps
CPU time 1.57 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:08 PM PDT 24
Peak memory 214996 kb
Host smart-c5d3950c-67bd-4ebc-ad0e-800c27be27f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462588114 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2462588114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1634759287
Short name T737
Test name
Test status
Simulation time 48647738 ps
CPU time 1.11 seconds
Started Aug 13 06:24:08 PM PDT 24
Finished Aug 13 06:24:09 PM PDT 24
Peak memory 206764 kb
Host smart-82a64172-b13b-4054-83f7-d518615d57ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634759287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1634759287 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3189783006
Short name T175
Test name
Test status
Simulation time 42430165 ps
CPU time 0.75 seconds
Started Aug 13 06:24:05 PM PDT 24
Finished Aug 13 06:24:06 PM PDT 24
Peak memory 206412 kb
Host smart-d306cbbd-67fa-4e13-9231-4a24092b7c63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189783006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3189783006 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2482303129
Short name T744
Test name
Test status
Simulation time 96258529 ps
CPU time 1.49 seconds
Started Aug 13 06:24:04 PM PDT 24
Finished Aug 13 06:24:06 PM PDT 24
Peak memory 215240 kb
Host smart-c4141fd4-6355-45e4-978c-3359d35cb176
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482303129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.2482303129 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2701248429
Short name T95
Test name
Test status
Simulation time 73707305 ps
CPU time 1.42 seconds
Started Aug 13 06:24:04 PM PDT 24
Finished Aug 13 06:24:05 PM PDT 24
Peak memory 215364 kb
Host smart-b43bdfbf-519e-414c-bf5d-e1e97874bc5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701248429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.2701248429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1645148352
Short name T746
Test name
Test status
Simulation time 61269313 ps
CPU time 1.72 seconds
Started Aug 13 06:24:04 PM PDT 24
Finished Aug 13 06:24:05 PM PDT 24
Peak memory 215536 kb
Host smart-97fd32d6-4bd8-4ccf-8b50-f2f11d192c49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645148352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.1645148352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.772343124
Short name T837
Test name
Test status
Simulation time 118017392 ps
CPU time 2.01 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:08 PM PDT 24
Peak memory 215028 kb
Host smart-32742385-75ba-4904-81e2-9e4e637d4d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772343124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.772343124 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4132647416
Short name T786
Test name
Test status
Simulation time 33954663 ps
CPU time 2.06 seconds
Started Aug 13 06:24:05 PM PDT 24
Finished Aug 13 06:24:07 PM PDT 24
Peak memory 223220 kb
Host smart-212e8ba2-24d4-422b-be02-e38cd2dc6dcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132647416 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.4132647416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3265604179
Short name T806
Test name
Test status
Simulation time 19881578 ps
CPU time 0.93 seconds
Started Aug 13 06:24:07 PM PDT 24
Finished Aug 13 06:24:08 PM PDT 24
Peak memory 206520 kb
Host smart-a8384f68-30f9-45fd-86dd-c933354dfabd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265604179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3265604179 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.3688477120
Short name T868
Test name
Test status
Simulation time 14740439 ps
CPU time 0.75 seconds
Started Aug 13 06:24:05 PM PDT 24
Finished Aug 13 06:24:06 PM PDT 24
Peak memory 206472 kb
Host smart-05e3df4b-b710-4541-b4b9-6ba3dcf087a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688477120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3688477120 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1577535135
Short name T152
Test name
Test status
Simulation time 220905835 ps
CPU time 2.45 seconds
Started Aug 13 06:24:08 PM PDT 24
Finished Aug 13 06:24:11 PM PDT 24
Peak memory 215444 kb
Host smart-454e0eb2-defe-4f56-ab9d-2415e386349a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577535135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1577535135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2506635663
Short name T98
Test name
Test status
Simulation time 39075315 ps
CPU time 0.95 seconds
Started Aug 13 06:24:08 PM PDT 24
Finished Aug 13 06:24:09 PM PDT 24
Peak memory 215244 kb
Host smart-b6d8101d-9767-4f76-92c0-e1babf21cfb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506635663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.2506635663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.27751527
Short name T845
Test name
Test status
Simulation time 307041625 ps
CPU time 2.94 seconds
Started Aug 13 06:24:04 PM PDT 24
Finished Aug 13 06:24:07 PM PDT 24
Peak memory 223356 kb
Host smart-0c1d39e6-1570-416f-b4f0-7cb79b3e96e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27751527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_
shadow_reg_errors_with_csr_rw.27751527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3421253101
Short name T140
Test name
Test status
Simulation time 373680483 ps
CPU time 3.86 seconds
Started Aug 13 06:24:05 PM PDT 24
Finished Aug 13 06:24:09 PM PDT 24
Peak memory 214972 kb
Host smart-9d0c605e-1367-4d1b-989a-7b492c48da21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421253101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3421
253101 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1489767762
Short name T802
Test name
Test status
Simulation time 78249318 ps
CPU time 1.57 seconds
Started Aug 13 06:24:14 PM PDT 24
Finished Aug 13 06:24:16 PM PDT 24
Peak memory 215268 kb
Host smart-7bcb4f59-db08-4377-872b-06c2f658c20c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489767762 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.1489767762 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2250294948
Short name T763
Test name
Test status
Simulation time 26937635 ps
CPU time 0.93 seconds
Started Aug 13 06:24:08 PM PDT 24
Finished Aug 13 06:24:10 PM PDT 24
Peak memory 206548 kb
Host smart-39b5dc63-d111-4325-9a33-5ceeded0f941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250294948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2250294948 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.3252554535
Short name T838
Test name
Test status
Simulation time 44907117 ps
CPU time 0.76 seconds
Started Aug 13 06:24:04 PM PDT 24
Finished Aug 13 06:24:05 PM PDT 24
Peak memory 206420 kb
Host smart-27cdeee1-7f56-4044-98e9-c2c5662a7baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252554535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3252554535 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.766681237
Short name T782
Test name
Test status
Simulation time 118058932 ps
CPU time 1.59 seconds
Started Aug 13 06:24:05 PM PDT 24
Finished Aug 13 06:24:07 PM PDT 24
Peak memory 215036 kb
Host smart-2820b6b9-d893-4e5e-997f-e61a17bb8495
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766681237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.766681237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.321160365
Short name T787
Test name
Test status
Simulation time 38692655 ps
CPU time 0.97 seconds
Started Aug 13 06:24:03 PM PDT 24
Finished Aug 13 06:24:04 PM PDT 24
Peak memory 215188 kb
Host smart-32fa1a28-9bea-4dca-9f6f-bf4be486c42a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321160365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_
errors.321160365 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.493031229
Short name T781
Test name
Test status
Simulation time 187619803 ps
CPU time 1.79 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:08 PM PDT 24
Peak memory 215496 kb
Host smart-8f1ad164-9bfd-44c5-bdbd-ed7d31b177e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493031229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac
_shadow_reg_errors_with_csr_rw.493031229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3524014490
Short name T134
Test name
Test status
Simulation time 282010844 ps
CPU time 2.13 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:08 PM PDT 24
Peak memory 214988 kb
Host smart-e1a40767-4e99-4c1b-aa76-4f7f596e1652
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524014490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3524014490 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3382525121
Short name T183
Test name
Test status
Simulation time 184131166 ps
CPU time 3.96 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:10 PM PDT 24
Peak memory 206768 kb
Host smart-4d31c974-36b4-4871-82c1-7296bb68fa64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382525121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3382
525121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2921242635
Short name T852
Test name
Test status
Simulation time 90636897 ps
CPU time 2.19 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:08 PM PDT 24
Peak memory 216444 kb
Host smart-635d7f04-68e3-43f9-92aa-4a6791364027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921242635 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2921242635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.476878029
Short name T184
Test name
Test status
Simulation time 19772383 ps
CPU time 0.94 seconds
Started Aug 13 06:24:02 PM PDT 24
Finished Aug 13 06:24:03 PM PDT 24
Peak memory 206428 kb
Host smart-f4d8c956-c77d-47ac-a0d7-d4dc55e2a62c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476878029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.476878029 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.1027190435
Short name T805
Test name
Test status
Simulation time 13692945 ps
CPU time 0.77 seconds
Started Aug 13 06:24:13 PM PDT 24
Finished Aug 13 06:24:14 PM PDT 24
Peak memory 206496 kb
Host smart-aa641632-f33b-4b21-a93d-fda0c308724f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027190435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1027190435 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.228113289
Short name T804
Test name
Test status
Simulation time 119896386 ps
CPU time 1.65 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:08 PM PDT 24
Peak memory 215332 kb
Host smart-5d190b0e-10f9-45a7-9c35-9e3cdb26c0ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228113289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr
_outstanding.228113289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3313341815
Short name T826
Test name
Test status
Simulation time 61058834 ps
CPU time 1.5 seconds
Started Aug 13 06:24:13 PM PDT 24
Finished Aug 13 06:24:14 PM PDT 24
Peak memory 215420 kb
Host smart-245a2b71-94f0-43ca-8e6c-6bd0d2ed063c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313341815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.3313341815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1157631749
Short name T873
Test name
Test status
Simulation time 27792574 ps
CPU time 1.58 seconds
Started Aug 13 06:24:06 PM PDT 24
Finished Aug 13 06:24:07 PM PDT 24
Peak memory 215460 kb
Host smart-d9e9276e-845f-4ff1-9d3a-cab68d4485a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157631749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.1157631749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.4085616946
Short name T128
Test name
Test status
Simulation time 632963376 ps
CPU time 1.79 seconds
Started Aug 13 06:24:13 PM PDT 24
Finished Aug 13 06:24:15 PM PDT 24
Peak memory 215092 kb
Host smart-c7cbd17c-0a95-47c6-beca-fa65cbbda40e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085616946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.4085616946 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1481101098
Short name T762
Test name
Test status
Simulation time 274518999 ps
CPU time 3.07 seconds
Started Aug 13 06:24:07 PM PDT 24
Finished Aug 13 06:24:11 PM PDT 24
Peak memory 215012 kb
Host smart-1fef4303-9532-478e-a1ab-f726562928ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481101098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1481
101098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2947879205
Short name T775
Test name
Test status
Simulation time 53191704 ps
CPU time 1.75 seconds
Started Aug 13 06:24:13 PM PDT 24
Finished Aug 13 06:24:15 PM PDT 24
Peak memory 223044 kb
Host smart-8c9696cf-3b2f-4fb8-ac84-1c52a31e3404
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947879205 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2947879205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.890518293
Short name T797
Test name
Test status
Simulation time 19400159 ps
CPU time 0.93 seconds
Started Aug 13 06:24:05 PM PDT 24
Finished Aug 13 06:24:06 PM PDT 24
Peak memory 206368 kb
Host smart-e4b5d185-2777-4690-8248-725ddd292383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890518293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.890518293 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.340328972
Short name T151
Test name
Test status
Simulation time 427575046 ps
CPU time 1.73 seconds
Started Aug 13 06:24:03 PM PDT 24
Finished Aug 13 06:24:05 PM PDT 24
Peak memory 215412 kb
Host smart-d51237f8-440e-49d0-b411-80f521b18c28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340328972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr
_outstanding.340328972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2256823837
Short name T819
Test name
Test status
Simulation time 40403488 ps
CPU time 1.16 seconds
Started Aug 13 06:24:07 PM PDT 24
Finished Aug 13 06:24:08 PM PDT 24
Peak memory 215416 kb
Host smart-28b06069-d173-4413-a0d7-1ef96e3012bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256823837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.2256823837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1835275071
Short name T84
Test name
Test status
Simulation time 140629842 ps
CPU time 3.19 seconds
Started Aug 13 06:24:08 PM PDT 24
Finished Aug 13 06:24:12 PM PDT 24
Peak memory 223676 kb
Host smart-839b825e-d2c1-401f-80b8-545824617f6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835275071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.1835275071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3113377465
Short name T138
Test name
Test status
Simulation time 232324080 ps
CPU time 4.8 seconds
Started Aug 13 06:24:14 PM PDT 24
Finished Aug 13 06:24:18 PM PDT 24
Peak memory 215040 kb
Host smart-6b46cb96-d967-4415-9fd8-09d557439ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113377465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3113
377465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.174974836
Short name T139
Test name
Test status
Simulation time 58364455 ps
CPU time 1.73 seconds
Started Aug 13 06:24:14 PM PDT 24
Finished Aug 13 06:24:16 PM PDT 24
Peak memory 215060 kb
Host smart-298bdb96-5e76-4614-bb95-f2ae04162d5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174974836 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.174974836 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.4248883140
Short name T777
Test name
Test status
Simulation time 66526056 ps
CPU time 0.93 seconds
Started Aug 13 06:24:15 PM PDT 24
Finished Aug 13 06:24:16 PM PDT 24
Peak memory 206436 kb
Host smart-3082f38c-dfa7-4bad-9e54-45f27e4bd199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248883140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4248883140 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.370201927
Short name T780
Test name
Test status
Simulation time 48135442 ps
CPU time 0.87 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:19 PM PDT 24
Peak memory 206492 kb
Host smart-5d8058cc-f31d-4620-ba7d-9aaedd66b7f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370201927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.370201927 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.458277571
Short name T750
Test name
Test status
Simulation time 122502065 ps
CPU time 1.41 seconds
Started Aug 13 06:24:12 PM PDT 24
Finished Aug 13 06:24:14 PM PDT 24
Peak memory 214932 kb
Host smart-fb3aae92-545a-4604-b2a5-409913fdb8a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458277571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.458277571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.4067329873
Short name T859
Test name
Test status
Simulation time 45208669 ps
CPU time 1.02 seconds
Started Aug 13 06:24:03 PM PDT 24
Finished Aug 13 06:24:04 PM PDT 24
Peak memory 207192 kb
Host smart-e131ab00-a201-4274-9961-1e71018be956
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067329873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.4067329873 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2177898179
Short name T770
Test name
Test status
Simulation time 123024294 ps
CPU time 1.87 seconds
Started Aug 13 06:24:15 PM PDT 24
Finished Aug 13 06:24:17 PM PDT 24
Peak memory 215448 kb
Host smart-5cc5b601-9fe0-4078-a904-f515414e104f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177898179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.2177898179 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.4248476571
Short name T848
Test name
Test status
Simulation time 38032127 ps
CPU time 2.2 seconds
Started Aug 13 06:24:15 PM PDT 24
Finished Aug 13 06:24:17 PM PDT 24
Peak memory 214988 kb
Host smart-b7a7a746-9c78-4e75-b3b7-37118d72a450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248476571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.4248476571 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3746030991
Short name T116
Test name
Test status
Simulation time 95686647 ps
CPU time 4.04 seconds
Started Aug 13 06:24:15 PM PDT 24
Finished Aug 13 06:24:20 PM PDT 24
Peak memory 215068 kb
Host smart-0123c686-5422-45fd-b3fd-3af9c44b96d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746030991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3746
030991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3949303059
Short name T793
Test name
Test status
Simulation time 3348194469 ps
CPU time 9.1 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:50 PM PDT 24
Peak memory 214972 kb
Host smart-a2b252db-404f-4f1c-846d-3c498ad81e64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949303059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3949303
059 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1448352291
Short name T789
Test name
Test status
Simulation time 301562966 ps
CPU time 14.77 seconds
Started Aug 13 06:23:35 PM PDT 24
Finished Aug 13 06:23:50 PM PDT 24
Peak memory 206676 kb
Host smart-5f2641ea-ca19-4492-b8ef-8297435369b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448352291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1448352
291 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.705806604
Short name T739
Test name
Test status
Simulation time 52859339 ps
CPU time 1.11 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:43 PM PDT 24
Peak memory 206676 kb
Host smart-8aea3c10-d529-43ee-a17f-0b4812e3d40f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705806604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.70580660
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.821147067
Short name T761
Test name
Test status
Simulation time 133250230 ps
CPU time 1.56 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:43 PM PDT 24
Peak memory 215232 kb
Host smart-130e5abf-09a4-447f-8fa8-d9c145e96e9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821147067 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.821147067 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1318926990
Short name T753
Test name
Test status
Simulation time 102706673 ps
CPU time 1.13 seconds
Started Aug 13 06:23:39 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 206588 kb
Host smart-de93316f-e58f-4c47-b91c-ed3d59f08654
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318926990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1318926990 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.1563038465
Short name T849
Test name
Test status
Simulation time 19629466 ps
CPU time 0.72 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:42 PM PDT 24
Peak memory 206532 kb
Host smart-e74aa8a0-f1a6-4dbd-8cc8-9c57b7b98f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563038465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.1563038465 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1565437215
Short name T146
Test name
Test status
Simulation time 57549643 ps
CPU time 1.18 seconds
Started Aug 13 06:23:39 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 214844 kb
Host smart-73b5e78f-a830-415e-8dfe-92aed29ed844
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565437215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.1565437215 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.4274452183
Short name T812
Test name
Test status
Simulation time 32491601 ps
CPU time 0.76 seconds
Started Aug 13 06:23:39 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 206496 kb
Host smart-2a8697ec-7198-4e3d-8a71-66892822e243
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274452183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.4274452183
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2286320465
Short name T736
Test name
Test status
Simulation time 58804128 ps
CPU time 1.52 seconds
Started Aug 13 06:23:35 PM PDT 24
Finished Aug 13 06:23:37 PM PDT 24
Peak memory 214924 kb
Host smart-f0f6bb9a-9a4d-42ff-9e26-b39baed73383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286320465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.2286320465 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3230295613
Short name T850
Test name
Test status
Simulation time 182198760 ps
CPU time 1.37 seconds
Started Aug 13 06:23:35 PM PDT 24
Finished Aug 13 06:23:37 PM PDT 24
Peak memory 215440 kb
Host smart-04fee002-a21d-4d40-b19c-3a2faef628b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230295613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.3230295613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1628543932
Short name T839
Test name
Test status
Simulation time 67726050 ps
CPU time 2.41 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:43 PM PDT 24
Peak memory 215468 kb
Host smart-222366a0-c687-4da4-8387-a7207db6382e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628543932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.1628543932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2270093883
Short name T803
Test name
Test status
Simulation time 298282590 ps
CPU time 2.49 seconds
Started Aug 13 06:23:37 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 216924 kb
Host smart-c7af5653-ddbe-4395-85cc-f39265a4fc0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270093883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2270093883 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1824220746
Short name T137
Test name
Test status
Simulation time 1005033462 ps
CPU time 3.78 seconds
Started Aug 13 06:23:42 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 215056 kb
Host smart-f37fe6d9-d6f4-40f0-b58d-fb42b1a653da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824220746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.18242
20746 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.2044040788
Short name T765
Test name
Test status
Simulation time 13994848 ps
CPU time 0.71 seconds
Started Aug 13 06:24:16 PM PDT 24
Finished Aug 13 06:24:17 PM PDT 24
Peak memory 206496 kb
Host smart-5d1003c7-66e7-4d98-8d15-e8c5b8a32eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044040788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2044040788 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.1724904364
Short name T173
Test name
Test status
Simulation time 14036677 ps
CPU time 0.75 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:19 PM PDT 24
Peak memory 206468 kb
Host smart-502bbd2f-2e7b-4938-92ce-6ba103c0ccfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724904364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1724904364 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.376858298
Short name T828
Test name
Test status
Simulation time 30754415 ps
CPU time 0.79 seconds
Started Aug 13 06:24:14 PM PDT 24
Finished Aug 13 06:24:15 PM PDT 24
Peak memory 206540 kb
Host smart-0b9ad392-22fd-4020-b80b-32e1b8095dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376858298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.376858298 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.3628844123
Short name T127
Test name
Test status
Simulation time 14684665 ps
CPU time 0.79 seconds
Started Aug 13 06:24:17 PM PDT 24
Finished Aug 13 06:24:18 PM PDT 24
Peak memory 206520 kb
Host smart-ac98fb2e-c020-4a8f-bf9a-d8fd95a40e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628844123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3628844123 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2215974744
Short name T170
Test name
Test status
Simulation time 17124237 ps
CPU time 0.77 seconds
Started Aug 13 06:24:13 PM PDT 24
Finished Aug 13 06:24:14 PM PDT 24
Peak memory 206532 kb
Host smart-b50c507b-3e7c-4deb-83b8-c2cc59f2cfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215974744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2215974744 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.3627060128
Short name T751
Test name
Test status
Simulation time 15139686 ps
CPU time 0.76 seconds
Started Aug 13 06:24:19 PM PDT 24
Finished Aug 13 06:24:20 PM PDT 24
Peak memory 206496 kb
Host smart-30378a5a-b30b-4ffd-9e7e-745d2fcf2b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627060128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3627060128 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.1162913634
Short name T171
Test name
Test status
Simulation time 18286004 ps
CPU time 0.77 seconds
Started Aug 13 06:24:15 PM PDT 24
Finished Aug 13 06:24:16 PM PDT 24
Peak memory 206504 kb
Host smart-15a0e526-c925-451c-8bee-224a92caef65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162913634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1162913634 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.977399836
Short name T798
Test name
Test status
Simulation time 39962422 ps
CPU time 0.75 seconds
Started Aug 13 06:24:16 PM PDT 24
Finished Aug 13 06:24:17 PM PDT 24
Peak memory 206508 kb
Host smart-d956cb2a-13de-462e-bd2a-af1e24adf961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977399836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.977399836 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.2425517469
Short name T158
Test name
Test status
Simulation time 23226812 ps
CPU time 0.76 seconds
Started Aug 13 06:24:16 PM PDT 24
Finished Aug 13 06:24:17 PM PDT 24
Peak memory 206484 kb
Host smart-d6d2bf03-2049-41d3-8a64-5307a0356a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425517469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2425517469 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.4087433253
Short name T159
Test name
Test status
Simulation time 1089404846 ps
CPU time 5.7 seconds
Started Aug 13 06:23:35 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 206748 kb
Host smart-ed8674ec-0114-485b-bdc6-a529ce904421
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087433253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.4087433
253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.852558558
Short name T821
Test name
Test status
Simulation time 279270403 ps
CPU time 8.28 seconds
Started Aug 13 06:23:40 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 206756 kb
Host smart-86968dfe-4d77-482c-98bd-67253556a0cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852558558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.85255855
8 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2964919623
Short name T86
Test name
Test status
Simulation time 23609968 ps
CPU time 0.92 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:42 PM PDT 24
Peak memory 206520 kb
Host smart-2346de13-8152-441f-81b2-f476d74ac672
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964919623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2964919
623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2360880692
Short name T835
Test name
Test status
Simulation time 49940809 ps
CPU time 2.44 seconds
Started Aug 13 06:23:35 PM PDT 24
Finished Aug 13 06:23:37 PM PDT 24
Peak memory 223220 kb
Host smart-94c581ce-7b87-4ea8-bde2-a6c9928d0e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360880692 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2360880692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3307667375
Short name T818
Test name
Test status
Simulation time 40477114 ps
CPU time 0.86 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:41 PM PDT 24
Peak memory 206640 kb
Host smart-0da11a3e-cd68-418b-ba0a-8c38757dceb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307667375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3307667375 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.3714423455
Short name T858
Test name
Test status
Simulation time 166264830 ps
CPU time 0.77 seconds
Started Aug 13 06:23:43 PM PDT 24
Finished Aug 13 06:23:44 PM PDT 24
Peak memory 206444 kb
Host smart-7ca65ca2-32c8-4a51-97c6-1f78bc0f4b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714423455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3714423455 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2789354964
Short name T784
Test name
Test status
Simulation time 96832678 ps
CPU time 1.16 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:43 PM PDT 24
Peak memory 214876 kb
Host smart-e74e9d37-a8e3-486d-8956-fd7689ad30b5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789354964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2789354964 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3487118366
Short name T738
Test name
Test status
Simulation time 21527349 ps
CPU time 0.71 seconds
Started Aug 13 06:23:42 PM PDT 24
Finished Aug 13 06:23:43 PM PDT 24
Peak memory 206528 kb
Host smart-dd8e86b3-61ac-4bd7-929e-293e4d10271e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487118366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3487118366
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1511227514
Short name T864
Test name
Test status
Simulation time 95536207 ps
CPU time 2.46 seconds
Started Aug 13 06:23:34 PM PDT 24
Finished Aug 13 06:23:36 PM PDT 24
Peak memory 215248 kb
Host smart-a5a432fa-2f8a-41f8-85b7-12a8bc72788b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511227514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.1511227514 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.924918149
Short name T96
Test name
Test status
Simulation time 29283037 ps
CPU time 1.14 seconds
Started Aug 13 06:23:35 PM PDT 24
Finished Aug 13 06:23:37 PM PDT 24
Peak memory 215440 kb
Host smart-632af52f-72df-4aa6-ab39-c34cd0aa0722
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924918149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.924918149 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2429447207
Short name T824
Test name
Test status
Simulation time 182307002 ps
CPU time 1.65 seconds
Started Aug 13 06:23:38 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 215356 kb
Host smart-95b88794-9272-4d76-8417-d246bb83a211
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429447207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.2429447207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.2547676017
Short name T773
Test name
Test status
Simulation time 948267601 ps
CPU time 3.59 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:45 PM PDT 24
Peak memory 215104 kb
Host smart-7d2f3360-ab1e-44f4-ba73-39f108df4526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547676017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2547676017 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.2352697792
Short name T829
Test name
Test status
Simulation time 34947625 ps
CPU time 0.74 seconds
Started Aug 13 06:24:16 PM PDT 24
Finished Aug 13 06:24:17 PM PDT 24
Peak memory 206520 kb
Host smart-a6ef636d-b3bc-4349-b9f0-8eb6eb0bb3b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352697792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2352697792 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.4263676854
Short name T157
Test name
Test status
Simulation time 15746613 ps
CPU time 0.78 seconds
Started Aug 13 06:24:17 PM PDT 24
Finished Aug 13 06:24:18 PM PDT 24
Peak memory 206500 kb
Host smart-099e072e-fd2f-433d-868c-4d61a0b96664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263676854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.4263676854 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.165470669
Short name T742
Test name
Test status
Simulation time 14477456 ps
CPU time 0.78 seconds
Started Aug 13 06:24:13 PM PDT 24
Finished Aug 13 06:24:14 PM PDT 24
Peak memory 206476 kb
Host smart-a3bbd34d-a40b-4d5d-89a7-aaf9d7ef70de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165470669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.165470669 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.1288165858
Short name T854
Test name
Test status
Simulation time 15206964 ps
CPU time 0.72 seconds
Started Aug 13 06:24:16 PM PDT 24
Finished Aug 13 06:24:17 PM PDT 24
Peak memory 206464 kb
Host smart-e0d80bd1-ab62-4152-846b-799fd2f9176b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288165858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1288165858 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.635862357
Short name T833
Test name
Test status
Simulation time 55894829 ps
CPU time 0.81 seconds
Started Aug 13 06:24:14 PM PDT 24
Finished Aug 13 06:24:15 PM PDT 24
Peak memory 206436 kb
Host smart-aaf66517-1782-411f-890d-17e898eb1f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635862357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.635862357 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3443670094
Short name T872
Test name
Test status
Simulation time 32801250 ps
CPU time 0.76 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:19 PM PDT 24
Peak memory 206504 kb
Host smart-0de54c48-d1e2-40b3-b67e-60c3de445012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443670094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3443670094 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.1836607897
Short name T856
Test name
Test status
Simulation time 42283015 ps
CPU time 0.78 seconds
Started Aug 13 06:24:13 PM PDT 24
Finished Aug 13 06:24:14 PM PDT 24
Peak memory 206524 kb
Host smart-3e84594a-6b5a-459b-9119-04172f65fb07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836607897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1836607897 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.942738682
Short name T843
Test name
Test status
Simulation time 55619727 ps
CPU time 0.75 seconds
Started Aug 13 06:24:15 PM PDT 24
Finished Aug 13 06:24:16 PM PDT 24
Peak memory 206420 kb
Host smart-c1463ad2-bb1d-4935-985d-d270b64f219c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942738682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.942738682 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.2859618145
Short name T796
Test name
Test status
Simulation time 43202378 ps
CPU time 0.77 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:19 PM PDT 24
Peak memory 206504 kb
Host smart-b668707d-cbf4-4c1c-be18-d7b6179d0d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859618145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2859618145 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.3475887564
Short name T820
Test name
Test status
Simulation time 15592096 ps
CPU time 0.79 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:19 PM PDT 24
Peak memory 206496 kb
Host smart-ce3b0c7d-a430-417d-a678-f366d084df6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475887564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3475887564 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2777555501
Short name T779
Test name
Test status
Simulation time 251237315 ps
CPU time 5.13 seconds
Started Aug 13 06:23:47 PM PDT 24
Finished Aug 13 06:23:53 PM PDT 24
Peak memory 206724 kb
Host smart-3723be14-7ef1-442f-b13c-eab4e8b7c545
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777555501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2777555
501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1566965950
Short name T815
Test name
Test status
Simulation time 766661267 ps
CPU time 10.79 seconds
Started Aug 13 06:23:44 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 206632 kb
Host smart-7740ad70-d604-40c6-a99d-71e6a086a063
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566965950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1566965
950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3290315984
Short name T841
Test name
Test status
Simulation time 38470322 ps
CPU time 0.96 seconds
Started Aug 13 06:23:43 PM PDT 24
Finished Aug 13 06:23:45 PM PDT 24
Peak memory 206448 kb
Host smart-52e924a7-f8a9-4ee8-87c3-723c1d224468
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290315984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3290315
984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3772178862
Short name T115
Test name
Test status
Simulation time 61261941 ps
CPU time 2.28 seconds
Started Aug 13 06:23:43 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 217096 kb
Host smart-9d50c082-c948-48ab-b5a0-3322e1dabc0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772178862 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3772178862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3213901419
Short name T808
Test name
Test status
Simulation time 32805270 ps
CPU time 0.93 seconds
Started Aug 13 06:23:48 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 205316 kb
Host smart-8d386940-1ec5-4065-92b8-c7a2d68c9491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213901419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3213901419 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.2470288621
Short name T741
Test name
Test status
Simulation time 14572812 ps
CPU time 0.78 seconds
Started Aug 13 06:23:43 PM PDT 24
Finished Aug 13 06:23:44 PM PDT 24
Peak memory 206524 kb
Host smart-6e1a5140-dc72-4a84-9084-44d8005cd127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470288621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2470288621 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2611934018
Short name T145
Test name
Test status
Simulation time 33789442 ps
CPU time 1.23 seconds
Started Aug 13 06:23:36 PM PDT 24
Finished Aug 13 06:23:38 PM PDT 24
Peak memory 214980 kb
Host smart-67b15501-550f-43b0-b325-4f0ca1fd0c9a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611934018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.2611934018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.999363844
Short name T743
Test name
Test status
Simulation time 16168715 ps
CPU time 0.75 seconds
Started Aug 13 06:23:43 PM PDT 24
Finished Aug 13 06:23:44 PM PDT 24
Peak memory 206444 kb
Host smart-2df18b3f-f1f6-4501-9949-e91f9c36ffcb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999363844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.999363844 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.898720921
Short name T755
Test name
Test status
Simulation time 49555323 ps
CPU time 1.48 seconds
Started Aug 13 06:23:44 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 215288 kb
Host smart-c1f3704c-5d54-40f8-972f-ae5d7820e57f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898720921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_
outstanding.898720921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.660001575
Short name T834
Test name
Test status
Simulation time 148234436 ps
CPU time 1.18 seconds
Started Aug 13 06:23:41 PM PDT 24
Finished Aug 13 06:23:43 PM PDT 24
Peak memory 215024 kb
Host smart-6505f5fd-1ea7-4e52-972c-40d64c270b58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660001575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_e
rrors.660001575 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3507589999
Short name T117
Test name
Test status
Simulation time 67814727 ps
CPU time 1.86 seconds
Started Aug 13 06:23:38 PM PDT 24
Finished Aug 13 06:23:40 PM PDT 24
Peak memory 215368 kb
Host smart-48d795a0-f77c-4de4-88d1-3252967c333e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507589999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.3507589999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3175739039
Short name T130
Test name
Test status
Simulation time 39142426 ps
CPU time 1.88 seconds
Started Aug 13 06:23:34 PM PDT 24
Finished Aug 13 06:23:36 PM PDT 24
Peak memory 215016 kb
Host smart-814035aa-6387-4796-9d2c-a48f1cfec928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175739039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3175739039 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4219582289
Short name T754
Test name
Test status
Simulation time 54417796 ps
CPU time 2.41 seconds
Started Aug 13 06:23:35 PM PDT 24
Finished Aug 13 06:23:38 PM PDT 24
Peak memory 215272 kb
Host smart-b04e2cb6-53ba-46ad-ba08-578ff884fcf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219582289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.42195
82289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.3056633075
Short name T801
Test name
Test status
Simulation time 35610610 ps
CPU time 0.72 seconds
Started Aug 13 06:24:17 PM PDT 24
Finished Aug 13 06:24:18 PM PDT 24
Peak memory 206448 kb
Host smart-12610ff2-653c-431d-b565-6007d54a212e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056633075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3056633075 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.3104861401
Short name T174
Test name
Test status
Simulation time 18477343 ps
CPU time 0.78 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:19 PM PDT 24
Peak memory 206472 kb
Host smart-a12779d3-2588-494c-aa31-ab4274a37e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104861401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3104861401 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.2121424898
Short name T822
Test name
Test status
Simulation time 18812332 ps
CPU time 0.77 seconds
Started Aug 13 06:24:19 PM PDT 24
Finished Aug 13 06:24:20 PM PDT 24
Peak memory 206504 kb
Host smart-3ef86044-f7cc-476f-af12-89335409989e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121424898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2121424898 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.78441356
Short name T747
Test name
Test status
Simulation time 12008525 ps
CPU time 0.75 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:18 PM PDT 24
Peak memory 206524 kb
Host smart-da9edaa8-16b7-4e0e-bf5b-8b93a9c1f02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78441356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.78441356 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.81753819
Short name T830
Test name
Test status
Simulation time 15694071 ps
CPU time 0.8 seconds
Started Aug 13 06:24:15 PM PDT 24
Finished Aug 13 06:24:16 PM PDT 24
Peak memory 206444 kb
Host smart-3db18363-3906-45c9-8527-6da39243766d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81753819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.81753819 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.3271284476
Short name T827
Test name
Test status
Simulation time 12312777 ps
CPU time 0.71 seconds
Started Aug 13 06:24:15 PM PDT 24
Finished Aug 13 06:24:16 PM PDT 24
Peak memory 206504 kb
Host smart-340b36f1-c261-4e34-9b63-209db0ab4c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271284476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3271284476 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.2706767311
Short name T847
Test name
Test status
Simulation time 34746842 ps
CPU time 0.81 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:19 PM PDT 24
Peak memory 206448 kb
Host smart-56779592-08b4-4f9f-818b-02d0a438ab58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706767311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2706767311 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.1928168612
Short name T172
Test name
Test status
Simulation time 48082928 ps
CPU time 0.74 seconds
Started Aug 13 06:24:17 PM PDT 24
Finished Aug 13 06:24:18 PM PDT 24
Peak memory 206412 kb
Host smart-53960858-e9f4-42e1-b5d3-d3ef128ad025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928168612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1928168612 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2452917443
Short name T844
Test name
Test status
Simulation time 13910584 ps
CPU time 0.79 seconds
Started Aug 13 06:24:18 PM PDT 24
Finished Aug 13 06:24:19 PM PDT 24
Peak memory 206468 kb
Host smart-32a3d714-3189-4862-ac51-a5147fd2db8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452917443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2452917443 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.2005149774
Short name T857
Test name
Test status
Simulation time 21610332 ps
CPU time 0.76 seconds
Started Aug 13 06:24:17 PM PDT 24
Finished Aug 13 06:24:18 PM PDT 24
Peak memory 206412 kb
Host smart-0c5b5f72-6fee-48f7-ad0c-e344d3bbc5e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005149774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2005149774 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.259734308
Short name T752
Test name
Test status
Simulation time 83618472 ps
CPU time 1.68 seconds
Started Aug 13 06:23:47 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 223228 kb
Host smart-094b7de8-ee2e-4f46-9976-7b76a63bbd1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259734308 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.259734308 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1705436629
Short name T769
Test name
Test status
Simulation time 24318030 ps
CPU time 0.9 seconds
Started Aug 13 06:23:48 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 206372 kb
Host smart-82dded98-33e4-4306-a352-c7e89c1da989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705436629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1705436629 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.778246037
Short name T810
Test name
Test status
Simulation time 28889961 ps
CPU time 0.76 seconds
Started Aug 13 06:23:48 PM PDT 24
Finished Aug 13 06:23:48 PM PDT 24
Peak memory 206524 kb
Host smart-da8563fe-bc12-485f-9e2a-1f64dd29f086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778246037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.778246037 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3655476861
Short name T774
Test name
Test status
Simulation time 468098168 ps
CPU time 1.49 seconds
Started Aug 13 06:23:47 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 214864 kb
Host smart-37efc5b3-a9a3-4922-a8f9-312f7d100c28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655476861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.3655476861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3860456381
Short name T772
Test name
Test status
Simulation time 40969194 ps
CPU time 1.2 seconds
Started Aug 13 06:23:43 PM PDT 24
Finished Aug 13 06:23:45 PM PDT 24
Peak memory 215488 kb
Host smart-3dd2bc42-2fa8-41ba-910b-24c2a56152f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860456381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.3860456381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3841559677
Short name T87
Test name
Test status
Simulation time 130525000 ps
CPU time 1.61 seconds
Started Aug 13 06:23:44 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 223360 kb
Host smart-a6168078-74f0-46ba-9dbc-22752321538a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841559677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.3841559677 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.1297533731
Short name T176
Test name
Test status
Simulation time 155158560 ps
CPU time 2.56 seconds
Started Aug 13 06:23:46 PM PDT 24
Finished Aug 13 06:23:48 PM PDT 24
Peak memory 215016 kb
Host smart-742a7327-0021-4283-bf9f-150b8d66348f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297533731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1297533731 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2858806613
Short name T135
Test name
Test status
Simulation time 83713761 ps
CPU time 2.46 seconds
Started Aug 13 06:23:43 PM PDT 24
Finished Aug 13 06:23:45 PM PDT 24
Peak memory 214952 kb
Host smart-90bf7ab1-ce36-437b-9176-49ff54925de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858806613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.28588
06613 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3990614252
Short name T766
Test name
Test status
Simulation time 257846803 ps
CPU time 2.18 seconds
Started Aug 13 06:23:46 PM PDT 24
Finished Aug 13 06:23:48 PM PDT 24
Peak memory 216400 kb
Host smart-76a1e062-259e-4151-aa85-8324d8596faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990614252 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3990614252 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.105685179
Short name T795
Test name
Test status
Simulation time 54451177 ps
CPU time 0.94 seconds
Started Aug 13 06:23:54 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 206380 kb
Host smart-c33fd1c2-0849-4985-b2f7-28be6a850701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105685179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.105685179 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.2946697921
Short name T807
Test name
Test status
Simulation time 25736926 ps
CPU time 0.74 seconds
Started Aug 13 06:23:45 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 206484 kb
Host smart-b0aafefa-0acc-4b3f-9683-c43896ac1a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946697921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2946697921 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4013579925
Short name T799
Test name
Test status
Simulation time 58506581 ps
CPU time 1.59 seconds
Started Aug 13 06:23:48 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 214956 kb
Host smart-acb46cfe-fbc0-440d-b2ef-8a0403bca91c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013579925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.4013579925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3328087343
Short name T88
Test name
Test status
Simulation time 112373928 ps
CPU time 1.19 seconds
Started Aug 13 06:23:45 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 215460 kb
Host smart-96a4498c-65d8-4d83-a333-67ce085adf8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328087343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3328087343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.440750356
Short name T870
Test name
Test status
Simulation time 56782007 ps
CPU time 1.78 seconds
Started Aug 13 06:23:48 PM PDT 24
Finished Aug 13 06:23:50 PM PDT 24
Peak memory 215128 kb
Host smart-6257d60e-7523-4df5-a286-8956d42a0225
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440750356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.440750356 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.929837220
Short name T46
Test name
Test status
Simulation time 241702248 ps
CPU time 4.56 seconds
Started Aug 13 06:23:46 PM PDT 24
Finished Aug 13 06:23:51 PM PDT 24
Peak memory 214884 kb
Host smart-bdcdcc6f-f645-455c-926e-b55fe9fc52ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929837220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.929837
220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.614453415
Short name T816
Test name
Test status
Simulation time 148653763 ps
CPU time 2.21 seconds
Started Aug 13 06:23:44 PM PDT 24
Finished Aug 13 06:23:47 PM PDT 24
Peak memory 216036 kb
Host smart-f88003ab-697d-4748-81a6-a409d6ffcef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614453415 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.614453415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2453435063
Short name T788
Test name
Test status
Simulation time 60853867 ps
CPU time 1.11 seconds
Started Aug 13 06:23:46 PM PDT 24
Finished Aug 13 06:23:47 PM PDT 24
Peak memory 206668 kb
Host smart-938c2fa6-8029-4bf8-80f9-e062455f4f31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453435063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2453435063 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.3724825888
Short name T832
Test name
Test status
Simulation time 13465801 ps
CPU time 0.72 seconds
Started Aug 13 06:23:44 PM PDT 24
Finished Aug 13 06:23:45 PM PDT 24
Peak memory 206648 kb
Host smart-922fd20f-42cc-4d7c-ae94-eb0f0ae6136a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724825888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3724825888 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3160602229
Short name T760
Test name
Test status
Simulation time 132866660 ps
CPU time 2.3 seconds
Started Aug 13 06:23:44 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 215376 kb
Host smart-0fa4fc7c-d33a-4abd-8519-46a3e039de09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160602229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3160602229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1972998880
Short name T851
Test name
Test status
Simulation time 154613701 ps
CPU time 1.13 seconds
Started Aug 13 06:23:45 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 215400 kb
Host smart-41985ae3-75e1-4f3a-a1f9-6d89072043fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972998880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.1972998880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2770179001
Short name T91
Test name
Test status
Simulation time 815117772 ps
CPU time 2.01 seconds
Started Aug 13 06:23:48 PM PDT 24
Finished Aug 13 06:23:50 PM PDT 24
Peak memory 215412 kb
Host smart-405b79cf-2f50-46ba-a559-dc1564d5cbc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770179001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.2770179001 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2095030272
Short name T866
Test name
Test status
Simulation time 354537184 ps
CPU time 2.27 seconds
Started Aug 13 06:23:44 PM PDT 24
Finished Aug 13 06:23:47 PM PDT 24
Peak memory 214964 kb
Host smart-467b2c2f-946b-43c6-99dc-2cb91e53c633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095030272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2095030272 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1904187274
Short name T842
Test name
Test status
Simulation time 228438554 ps
CPU time 4.38 seconds
Started Aug 13 06:23:45 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 205664 kb
Host smart-e8a2c762-6fd1-4ee1-8f44-6326f2143b90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904187274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.19041
87274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.465760241
Short name T45
Test name
Test status
Simulation time 400015338 ps
CPU time 1.7 seconds
Started Aug 13 06:23:56 PM PDT 24
Finished Aug 13 06:23:58 PM PDT 24
Peak memory 215456 kb
Host smart-1be86793-8116-43e0-820a-76f502272662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465760241 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.465760241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.4024171900
Short name T759
Test name
Test status
Simulation time 114734986 ps
CPU time 1.15 seconds
Started Aug 13 06:23:54 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 206704 kb
Host smart-e234a76b-5eaf-4044-a865-d0b0f792ef0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024171900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.4024171900 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3404526372
Short name T871
Test name
Test status
Simulation time 25498617 ps
CPU time 0.74 seconds
Started Aug 13 06:23:42 PM PDT 24
Finished Aug 13 06:23:43 PM PDT 24
Peak memory 206500 kb
Host smart-2d681b72-bb93-4a75-adc9-56608ec36a5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404526372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3404526372 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.667402932
Short name T836
Test name
Test status
Simulation time 45102305 ps
CPU time 1.42 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:57 PM PDT 24
Peak memory 215148 kb
Host smart-9f967dc6-e04e-4fe6-8e2f-500908925ba0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667402932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_
outstanding.667402932 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1090960242
Short name T89
Test name
Test status
Simulation time 39498152 ps
CPU time 1.06 seconds
Started Aug 13 06:23:46 PM PDT 24
Finished Aug 13 06:23:48 PM PDT 24
Peak memory 215348 kb
Host smart-468ba5dc-fd87-4659-9507-179b2da8f3da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090960242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.1090960242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.12252727
Short name T119
Test name
Test status
Simulation time 178415137 ps
CPU time 2.98 seconds
Started Aug 13 06:23:47 PM PDT 24
Finished Aug 13 06:23:50 PM PDT 24
Peak memory 214956 kb
Host smart-dea9843b-5c3e-4370-82e2-bd643df9e990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12252727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.12252727 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.4206545571
Short name T182
Test name
Test status
Simulation time 738237361 ps
CPU time 4.46 seconds
Started Aug 13 06:23:45 PM PDT 24
Finished Aug 13 06:23:49 PM PDT 24
Peak memory 215012 kb
Host smart-c200ff93-6893-42be-a80e-4d70493f7817
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206545571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.42065
45571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3707697782
Short name T776
Test name
Test status
Simulation time 56401633 ps
CPU time 1.56 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:57 PM PDT 24
Peak memory 215192 kb
Host smart-920fb0d5-cf34-472c-adcc-1e7d5988a4e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707697782 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3707697782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3342360720
Short name T758
Test name
Test status
Simulation time 67136044 ps
CPU time 0.9 seconds
Started Aug 13 06:23:54 PM PDT 24
Finished Aug 13 06:23:55 PM PDT 24
Peak memory 206444 kb
Host smart-56362f20-5b0b-47eb-a63c-00a5bb8e2adc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342360720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3342360720 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.982252009
Short name T823
Test name
Test status
Simulation time 13350016 ps
CPU time 0.76 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 206488 kb
Host smart-f2b9c30b-de20-41de-9420-71e871cf3544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982252009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.982252009 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2112674335
Short name T862
Test name
Test status
Simulation time 132567404 ps
CPU time 1.74 seconds
Started Aug 13 06:23:57 PM PDT 24
Finished Aug 13 06:23:59 PM PDT 24
Peak memory 214968 kb
Host smart-993ab381-b605-471d-8c65-a1185265695b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112674335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2112674335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2334504030
Short name T764
Test name
Test status
Simulation time 30999262 ps
CPU time 0.98 seconds
Started Aug 13 06:23:55 PM PDT 24
Finished Aug 13 06:23:56 PM PDT 24
Peak memory 215072 kb
Host smart-a035e859-47df-4840-98a3-9a2e0823fdc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334504030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.2334504030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1745359822
Short name T757
Test name
Test status
Simulation time 258769054 ps
CPU time 2.03 seconds
Started Aug 13 06:23:56 PM PDT 24
Finished Aug 13 06:23:59 PM PDT 24
Peak memory 215488 kb
Host smart-017213d9-2d5c-4ad1-85ce-76a54a9b6fc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745359822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1745359822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2658067470
Short name T132
Test name
Test status
Simulation time 808018630 ps
CPU time 3.54 seconds
Started Aug 13 06:23:56 PM PDT 24
Finished Aug 13 06:24:00 PM PDT 24
Peak memory 215004 kb
Host smart-070014e4-fbb2-48b9-a488-6f342bac0f95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658067470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2658067470 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/default/0.kmac_app.998983213
Short name T516
Test name
Test status
Simulation time 2572157777 ps
CPU time 147.87 seconds
Started Aug 13 05:54:57 PM PDT 24
Finished Aug 13 05:57:25 PM PDT 24
Peak memory 279208 kb
Host smart-d8aabece-dc5a-46c3-b557-fe371b11014a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998983213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.998983213 +enable_masking=0
+sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.5251908
Short name T421
Test name
Test status
Simulation time 133736038887 ps
CPU time 268.67 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:59:25 PM PDT 24
Peak memory 444180 kb
Host smart-63534961-ac37-4160-a580-42b8916fec5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5251908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial
_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partia
l_data.5251908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2283181062
Short name T177
Test name
Test status
Simulation time 31397967299 ps
CPU time 712.21 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 06:06:48 PM PDT 24
Peak memory 239464 kb
Host smart-fa2bf81c-3951-47bf-bd1f-a46a191d005a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283181062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2283181062
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.3726723611
Short name T102
Test name
Test status
Simulation time 6833202541 ps
CPU time 27.41 seconds
Started Aug 13 05:54:54 PM PDT 24
Finished Aug 13 05:55:21 PM PDT 24
Peak memory 223600 kb
Host smart-732ab400-2626-45e6-884b-1183d04846ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3726723611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3726723611 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.421233306
Short name T630
Test name
Test status
Simulation time 1366621934 ps
CPU time 24.67 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:55:21 PM PDT 24
Peak memory 223472 kb
Host smart-021ca4e6-83b5-4abc-ad70-f96b6caf16e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=421233306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.421233306 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.412401587
Short name T299
Test name
Test status
Simulation time 31691308809 ps
CPU time 124.65 seconds
Started Aug 13 05:54:57 PM PDT 24
Finished Aug 13 05:57:02 PM PDT 24
Peak memory 316984 kb
Host smart-6c62e5da-839a-465a-bae7-951f52c087b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412401587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.412
401587 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_key_error.3402839905
Short name T495
Test name
Test status
Simulation time 1731218583 ps
CPU time 4.87 seconds
Started Aug 13 05:54:58 PM PDT 24
Finished Aug 13 05:55:03 PM PDT 24
Peak memory 217656 kb
Host smart-987dc609-ac77-4023-a5bd-7da7ae828b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402839905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3402839905 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.3514644271
Short name T390
Test name
Test status
Simulation time 41107325 ps
CPU time 1.45 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:54:58 PM PDT 24
Peak memory 217620 kb
Host smart-a537fa83-3f48-4cbe-a51e-2697e029dc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514644271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3514644271 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3465370645
Short name T360
Test name
Test status
Simulation time 44342061339 ps
CPU time 529.79 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 06:03:46 PM PDT 24
Peak memory 852840 kb
Host smart-648152fe-9de9-4f70-b985-8db0f167e73e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465370645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3465370645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.836668515
Short name T74
Test name
Test status
Simulation time 23873760670 ps
CPU time 320.11 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 06:00:16 PM PDT 24
Peak memory 497324 kb
Host smart-2a2504c4-31fc-4d91-9e9f-260c7f7d36d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836668515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.836668515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.2059049747
Short name T63
Test name
Test status
Simulation time 4836268879 ps
CPU time 60.67 seconds
Started Aug 13 05:54:58 PM PDT 24
Finished Aug 13 05:55:59 PM PDT 24
Peak memory 257916 kb
Host smart-a9f33d0f-536b-4a31-9cc2-4cb929d58ff6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059049747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2059049747 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.823229630
Short name T314
Test name
Test status
Simulation time 4436565558 ps
CPU time 88.84 seconds
Started Aug 13 05:54:55 PM PDT 24
Finished Aug 13 05:56:24 PM PDT 24
Peak memory 257756 kb
Host smart-f2e79a6a-e202-4003-a091-95d0c332d6a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823229630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.823229630 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.2134769263
Short name T402
Test name
Test status
Simulation time 3321581894 ps
CPU time 55.91 seconds
Started Aug 13 05:54:54 PM PDT 24
Finished Aug 13 05:55:50 PM PDT 24
Peak memory 220972 kb
Host smart-999db0ff-6021-4409-ba46-d3cbd888efbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134769263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2134769263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.793628283
Short name T499
Test name
Test status
Simulation time 73874881305 ps
CPU time 2082.99 seconds
Started Aug 13 05:54:57 PM PDT 24
Finished Aug 13 06:29:41 PM PDT 24
Peak memory 1394148 kb
Host smart-8d2c4788-5b00-45f8-b236-4b95dade4e13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=793628283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.793628283 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.830900054
Short name T501
Test name
Test status
Simulation time 64844844 ps
CPU time 2.17 seconds
Started Aug 13 05:54:58 PM PDT 24
Finished Aug 13 05:55:00 PM PDT 24
Peak memory 217512 kb
Host smart-378a257e-b3ef-41b5-af88-3e66021a54a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830900054 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.kmac_test_vectors_kmac.830900054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.3165034357
Short name T362
Test name
Test status
Simulation time 1465882497 ps
CPU time 3.06 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:54:59 PM PDT 24
Peak memory 217768 kb
Host smart-0c8a45a1-d292-4307-8b8f-cd45ee400af7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165034357 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3165034357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.4006563634
Short name T432
Test name
Test status
Simulation time 72464888973 ps
CPU time 1717.21 seconds
Started Aug 13 05:55:00 PM PDT 24
Finished Aug 13 06:23:37 PM PDT 24
Peak memory 1155756 kb
Host smart-6961a77e-4989-4b63-a62d-88a4ccf43e9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4006563634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.4006563634 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.1658477827
Short name T541
Test name
Test status
Simulation time 85659435307 ps
CPU time 2993.55 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 06:44:51 PM PDT 24
Peak memory 2941800 kb
Host smart-7f97c4fb-e3b0-4c72-a7dd-16519bd526de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1658477827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1658477827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.2996018334
Short name T213
Test name
Test status
Simulation time 12766999330 ps
CPU time 1231.36 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 06:15:28 PM PDT 24
Peak memory 885632 kb
Host smart-ddfed1a6-ad65-456f-b8b7-bc40112bc236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2996018334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2996018334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.2266122013
Short name T437
Test name
Test status
Simulation time 18250050229 ps
CPU time 837.4 seconds
Started Aug 13 05:54:58 PM PDT 24
Finished Aug 13 06:08:56 PM PDT 24
Peak memory 701784 kb
Host smart-95a9a573-9970-46d1-9b44-0d7b7fc1f38e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2266122013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2266122013 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.764814329
Short name T577
Test name
Test status
Simulation time 170167398873 ps
CPU time 2058.07 seconds
Started Aug 13 05:54:57 PM PDT 24
Finished Aug 13 06:29:15 PM PDT 24
Peak memory 1325180 kb
Host smart-491412e7-bc59-4287-8798-41bfdc8983ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=764814329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.764814329 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.2145893987
Short name T316
Test name
Test status
Simulation time 9968832162 ps
CPU time 136.36 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:57:13 PM PDT 24
Peak memory 348384 kb
Host smart-a01034c9-82d9-420b-ab66-992e846bef1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2145893987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2145893987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.2419717871
Short name T409
Test name
Test status
Simulation time 22482425 ps
CPU time 0.79 seconds
Started Aug 13 05:55:06 PM PDT 24
Finished Aug 13 05:55:07 PM PDT 24
Peak memory 204952 kb
Host smart-d26c4a2f-0dae-4800-998f-c05bffbff5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419717871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2419717871 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.3561569834
Short name T36
Test name
Test status
Simulation time 11606678980 ps
CPU time 282.31 seconds
Started Aug 13 05:55:09 PM PDT 24
Finished Aug 13 05:59:51 PM PDT 24
Peak memory 478964 kb
Host smart-bdf23080-df3c-4494-a82e-e96fdd51ebbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561569834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3561569834 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.36199680
Short name T476
Test name
Test status
Simulation time 12357766739 ps
CPU time 264 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:59:29 PM PDT 24
Peak memory 419112 kb
Host smart-02b2a6a3-1f38-4b19-b962-647cf44adc42
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36199680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partia
l_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_parti
al_data.36199680 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.2062366180
Short name T493
Test name
Test status
Simulation time 79909182773 ps
CPU time 606.76 seconds
Started Aug 13 05:54:53 PM PDT 24
Finished Aug 13 06:05:00 PM PDT 24
Peak memory 244812 kb
Host smart-c57ad278-3317-4678-a682-8c386def5f44
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062366180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2062366180
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.467221015
Short name T254
Test name
Test status
Simulation time 6446706805 ps
CPU time 32.45 seconds
Started Aug 13 05:55:06 PM PDT 24
Finished Aug 13 05:55:38 PM PDT 24
Peak memory 221272 kb
Host smart-1ede781e-84d9-43ac-ad3c-799806dc14c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=467221015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.467221015 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1610615565
Short name T77
Test name
Test status
Simulation time 2272877309 ps
CPU time 26.08 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:55:31 PM PDT 24
Peak memory 218716 kb
Host smart-f317816a-4813-49a5-965a-70f6db1586ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1610615565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1610615565 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.1065176009
Short name T633
Test name
Test status
Simulation time 10913027576 ps
CPU time 33.16 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:55:39 PM PDT 24
Peak memory 218416 kb
Host smart-450f6e5c-9417-495e-9d7e-72258331c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065176009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1065176009 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.1751633738
Short name T25
Test name
Test status
Simulation time 77513680721 ps
CPU time 370.69 seconds
Started Aug 13 05:55:06 PM PDT 24
Finished Aug 13 06:01:17 PM PDT 24
Peak memory 498896 kb
Host smart-69248221-2201-489a-a371-9cd76fd62a82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751633738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.17
51633738 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.1644587065
Short name T452
Test name
Test status
Simulation time 3232271806 ps
CPU time 96.59 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:56:42 PM PDT 24
Peak memory 301236 kb
Host smart-e3bed69e-2453-4a2e-815a-dafc0b7eab75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644587065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1644587065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.3406768207
Short name T717
Test name
Test status
Simulation time 3538214065 ps
CPU time 5.85 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:55:11 PM PDT 24
Peak memory 218696 kb
Host smart-978f6994-456b-4346-98f8-b43b42432cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406768207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3406768207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1923345918
Short name T253
Test name
Test status
Simulation time 55281913381 ps
CPU time 2059.72 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 06:29:17 PM PDT 24
Peak memory 2155808 kb
Host smart-479fddf9-4743-413a-acd8-e886e69bf51c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923345918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1923345918 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.279305195
Short name T312
Test name
Test status
Simulation time 839828552 ps
CPU time 18.82 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:55:24 PM PDT 24
Peak memory 239092 kb
Host smart-f4df2c6e-6b28-48c7-aa75-dbd9a4a61694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279305195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.279305195 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.398564772
Short name T12
Test name
Test status
Simulation time 11661267881 ps
CPU time 85.26 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:56:30 PM PDT 24
Peak memory 280024 kb
Host smart-a5304040-cee9-451b-a999-3616d2d5008b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398564772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.398564772 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.211599962
Short name T268
Test name
Test status
Simulation time 26631133407 ps
CPU time 160.07 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:57:37 PM PDT 24
Peak memory 352628 kb
Host smart-01e91782-d855-4bf0-8ea8-59a311f8f80d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211599962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.211599962 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.1125544341
Short name T257
Test name
Test status
Simulation time 3753711490 ps
CPU time 21.48 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 05:55:18 PM PDT 24
Peak memory 223620 kb
Host smart-45ae22c7-321e-421f-bcc4-539051d6e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125544341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1125544341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.873410170
Short name T412
Test name
Test status
Simulation time 1264861482 ps
CPU time 4.74 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 05:55:12 PM PDT 24
Peak memory 219796 kb
Host smart-0ba8d0de-4f55-483e-a279-5085e6648e84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=873410170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.873410170 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.3890678832
Short name T195
Test name
Test status
Simulation time 239533024 ps
CPU time 2.46 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 05:55:10 PM PDT 24
Peak memory 217820 kb
Host smart-842402dc-57b6-4398-86ff-c1ca136f1f45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890678832 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.3890678832 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3141715740
Short name T355
Test name
Test status
Simulation time 322252196 ps
CPU time 2.66 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 05:55:10 PM PDT 24
Peak memory 217832 kb
Host smart-c3af9273-5c2c-40ac-8491-8e8d828cd6d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141715740 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3141715740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.1871792926
Short name T564
Test name
Test status
Simulation time 71307585043 ps
CPU time 1891.41 seconds
Started Aug 13 05:54:58 PM PDT 24
Finished Aug 13 06:26:30 PM PDT 24
Peak memory 1185652 kb
Host smart-6fff3958-a7f2-4b2d-b7d3-7fa9f4658b08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1871792926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1871792926 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.855326884
Short name T673
Test name
Test status
Simulation time 68152665950 ps
CPU time 1617.86 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 06:21:54 PM PDT 24
Peak memory 1097148 kb
Host smart-36936328-1418-4876-853c-9f663b5eab53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=855326884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.855326884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.3528627367
Short name T523
Test name
Test status
Simulation time 440468744 ps
CPU time 24.82 seconds
Started Aug 13 05:54:55 PM PDT 24
Finished Aug 13 05:55:20 PM PDT 24
Peak memory 216544 kb
Host smart-9b634d2b-d862-413d-ad8e-a6f22786101b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3528627367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3528627367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.2472474046
Short name T587
Test name
Test status
Simulation time 744866602 ps
CPU time 18.45 seconds
Started Aug 13 05:54:57 PM PDT 24
Finished Aug 13 05:55:16 PM PDT 24
Peak memory 217468 kb
Host smart-529ad66f-79ef-4479-8b72-0609be0a2cf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2472474046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2472474046 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1532022381
Short name T19
Test name
Test status
Simulation time 114190574272 ps
CPU time 4256.25 seconds
Started Aug 13 05:54:56 PM PDT 24
Finished Aug 13 07:05:53 PM PDT 24
Peak memory 3639300 kb
Host smart-172e229f-1d71-4aa5-8610-2149cf970ef0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1532022381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1532022381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3327993435
Short name T234
Test name
Test status
Simulation time 22553502215 ps
CPU time 321.7 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 06:00:29 PM PDT 24
Peak memory 253188 kb
Host smart-f27137fe-b8dc-4cee-be1b-ebfedba10bfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3327993435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3327993435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.3828051913
Short name T504
Test name
Test status
Simulation time 13267730 ps
CPU time 0.79 seconds
Started Aug 13 05:55:45 PM PDT 24
Finished Aug 13 05:55:46 PM PDT 24
Peak memory 204936 kb
Host smart-606c0010-5f5a-40df-a999-79accee5a0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828051913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3828051913 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.554205153
Short name T701
Test name
Test status
Simulation time 17387303285 ps
CPU time 259.65 seconds
Started Aug 13 05:55:39 PM PDT 24
Finished Aug 13 05:59:59 PM PDT 24
Peak memory 434116 kb
Host smart-b2b6a115-c40e-445b-829f-c85986fc7118
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554205153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.554205153 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.4247772802
Short name T277
Test name
Test status
Simulation time 49341062270 ps
CPU time 423.34 seconds
Started Aug 13 05:55:37 PM PDT 24
Finished Aug 13 06:02:41 PM PDT 24
Peak memory 237168 kb
Host smart-a3e6c7b9-8db0-46bf-a520-8770c61dcb65
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247772802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.424777280
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.3197364497
Short name T196
Test name
Test status
Simulation time 7576604229 ps
CPU time 37.32 seconds
Started Aug 13 05:55:39 PM PDT 24
Finished Aug 13 05:56:16 PM PDT 24
Peak memory 223612 kb
Host smart-f7eddf24-4486-4c97-ae65-b26852eb9766
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3197364497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3197364497 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2810071355
Short name T291
Test name
Test status
Simulation time 12507640645 ps
CPU time 39.8 seconds
Started Aug 13 05:55:36 PM PDT 24
Finished Aug 13 05:56:16 PM PDT 24
Peak memory 224608 kb
Host smart-f976bc51-30b5-488b-907d-d609379d2f4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810071355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2810071355 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.3655710851
Short name T259
Test name
Test status
Simulation time 3408571434 ps
CPU time 53.94 seconds
Started Aug 13 05:55:45 PM PDT 24
Finished Aug 13 05:56:39 PM PDT 24
Peak memory 239932 kb
Host smart-70eb13a9-a6fc-4f94-a98f-2ad01c4c0cc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655710851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3
655710851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.4279875656
Short name T488
Test name
Test status
Simulation time 1441316943 ps
CPU time 27.35 seconds
Started Aug 13 05:55:38 PM PDT 24
Finished Aug 13 05:56:05 PM PDT 24
Peak memory 238372 kb
Host smart-9cce38e4-82d0-473d-a714-12dcfa051fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279875656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.4279875656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.763640335
Short name T429
Test name
Test status
Simulation time 3081024611 ps
CPU time 8.31 seconds
Started Aug 13 05:55:38 PM PDT 24
Finished Aug 13 05:55:47 PM PDT 24
Peak memory 217312 kb
Host smart-324b8aae-9074-456c-8359-dd27abe61910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763640335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.763640335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.878184701
Short name T387
Test name
Test status
Simulation time 101490381407 ps
CPU time 5073.85 seconds
Started Aug 13 05:55:39 PM PDT 24
Finished Aug 13 07:20:14 PM PDT 24
Peak memory 3683468 kb
Host smart-72fa778e-0087-4a87-993e-e61e5e452b19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878184701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_an
d_output.878184701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2812032418
Short name T642
Test name
Test status
Simulation time 3172486928 ps
CPU time 10.32 seconds
Started Aug 13 05:55:40 PM PDT 24
Finished Aug 13 05:55:50 PM PDT 24
Peak memory 219452 kb
Host smart-164d2b00-4429-40f2-8947-572ee469d9c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812032418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2812032418 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.2617161895
Short name T594
Test name
Test status
Simulation time 728105339 ps
CPU time 37.56 seconds
Started Aug 13 05:55:45 PM PDT 24
Finished Aug 13 05:56:23 PM PDT 24
Peak memory 217616 kb
Host smart-714aa484-b347-4159-9913-a90ae457caf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617161895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2617161895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.1031335612
Short name T506
Test name
Test status
Simulation time 17847753030 ps
CPU time 136.04 seconds
Started Aug 13 05:55:39 PM PDT 24
Finished Aug 13 05:57:55 PM PDT 24
Peak memory 290600 kb
Host smart-063a865b-b253-4e67-a094-a77eb61092f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1031335612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1031335612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_alert_test.203305229
Short name T615
Test name
Test status
Simulation time 28367730 ps
CPU time 0.84 seconds
Started Aug 13 05:55:47 PM PDT 24
Finished Aug 13 05:55:48 PM PDT 24
Peak memory 204824 kb
Host smart-dc2fbdc9-30fa-4ec7-9067-34992a11be28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203305229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.203305229 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.1260305462
Short name T264
Test name
Test status
Simulation time 9978133341 ps
CPU time 306.42 seconds
Started Aug 13 05:55:48 PM PDT 24
Finished Aug 13 06:00:54 PM PDT 24
Peak memory 337780 kb
Host smart-fc317f42-852c-4f6d-89ab-65be10e82158
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260305462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1260305462 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.1946495452
Short name T293
Test name
Test status
Simulation time 432985244505 ps
CPU time 810.39 seconds
Started Aug 13 05:55:44 PM PDT 24
Finished Aug 13 06:09:15 PM PDT 24
Peak memory 250412 kb
Host smart-22615a37-1fa7-40ac-bd7c-d7f9f4eeec22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946495452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.194649545
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.2955147177
Short name T276
Test name
Test status
Simulation time 7127991454 ps
CPU time 36.55 seconds
Started Aug 13 05:55:50 PM PDT 24
Finished Aug 13 05:56:27 PM PDT 24
Peak memory 220920 kb
Host smart-a73b7119-fcf8-46d8-a3b3-974a2a4a7877
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2955147177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2955147177 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2826873992
Short name T460
Test name
Test status
Simulation time 1391006849 ps
CPU time 3.83 seconds
Started Aug 13 05:55:49 PM PDT 24
Finished Aug 13 05:55:53 PM PDT 24
Peak memory 215404 kb
Host smart-e9dbeaac-42fc-4713-823e-4c66122b1974
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2826873992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2826873992 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.3337060470
Short name T275
Test name
Test status
Simulation time 1291425183 ps
CPU time 34.32 seconds
Started Aug 13 05:55:48 PM PDT 24
Finished Aug 13 05:56:23 PM PDT 24
Peak memory 232372 kb
Host smart-bb0de3a5-07d3-4c57-a601-c830cefc9457
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337060470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3
337060470 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.3177114668
Short name T72
Test name
Test status
Simulation time 848926032 ps
CPU time 71.22 seconds
Started Aug 13 05:55:45 PM PDT 24
Finished Aug 13 05:56:56 PM PDT 24
Peak memory 256472 kb
Host smart-3d455f07-8427-4f22-9707-84c357892498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177114668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3177114668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.2306330340
Short name T57
Test name
Test status
Simulation time 157333965 ps
CPU time 1.58 seconds
Started Aug 13 05:55:47 PM PDT 24
Finished Aug 13 05:55:49 PM PDT 24
Peak memory 217748 kb
Host smart-d72c27a2-15c5-4d76-88f0-6c737024bfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306330340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2306330340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.2324770560
Short name T69
Test name
Test status
Simulation time 186576204640 ps
CPU time 1198.92 seconds
Started Aug 13 05:55:48 PM PDT 24
Finished Aug 13 06:15:47 PM PDT 24
Peak memory 1559300 kb
Host smart-44148a57-befb-46d8-9093-d685c81a8725
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324770560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.2324770560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2308955707
Short name T194
Test name
Test status
Simulation time 462736036 ps
CPU time 5.91 seconds
Started Aug 13 05:55:47 PM PDT 24
Finished Aug 13 05:55:54 PM PDT 24
Peak memory 218852 kb
Host smart-d8ff1e88-1663-4813-ab82-e8a5f40c9f9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308955707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2308955707 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.3865129415
Short name T189
Test name
Test status
Simulation time 2139283810 ps
CPU time 47.77 seconds
Started Aug 13 05:55:38 PM PDT 24
Finished Aug 13 05:56:26 PM PDT 24
Peak memory 217644 kb
Host smart-d902a303-356f-4ea1-9f71-75aeb14d155e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865129415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3865129415 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.2415735435
Short name T574
Test name
Test status
Simulation time 86069901223 ps
CPU time 491.96 seconds
Started Aug 13 05:55:48 PM PDT 24
Finished Aug 13 06:04:00 PM PDT 24
Peak memory 514500 kb
Host smart-85805bb4-25a8-4d14-979d-0ab2ecc4374c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2415735435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2415735435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_alert_test.701370280
Short name T527
Test name
Test status
Simulation time 21877531 ps
CPU time 0.82 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 05:55:59 PM PDT 24
Peak memory 204868 kb
Host smart-83bf940a-2218-4deb-8b69-32672035a692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701370280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.701370280 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.1367747399
Short name T581
Test name
Test status
Simulation time 7579884368 ps
CPU time 46.98 seconds
Started Aug 13 05:55:47 PM PDT 24
Finished Aug 13 05:56:35 PM PDT 24
Peak memory 260360 kb
Host smart-ead9cda0-8276-40c4-b63a-832fa5fbdaea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367747399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1367747399 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.3372122083
Short name T613
Test name
Test status
Simulation time 22640717976 ps
CPU time 444.42 seconds
Started Aug 13 05:55:47 PM PDT 24
Finished Aug 13 06:03:12 PM PDT 24
Peak memory 238624 kb
Host smart-3b0a555b-903b-4409-bc53-70410e14d9a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372122083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.337212208
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.1572831783
Short name T604
Test name
Test status
Simulation time 268298498 ps
CPU time 6.95 seconds
Started Aug 13 05:55:55 PM PDT 24
Finished Aug 13 05:56:03 PM PDT 24
Peak memory 216320 kb
Host smart-e0fe4649-07db-4c77-adfd-ccd6291e9734
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1572831783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1572831783 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.2021318967
Short name T246
Test name
Test status
Simulation time 33866123 ps
CPU time 1.26 seconds
Started Aug 13 05:56:02 PM PDT 24
Finished Aug 13 05:56:03 PM PDT 24
Peak memory 215412 kb
Host smart-0995c027-36a3-4cca-b09c-269e5aeffff8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2021318967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2021318967 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.352564898
Short name T224
Test name
Test status
Simulation time 15543287542 ps
CPU time 166.64 seconds
Started Aug 13 05:55:48 PM PDT 24
Finished Aug 13 05:58:35 PM PDT 24
Peak memory 362828 kb
Host smart-a3941554-22b8-42cd-a40b-5db14b503ccf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352564898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.35
2564898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.3420412250
Short name T369
Test name
Test status
Simulation time 915725032 ps
CPU time 69.69 seconds
Started Aug 13 05:55:56 PM PDT 24
Finished Aug 13 05:57:06 PM PDT 24
Peak memory 252196 kb
Host smart-bd4d71b9-4fd5-4018-9722-f1fb6ca5db77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420412250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3420412250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.2144746424
Short name T403
Test name
Test status
Simulation time 618028779 ps
CPU time 3.67 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 05:56:02 PM PDT 24
Peak memory 217284 kb
Host smart-b3b6049f-57ed-45a3-a152-6402c3dc432d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144746424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2144746424 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.751848188
Short name T49
Test name
Test status
Simulation time 125898993 ps
CPU time 1.39 seconds
Started Aug 13 05:55:56 PM PDT 24
Finished Aug 13 05:55:58 PM PDT 24
Peak memory 218036 kb
Host smart-72ec79c5-056b-43c7-b7ba-6c4c08bd7f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751848188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.751848188 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.576022973
Short name T726
Test name
Test status
Simulation time 23549117179 ps
CPU time 607.78 seconds
Started Aug 13 05:55:47 PM PDT 24
Finished Aug 13 06:05:55 PM PDT 24
Peak memory 624448 kb
Host smart-9501ea69-c693-462b-977c-51784818b5e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576022973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.576022973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.2885297846
Short name T518
Test name
Test status
Simulation time 1475771940 ps
CPU time 123.59 seconds
Started Aug 13 05:55:45 PM PDT 24
Finished Aug 13 05:57:49 PM PDT 24
Peak memory 269720 kb
Host smart-0315aa0c-b46a-44d3-be98-72608f791f86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885297846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2885297846 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.1102240090
Short name T578
Test name
Test status
Simulation time 33000386 ps
CPU time 1.6 seconds
Started Aug 13 05:55:48 PM PDT 24
Finished Aug 13 05:55:50 PM PDT 24
Peak memory 217944 kb
Host smart-0ed17580-d2d4-44ef-9c5b-3a79524eb796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102240090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1102240090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.645169816
Short name T333
Test name
Test status
Simulation time 12176985671 ps
CPU time 327.77 seconds
Started Aug 13 05:55:53 PM PDT 24
Finished Aug 13 06:01:21 PM PDT 24
Peak memory 330068 kb
Host smart-37e0a30b-868c-40fc-a27a-24afa1ec6f8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=645169816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.645169816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_alert_test.4204711002
Short name T361
Test name
Test status
Simulation time 19462326 ps
CPU time 0.83 seconds
Started Aug 13 05:55:57 PM PDT 24
Finished Aug 13 05:55:59 PM PDT 24
Peak memory 204928 kb
Host smart-6980980a-95d2-4c98-bc34-02c358067039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204711002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.4204711002 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.3660144217
Short name T368
Test name
Test status
Simulation time 4998330717 ps
CPU time 122 seconds
Started Aug 13 05:55:57 PM PDT 24
Finished Aug 13 05:57:59 PM PDT 24
Peak memory 267140 kb
Host smart-f80e8186-10f3-4f24-a8c4-460be2e0c499
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660144217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3660144217 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.1242175895
Short name T150
Test name
Test status
Simulation time 39971267357 ps
CPU time 356.16 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 06:01:54 PM PDT 24
Peak memory 235436 kb
Host smart-48f9e9eb-dbaa-4268-b152-f0d6883b3569
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242175895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.124217589
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2440193138
Short name T663
Test name
Test status
Simulation time 6485355991 ps
CPU time 43.79 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 05:56:42 PM PDT 24
Peak memory 221908 kb
Host smart-3050e55e-80c7-4515-a12a-7741c7c53300
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2440193138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2440193138 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.3447078395
Short name T218
Test name
Test status
Simulation time 36842921 ps
CPU time 2.85 seconds
Started Aug 13 05:55:57 PM PDT 24
Finished Aug 13 05:56:00 PM PDT 24
Peak memory 215356 kb
Host smart-03a387d8-7371-4b9b-b100-7bcbc671e1a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3447078395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3447078395 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.2986808331
Short name T609
Test name
Test status
Simulation time 1009929405 ps
CPU time 20.02 seconds
Started Aug 13 05:55:55 PM PDT 24
Finished Aug 13 05:56:15 PM PDT 24
Peak memory 221272 kb
Host smart-7a7dff35-9f1a-45db-b2c3-a64690afb83a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986808331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2
986808331 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.855608661
Short name T220
Test name
Test status
Simulation time 570792535 ps
CPU time 46.2 seconds
Started Aug 13 05:55:56 PM PDT 24
Finished Aug 13 05:56:43 PM PDT 24
Peak memory 248412 kb
Host smart-58d160dc-402c-4e3d-9ad4-acbdb72c29a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855608661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.855608661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.2117183237
Short name T284
Test name
Test status
Simulation time 2629821868 ps
CPU time 2.59 seconds
Started Aug 13 05:55:56 PM PDT 24
Finished Aug 13 05:55:59 PM PDT 24
Peak memory 217800 kb
Host smart-1475624d-1529-4840-9b0e-68ad3503e504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117183237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.2117183237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.2588677720
Short name T679
Test name
Test status
Simulation time 54447066 ps
CPU time 1.79 seconds
Started Aug 13 05:55:57 PM PDT 24
Finished Aug 13 05:55:59 PM PDT 24
Peak memory 216840 kb
Host smart-2bba7090-fe35-42d2-97c0-9d1f9f6ce009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588677720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2588677720 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3435071607
Short name T547
Test name
Test status
Simulation time 74092574359 ps
CPU time 2219.52 seconds
Started Aug 13 05:55:56 PM PDT 24
Finished Aug 13 06:32:56 PM PDT 24
Peak memory 1387960 kb
Host smart-2d54f78c-8a88-4d41-9f0a-de57799c01ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435071607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3435071607 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3982646662
Short name T350
Test name
Test status
Simulation time 18465850492 ps
CPU time 525.53 seconds
Started Aug 13 05:55:56 PM PDT 24
Finished Aug 13 06:04:42 PM PDT 24
Peak memory 643040 kb
Host smart-3fd74457-ffe6-43f8-8011-2509515a68ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982646662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3982646662 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.3886712580
Short name T327
Test name
Test status
Simulation time 1558360489 ps
CPU time 9.24 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 05:56:07 PM PDT 24
Peak memory 219152 kb
Host smart-94f80582-f2c1-4469-ba89-cd670182a10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886712580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3886712580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.708708922
Short name T693
Test name
Test status
Simulation time 38733941098 ps
CPU time 594.94 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 06:05:53 PM PDT 24
Peak memory 410784 kb
Host smart-b82076b9-c314-47a6-9336-5fc2e8862365
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=708708922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.708708922 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_alert_test.1572106018
Short name T285
Test name
Test status
Simulation time 15427231 ps
CPU time 0.78 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 05:56:06 PM PDT 24
Peak memory 204892 kb
Host smart-22a1cfb7-ab59-4974-8fb2-960a1a6ea496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572106018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1572106018 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.3764463253
Short name T545
Test name
Test status
Simulation time 4365906284 ps
CPU time 78.89 seconds
Started Aug 13 05:55:59 PM PDT 24
Finished Aug 13 05:57:18 PM PDT 24
Peak memory 253356 kb
Host smart-d546954f-4a3e-45e2-acc3-0d34a230b0eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764463253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3764463253 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.170118237
Short name T71
Test name
Test status
Simulation time 54305177960 ps
CPU time 767.45 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 06:08:46 PM PDT 24
Peak memory 240932 kb
Host smart-acaeaa4d-a739-4e2d-a721-b14da2f6382f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170118237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.170118237
+enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.2453887771
Short name T394
Test name
Test status
Simulation time 1947133082 ps
CPU time 39.46 seconds
Started Aug 13 05:56:04 PM PDT 24
Finished Aug 13 05:56:44 PM PDT 24
Peak memory 223440 kb
Host smart-dcb4fb34-2513-4a19-a635-f0d1baf827d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453887771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2453887771 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.241026938
Short name T351
Test name
Test status
Simulation time 998807380 ps
CPU time 5.59 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 05:56:10 PM PDT 24
Peak memory 215348 kb
Host smart-3945423e-ca19-4107-b1fb-f1fa7ff77ec9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=241026938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.241026938 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.1381528439
Short name T582
Test name
Test status
Simulation time 202085613727 ps
CPU time 393.55 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 06:02:32 PM PDT 24
Peak memory 483108 kb
Host smart-5e9d02a2-022e-4919-b507-346cb3ca06bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381528439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1
381528439 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.210447923
Short name T31
Test name
Test status
Simulation time 31375398042 ps
CPU time 377.83 seconds
Started Aug 13 05:55:57 PM PDT 24
Finished Aug 13 06:02:16 PM PDT 24
Peak memory 558084 kb
Host smart-3f78948f-0796-4084-ab63-cec7d7ae503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210447923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.210447923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.1156912849
Short name T318
Test name
Test status
Simulation time 1487428193 ps
CPU time 8.1 seconds
Started Aug 13 05:56:06 PM PDT 24
Finished Aug 13 05:56:14 PM PDT 24
Peak memory 217536 kb
Host smart-115ebd0c-f56e-4ca2-b8b1-2a7184d43f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156912849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1156912849 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.1019349915
Short name T6
Test name
Test status
Simulation time 136191144 ps
CPU time 4.58 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 05:56:10 PM PDT 24
Peak memory 222852 kb
Host smart-93d2a9cf-3ff7-44d8-b14c-a2eef65139b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019349915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1019349915 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3811312763
Short name T585
Test name
Test status
Simulation time 53337072680 ps
CPU time 471.62 seconds
Started Aug 13 05:55:57 PM PDT 24
Finished Aug 13 06:03:49 PM PDT 24
Peak memory 819408 kb
Host smart-364cda59-f66a-4dd2-993b-d05c8311a5ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811312763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3811312763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.3076300979
Short name T197
Test name
Test status
Simulation time 284339753 ps
CPU time 20.17 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 05:56:19 PM PDT 24
Peak memory 224128 kb
Host smart-8d1b4aa5-319e-4cf9-a9a4-627c3fe7d092
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076300979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3076300979 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.3720809030
Short name T706
Test name
Test status
Simulation time 2023057110 ps
CPU time 34.72 seconds
Started Aug 13 05:55:58 PM PDT 24
Finished Aug 13 05:56:33 PM PDT 24
Peak memory 217632 kb
Host smart-f22a47ca-ff9d-48ca-a663-b41828062307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720809030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3720809030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.4169511162
Short name T580
Test name
Test status
Simulation time 180227948574 ps
CPU time 1347.86 seconds
Started Aug 13 05:56:04 PM PDT 24
Finished Aug 13 06:18:32 PM PDT 24
Peak memory 1381092 kb
Host smart-761d372d-43b0-4fcc-a9a1-3da6d568daf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4169511162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.4169511162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_alert_test.848538545
Short name T384
Test name
Test status
Simulation time 15802478 ps
CPU time 0.77 seconds
Started Aug 13 05:56:10 PM PDT 24
Finished Aug 13 05:56:11 PM PDT 24
Peak memory 204840 kb
Host smart-d86cb391-2dc8-46dd-9c5b-0c3459d351e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848538545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.848538545 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.1416341996
Short name T657
Test name
Test status
Simulation time 50827293774 ps
CPU time 269.65 seconds
Started Aug 13 05:56:04 PM PDT 24
Finished Aug 13 06:00:34 PM PDT 24
Peak memory 434776 kb
Host smart-69b5ea3b-ffb9-4869-884d-63b8c705608f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416341996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1416341996 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.1004518794
Short name T598
Test name
Test status
Simulation time 2007891161 ps
CPU time 44.69 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 05:56:50 PM PDT 24
Peak memory 223812 kb
Host smart-5713b2c9-9453-47c0-af99-6b1a45e4ebd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004518794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.100451879
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.3983206116
Short name T214
Test name
Test status
Simulation time 2328827274 ps
CPU time 16.98 seconds
Started Aug 13 05:56:02 PM PDT 24
Finished Aug 13 05:56:19 PM PDT 24
Peak memory 223512 kb
Host smart-9709eab0-6283-4f28-9f72-8756a159e46d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3983206116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3983206116 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.629131803
Short name T229
Test name
Test status
Simulation time 72856442 ps
CPU time 5.37 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 05:56:10 PM PDT 24
Peak memory 215300 kb
Host smart-d5394b4a-7a45-486d-8fa5-0c4d81ea9b19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=629131803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.629131803 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.1616584854
Short name T551
Test name
Test status
Simulation time 2698775354 ps
CPU time 65.53 seconds
Started Aug 13 05:56:06 PM PDT 24
Finished Aug 13 05:57:12 PM PDT 24
Peak memory 243292 kb
Host smart-0fa05a3d-5f06-4060-962d-19be70df9510
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616584854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1
616584854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.3741085815
Short name T727
Test name
Test status
Simulation time 5587993301 ps
CPU time 54.83 seconds
Started Aug 13 05:56:04 PM PDT 24
Finished Aug 13 05:56:58 PM PDT 24
Peak memory 272900 kb
Host smart-a5faf4b7-22b9-401d-9aa3-cdca2cf16275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741085815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3741085815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.1627259290
Short name T58
Test name
Test status
Simulation time 1467867928 ps
CPU time 6.46 seconds
Started Aug 13 05:56:04 PM PDT 24
Finished Aug 13 05:56:11 PM PDT 24
Peak memory 217208 kb
Host smart-f3577bc3-dad8-405a-9b8b-f087f3e103c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627259290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1627259290 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.2364572964
Short name T711
Test name
Test status
Simulation time 99195472 ps
CPU time 1.29 seconds
Started Aug 13 05:56:07 PM PDT 24
Finished Aug 13 05:56:08 PM PDT 24
Peak memory 217712 kb
Host smart-7825aead-602b-4abf-a64b-f784b40ac203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364572964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2364572964 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.2465951923
Short name T216
Test name
Test status
Simulation time 63629183135 ps
CPU time 987.16 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 06:12:32 PM PDT 24
Peak memory 1336504 kb
Host smart-fbfeccdc-5e93-45a3-8dd3-a9d9aeaa168e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465951923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.2465951923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.195141237
Short name T141
Test name
Test status
Simulation time 31396040106 ps
CPU time 112.94 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 05:57:58 PM PDT 24
Peak memory 311360 kb
Host smart-fc87b157-007d-4ef6-ac99-9e67ab565243
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195141237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.195141237 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.2937043319
Short name T719
Test name
Test status
Simulation time 1465464903 ps
CPU time 51.04 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 05:56:57 PM PDT 24
Peak memory 217968 kb
Host smart-79e85d75-bbb5-4675-8f8f-62d1b0ecbbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937043319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2937043319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.3205745671
Short name T242
Test name
Test status
Simulation time 9997307770 ps
CPU time 749.58 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 06:08:34 PM PDT 24
Peak memory 577436 kb
Host smart-c690f52a-054c-465e-8839-3a3e431eb284
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3205745671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3205745671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_alert_test.1209630148
Short name T258
Test name
Test status
Simulation time 23499636 ps
CPU time 0.86 seconds
Started Aug 13 05:56:13 PM PDT 24
Finished Aug 13 05:56:14 PM PDT 24
Peak memory 204984 kb
Host smart-454d1bad-2aca-4c09-9af4-73f3165bedc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209630148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1209630148 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.3907599629
Short name T319
Test name
Test status
Simulation time 2420891934 ps
CPU time 16.12 seconds
Started Aug 13 05:56:07 PM PDT 24
Finished Aug 13 05:56:24 PM PDT 24
Peak memory 223840 kb
Host smart-63234899-c78a-41d7-ae4d-81f2c47a7547
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907599629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3907599629 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.2568662619
Short name T728
Test name
Test status
Simulation time 15894809685 ps
CPU time 797.02 seconds
Started Aug 13 05:56:07 PM PDT 24
Finished Aug 13 06:09:24 PM PDT 24
Peak memory 242316 kb
Host smart-65163529-a70e-48aa-bdd0-6703c37731c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568662619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.256866261
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.1986877805
Short name T648
Test name
Test status
Simulation time 1608868257 ps
CPU time 39.88 seconds
Started Aug 13 05:56:09 PM PDT 24
Finished Aug 13 05:56:49 PM PDT 24
Peak memory 220628 kb
Host smart-d9afe481-93b2-45a9-aa92-0ca3cb4d8f94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986877805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1986877805 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.411286702
Short name T225
Test name
Test status
Simulation time 25594787058 ps
CPU time 33.88 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:56:48 PM PDT 24
Peak memory 223564 kb
Host smart-25b12d2a-ba8d-4c83-9ae3-c2a088360d35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=411286702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.411286702 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.938106102
Short name T211
Test name
Test status
Simulation time 3153093943 ps
CPU time 73.89 seconds
Started Aug 13 05:56:07 PM PDT 24
Finished Aug 13 05:57:21 PM PDT 24
Peak memory 249616 kb
Host smart-ed51427f-24ba-4b5f-81d1-f8fede84c61b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938106102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.93
8106102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.3715171635
Short name T357
Test name
Test status
Simulation time 17960493270 ps
CPU time 99.13 seconds
Started Aug 13 05:56:08 PM PDT 24
Finished Aug 13 05:57:47 PM PDT 24
Peak memory 265208 kb
Host smart-6e37a537-2f59-4d48-978c-24d432081675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715171635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3715171635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.2002683898
Short name T557
Test name
Test status
Simulation time 1384647509 ps
CPU time 3.57 seconds
Started Aug 13 05:56:09 PM PDT 24
Finished Aug 13 05:56:13 PM PDT 24
Peak memory 217544 kb
Host smart-03b3d533-77a6-4d1e-a350-4f32a33a29d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002683898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2002683898 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.4076697982
Short name T54
Test name
Test status
Simulation time 44623297 ps
CPU time 1.53 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:56:15 PM PDT 24
Peak memory 223372 kb
Host smart-dc2c8c4b-76e7-4f6a-8941-107522279eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076697982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.4076697982 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.3800586008
Short name T532
Test name
Test status
Simulation time 25995383858 ps
CPU time 3004.56 seconds
Started Aug 13 05:56:05 PM PDT 24
Finished Aug 13 06:46:11 PM PDT 24
Peak memory 1798808 kb
Host smart-978e3c0a-7058-4f91-8735-d17ac7e0f720
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800586008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.3800586008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.2479016293
Short name T669
Test name
Test status
Simulation time 3711665532 ps
CPU time 75.91 seconds
Started Aug 13 05:56:10 PM PDT 24
Finished Aug 13 05:57:27 PM PDT 24
Peak memory 249988 kb
Host smart-da70b7c6-ab46-4d37-aded-a9899f5fc2d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479016293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2479016293 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.998555043
Short name T372
Test name
Test status
Simulation time 2119565631 ps
CPU time 44.47 seconds
Started Aug 13 05:56:06 PM PDT 24
Finished Aug 13 05:56:50 PM PDT 24
Peak memory 218552 kb
Host smart-f9c5b0d9-ac65-4fc7-9ead-0e67fd774515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998555043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.998555043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.2577714644
Short name T560
Test name
Test status
Simulation time 1910622967 ps
CPU time 159.86 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:58:54 PM PDT 24
Peak memory 280972 kb
Host smart-d2690694-f395-4b60-90f4-e9fa398423b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2577714644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2577714644 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_alert_test.1607222184
Short name T230
Test name
Test status
Simulation time 16427908 ps
CPU time 0.79 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:56:15 PM PDT 24
Peak memory 204800 kb
Host smart-b66d6ce9-507b-44d1-9361-c78ba06e2d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607222184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1607222184 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.3066341500
Short name T435
Test name
Test status
Simulation time 8453431887 ps
CPU time 193.49 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:59:28 PM PDT 24
Peak memory 371836 kb
Host smart-1a14150e-8642-4696-8009-ba93270cf3b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066341500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3066341500 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.4124084922
Short name T142
Test name
Test status
Simulation time 93157701384 ps
CPU time 880.19 seconds
Started Aug 13 05:56:12 PM PDT 24
Finished Aug 13 06:10:52 PM PDT 24
Peak memory 254624 kb
Host smart-b041fc71-f727-435d-b473-48b13d8a7aaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124084922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.412408492
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.3108920244
Short name T649
Test name
Test status
Simulation time 1024336012 ps
CPU time 14.42 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:56:28 PM PDT 24
Peak memory 223556 kb
Host smart-2a53e789-c521-4435-af3b-a53819cd31a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3108920244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3108920244 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.1704020898
Short name T231
Test name
Test status
Simulation time 1148527942 ps
CPU time 21.11 seconds
Started Aug 13 05:56:11 PM PDT 24
Finished Aug 13 05:56:32 PM PDT 24
Peak memory 223552 kb
Host smart-b6df4d52-73bf-4cbb-a743-f9191c416002
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1704020898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1704020898 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.998133012
Short name T358
Test name
Test status
Simulation time 344626134 ps
CPU time 7.74 seconds
Started Aug 13 05:56:12 PM PDT 24
Finished Aug 13 05:56:20 PM PDT 24
Peak memory 223028 kb
Host smart-16005424-e8c3-4747-a018-d2f6ff249845
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998133012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.99
8133012 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.1408090544
Short name T686
Test name
Test status
Simulation time 8497742070 ps
CPU time 63.59 seconds
Started Aug 13 05:56:19 PM PDT 24
Finished Aug 13 05:57:23 PM PDT 24
Peak memory 281124 kb
Host smart-8949237f-0311-4e08-b9ca-8a6dfc30bd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408090544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1408090544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.3708579411
Short name T376
Test name
Test status
Simulation time 5507229484 ps
CPU time 7.42 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:56:22 PM PDT 24
Peak memory 217708 kb
Host smart-004c5bc5-096c-4daf-ba72-022be4ffe784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708579411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3708579411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.1273081622
Short name T689
Test name
Test status
Simulation time 61872955 ps
CPU time 1.28 seconds
Started Aug 13 05:56:13 PM PDT 24
Finished Aug 13 05:56:15 PM PDT 24
Peak memory 218468 kb
Host smart-edf60333-7519-43d3-ae13-44948fe00d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273081622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1273081622 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.977570673
Short name T572
Test name
Test status
Simulation time 80141225688 ps
CPU time 1361.8 seconds
Started Aug 13 05:56:12 PM PDT 24
Finished Aug 13 06:18:54 PM PDT 24
Peak memory 1741088 kb
Host smart-401b5268-332d-4fe8-9642-7a04a645150e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977570673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_an
d_output.977570673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.2614794838
Short name T235
Test name
Test status
Simulation time 735110037 ps
CPU time 57.79 seconds
Started Aug 13 05:56:13 PM PDT 24
Finished Aug 13 05:57:10 PM PDT 24
Peak memory 243248 kb
Host smart-0b75e11e-c552-46cf-a8cb-8718f11d4e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614794838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2614794838 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.2536868469
Short name T382
Test name
Test status
Simulation time 12191082611 ps
CPU time 46.66 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:57:01 PM PDT 24
Peak memory 223872 kb
Host smart-4a202867-6407-4002-b6bd-a1c1fb65d838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536868469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2536868469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.3548020264
Short name T694
Test name
Test status
Simulation time 352247414397 ps
CPU time 2257.63 seconds
Started Aug 13 05:56:15 PM PDT 24
Finished Aug 13 06:33:53 PM PDT 24
Peak memory 1069416 kb
Host smart-92c3965b-38b5-4585-831f-7873311937f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3548020264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3548020264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_alert_test.992573407
Short name T467
Test name
Test status
Simulation time 23917998 ps
CPU time 0.81 seconds
Started Aug 13 05:56:23 PM PDT 24
Finished Aug 13 05:56:23 PM PDT 24
Peak memory 204896 kb
Host smart-1afc0e3d-82e0-4fa1-9eb8-23924867ca83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992573407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.992573407 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.4012986213
Short name T653
Test name
Test status
Simulation time 1041431879 ps
CPU time 66.79 seconds
Started Aug 13 05:56:13 PM PDT 24
Finished Aug 13 05:57:20 PM PDT 24
Peak memory 250360 kb
Host smart-3d75ad31-ee98-4e71-b1f4-ed8164425b8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012986213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.4012986213 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.455666725
Short name T343
Test name
Test status
Simulation time 27670385137 ps
CPU time 659.55 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 06:07:13 PM PDT 24
Peak memory 238476 kb
Host smart-2e9431cd-2bf4-4224-91f2-a0a0f2d68962
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455666725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.455666725
+enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.2010073305
Short name T352
Test name
Test status
Simulation time 383717541 ps
CPU time 24.56 seconds
Started Aug 13 05:56:21 PM PDT 24
Finished Aug 13 05:56:46 PM PDT 24
Peak memory 220844 kb
Host smart-50af95b5-fbd9-49ad-9b08-3a4cacb55d95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2010073305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2010073305 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.3304356409
Short name T632
Test name
Test status
Simulation time 1835010670 ps
CPU time 10.83 seconds
Started Aug 13 05:56:19 PM PDT 24
Finished Aug 13 05:56:30 PM PDT 24
Peak memory 221168 kb
Host smart-4e62ed69-db75-4e2d-8725-faa0ab14a3e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3304356409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3304356409 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.1574139642
Short name T203
Test name
Test status
Simulation time 28822239192 ps
CPU time 313.24 seconds
Started Aug 13 05:56:12 PM PDT 24
Finished Aug 13 06:01:25 PM PDT 24
Peak memory 355288 kb
Host smart-c77a6608-6b7f-4afd-9f5e-eb55d58b9839
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574139642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1
574139642 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.221581058
Short name T680
Test name
Test status
Simulation time 7710044898 ps
CPU time 229.94 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 06:00:04 PM PDT 24
Peak memory 429368 kb
Host smart-7c7108bc-51fc-4c11-a9da-ad07cccf35cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221581058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.221581058 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.3011170141
Short name T398
Test name
Test status
Simulation time 1230879496 ps
CPU time 3.81 seconds
Started Aug 13 05:56:23 PM PDT 24
Finished Aug 13 05:56:27 PM PDT 24
Peak memory 217516 kb
Host smart-f3691c86-dd42-4edb-a052-bdcfbbe17b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011170141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3011170141 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.474139
Short name T81
Test name
Test status
Simulation time 97234457 ps
CPU time 1.25 seconds
Started Aug 13 05:56:21 PM PDT 24
Finished Aug 13 05:56:23 PM PDT 24
Peak memory 218896 kb
Host smart-65667ca6-96d0-4182-af4f-ba8b814c5858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.474139 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2327583147
Short name T239
Test name
Test status
Simulation time 3067350749 ps
CPU time 135.89 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:58:30 PM PDT 24
Peak memory 309852 kb
Host smart-73613485-8fa2-4609-aa3e-f80955eb196f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327583147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2327583147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.3682549419
Short name T228
Test name
Test status
Simulation time 11951859680 ps
CPU time 269.26 seconds
Started Aug 13 05:56:13 PM PDT 24
Finished Aug 13 06:00:43 PM PDT 24
Peak memory 320588 kb
Host smart-727fd221-73f5-4dd0-a406-49c9197a32cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682549419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3682549419 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.2307417464
Short name T283
Test name
Test status
Simulation time 2150530741 ps
CPU time 48.71 seconds
Started Aug 13 05:56:14 PM PDT 24
Finished Aug 13 05:57:03 PM PDT 24
Peak memory 217804 kb
Host smart-29184b33-99be-40aa-9eaa-fa3ffb407b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307417464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2307417464 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.2523893000
Short name T48
Test name
Test status
Simulation time 326656135848 ps
CPU time 1120.12 seconds
Started Aug 13 05:56:23 PM PDT 24
Finished Aug 13 06:15:03 PM PDT 24
Peak memory 818212 kb
Host smart-09e8662e-a436-47fe-a0a3-b61d1d9d3c04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2523893000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2523893000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_alert_test.3711789030
Short name T524
Test name
Test status
Simulation time 50571901 ps
CPU time 0.82 seconds
Started Aug 13 05:56:23 PM PDT 24
Finished Aug 13 05:56:24 PM PDT 24
Peak memory 204880 kb
Host smart-7f20f05d-53ca-4aa8-9df0-bdc8dd8f4f5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711789030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3711789030 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.2979033751
Short name T311
Test name
Test status
Simulation time 41483055345 ps
CPU time 331.08 seconds
Started Aug 13 05:56:22 PM PDT 24
Finished Aug 13 06:01:53 PM PDT 24
Peak memory 495984 kb
Host smart-ef6b6ac8-eaf8-421f-9044-2897b357afa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979033751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2979033751 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.1146190425
Short name T707
Test name
Test status
Simulation time 7470350728 ps
CPU time 676.17 seconds
Started Aug 13 05:56:21 PM PDT 24
Finished Aug 13 06:07:38 PM PDT 24
Peak memory 239820 kb
Host smart-3157c833-4de0-4d3e-b3cb-c19af393279f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146190425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.114619042
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.2144008106
Short name T308
Test name
Test status
Simulation time 357593395 ps
CPU time 25.53 seconds
Started Aug 13 05:56:21 PM PDT 24
Finished Aug 13 05:56:47 PM PDT 24
Peak memory 223568 kb
Host smart-6a5cce43-40a4-4318-a23b-378511694877
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2144008106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2144008106 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.140624158
Short name T486
Test name
Test status
Simulation time 1088849183 ps
CPU time 15.22 seconds
Started Aug 13 05:56:21 PM PDT 24
Finished Aug 13 05:56:36 PM PDT 24
Peak memory 217580 kb
Host smart-f250a103-9577-457b-b2c7-28527303bdcd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=140624158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.140624158 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.2502902559
Short name T715
Test name
Test status
Simulation time 7657742426 ps
CPU time 188.54 seconds
Started Aug 13 05:56:20 PM PDT 24
Finished Aug 13 05:59:28 PM PDT 24
Peak memory 289816 kb
Host smart-9bdb34dc-463c-4ced-a2af-7af81a66bca5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502902559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2
502902559 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.3915180324
Short name T589
Test name
Test status
Simulation time 38790007288 ps
CPU time 441 seconds
Started Aug 13 05:56:22 PM PDT 24
Finished Aug 13 06:03:43 PM PDT 24
Peak memory 584548 kb
Host smart-db7cf255-f3e7-48af-b740-6a52095407e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915180324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3915180324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.2862401376
Short name T534
Test name
Test status
Simulation time 791489682 ps
CPU time 4.57 seconds
Started Aug 13 05:56:22 PM PDT 24
Finished Aug 13 05:56:26 PM PDT 24
Peak memory 217292 kb
Host smart-cae1a747-55d3-4c6e-8fd5-f0bc1c4fe54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862401376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2862401376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.407566264
Short name T519
Test name
Test status
Simulation time 24972278 ps
CPU time 1.17 seconds
Started Aug 13 05:56:22 PM PDT 24
Finished Aug 13 05:56:24 PM PDT 24
Peak memory 218720 kb
Host smart-0fd9581d-41fb-44f8-b7e2-dd79f02f2d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407566264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.407566264 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.2363934367
Short name T297
Test name
Test status
Simulation time 104367503923 ps
CPU time 795.93 seconds
Started Aug 13 05:56:23 PM PDT 24
Finished Aug 13 06:09:39 PM PDT 24
Peak memory 1180384 kb
Host smart-8e70796e-96c1-4bae-9098-6c8a92c30542
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363934367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.2363934367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2634272685
Short name T714
Test name
Test status
Simulation time 2111172365 ps
CPU time 170.93 seconds
Started Aug 13 05:56:22 PM PDT 24
Finished Aug 13 05:59:14 PM PDT 24
Peak memory 296020 kb
Host smart-db183767-7f32-4355-99d2-164ff4f373c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634272685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2634272685 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.2663049422
Short name T624
Test name
Test status
Simulation time 374334457 ps
CPU time 20.39 seconds
Started Aug 13 05:56:19 PM PDT 24
Finished Aug 13 05:56:39 PM PDT 24
Peak memory 217956 kb
Host smart-666c0229-8cf9-40fc-88f8-f814bbff0c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663049422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2663049422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.2554094193
Short name T68
Test name
Test status
Simulation time 68884047675 ps
CPU time 1160.48 seconds
Started Aug 13 05:56:22 PM PDT 24
Finished Aug 13 06:15:43 PM PDT 24
Peak memory 1491496 kb
Host smart-a4602591-f073-43f3-8baf-e8359fe59eb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2554094193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2554094193 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_alert_test.1503498219
Short name T554
Test name
Test status
Simulation time 411956098 ps
CPU time 0.94 seconds
Started Aug 13 05:55:04 PM PDT 24
Finished Aug 13 05:55:05 PM PDT 24
Peak memory 204976 kb
Host smart-eab7cc65-ec15-4104-a386-c34aadc5b28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503498219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1503498219 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.423258462
Short name T215
Test name
Test status
Simulation time 4587947258 ps
CPU time 238.8 seconds
Started Aug 13 05:55:10 PM PDT 24
Finished Aug 13 05:59:09 PM PDT 24
Peak memory 316484 kb
Host smart-0b127191-2475-4d47-8edf-d74d0469d362
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423258462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.423258462 +enable_masking=0
+sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2132349760
Short name T626
Test name
Test status
Simulation time 11243966767 ps
CPU time 300.13 seconds
Started Aug 13 05:55:02 PM PDT 24
Finished Aug 13 06:00:02 PM PDT 24
Peak memory 467284 kb
Host smart-96281749-5b68-4e78-a05f-e5f96a1deacd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132349760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.2132349760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2219830964
Short name T503
Test name
Test status
Simulation time 40022767684 ps
CPU time 498.46 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 06:03:25 PM PDT 24
Peak memory 240448 kb
Host smart-b2d39024-d85b-4ed3-bb44-f054b5f81f49
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219830964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2219830964
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.415144915
Short name T217
Test name
Test status
Simulation time 195838005 ps
CPU time 5.3 seconds
Started Aug 13 05:55:08 PM PDT 24
Finished Aug 13 05:55:13 PM PDT 24
Peak memory 217356 kb
Host smart-29c16304-b850-4bed-9ac9-7f4a4496fb5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=415144915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.415144915 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.2581450313
Short name T265
Test name
Test status
Simulation time 45436586 ps
CPU time 1.67 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 05:55:08 PM PDT 24
Peak memory 215424 kb
Host smart-732dc530-eeaa-43c8-b12f-b879805254ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2581450313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2581450313 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.3001277922
Short name T655
Test name
Test status
Simulation time 12809138133 ps
CPU time 56.46 seconds
Started Aug 13 05:55:08 PM PDT 24
Finished Aug 13 05:56:04 PM PDT 24
Peak memory 219160 kb
Host smart-6b4e4bdb-6cb3-48ad-994e-539c3d78c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001277922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3001277922 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.2939336501
Short name T530
Test name
Test status
Simulation time 9914687711 ps
CPU time 227.69 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:58:53 PM PDT 24
Peak memory 418660 kb
Host smart-e784905f-1d79-4a97-a73e-77aa4ff70f14
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939336501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.29
39336501 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.572411933
Short name T635
Test name
Test status
Simulation time 791157674 ps
CPU time 56.37 seconds
Started Aug 13 05:55:06 PM PDT 24
Finished Aug 13 05:56:02 PM PDT 24
Peak memory 250096 kb
Host smart-3f53060d-1f15-469c-aa3a-636727af17a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572411933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.572411933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.3023712999
Short name T411
Test name
Test status
Simulation time 10173961837 ps
CPU time 7.59 seconds
Started Aug 13 05:55:08 PM PDT 24
Finished Aug 13 05:55:15 PM PDT 24
Peak memory 217892 kb
Host smart-50eb1bdd-421f-4856-a7c1-ef0d3939c4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023712999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3023712999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.3676746892
Short name T666
Test name
Test status
Simulation time 75508755 ps
CPU time 1.41 seconds
Started Aug 13 05:55:10 PM PDT 24
Finished Aug 13 05:55:12 PM PDT 24
Peak memory 223248 kb
Host smart-a6f85c26-1d3d-40a2-88ca-43568f89fff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676746892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3676746892 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.331943261
Short name T690
Test name
Test status
Simulation time 71440623264 ps
CPU time 322.62 seconds
Started Aug 13 05:55:04 PM PDT 24
Finished Aug 13 06:00:27 PM PDT 24
Peak memory 624952 kb
Host smart-294d29f2-e6eb-49bf-807c-4cbde62c6b5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331943261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and
_output.331943261 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.3465252369
Short name T349
Test name
Test status
Simulation time 13335340412 ps
CPU time 378.31 seconds
Started Aug 13 05:55:08 PM PDT 24
Finished Aug 13 06:01:27 PM PDT 24
Peak memory 530552 kb
Host smart-d32a9954-727c-4162-89aa-9917e2cb72eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465252369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3465252369 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.2145641548
Short name T13
Test name
Test status
Simulation time 1466807383 ps
CPU time 22.46 seconds
Started Aug 13 05:55:06 PM PDT 24
Finished Aug 13 05:55:28 PM PDT 24
Peak memory 241628 kb
Host smart-168ce56d-2e74-416e-90cf-550ed566cdf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145641548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2145641548 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.1977789052
Short name T233
Test name
Test status
Simulation time 24339342225 ps
CPU time 323.7 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 06:00:31 PM PDT 24
Peak memory 479796 kb
Host smart-2db0f7a5-c82b-439d-834d-ba0607e7cf19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977789052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1977789052 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3132760664
Short name T643
Test name
Test status
Simulation time 2718666954 ps
CPU time 22.69 seconds
Started Aug 13 05:55:04 PM PDT 24
Finished Aug 13 05:55:26 PM PDT 24
Peak memory 218244 kb
Host smart-4f5a24c7-7081-4ed3-9b06-0eb52a3b04ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132760664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3132760664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.3131102066
Short name T336
Test name
Test status
Simulation time 663652639 ps
CPU time 31.2 seconds
Started Aug 13 05:55:06 PM PDT 24
Finished Aug 13 05:55:37 PM PDT 24
Peak memory 231404 kb
Host smart-11dcb4d5-934c-49d3-af19-8b39351fb86f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3131102066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3131102066 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.3223878911
Short name T696
Test name
Test status
Simulation time 40828057 ps
CPU time 2.53 seconds
Started Aug 13 05:55:04 PM PDT 24
Finished Aug 13 05:55:06 PM PDT 24
Peak memory 217712 kb
Host smart-d8b744c9-c1c9-4f5d-8eec-a4e600ea6408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223878911 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.3223878911 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3736427904
Short name T263
Test name
Test status
Simulation time 35264381 ps
CPU time 2.65 seconds
Started Aug 13 05:55:09 PM PDT 24
Finished Aug 13 05:55:12 PM PDT 24
Peak memory 217576 kb
Host smart-9bd5ed8d-aa39-45ff-a5b0-ddc7eac3613c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736427904 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3736427904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.2845528508
Short name T627
Test name
Test status
Simulation time 2262706111 ps
CPU time 38.51 seconds
Started Aug 13 05:55:02 PM PDT 24
Finished Aug 13 05:55:41 PM PDT 24
Peak memory 219844 kb
Host smart-83be03e7-b7e7-4c1a-8311-d83457f8a50a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2845528508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2845528508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.298121242
Short name T66
Test name
Test status
Simulation time 3147174046 ps
CPU time 36.15 seconds
Started Aug 13 05:55:09 PM PDT 24
Finished Aug 13 05:55:45 PM PDT 24
Peak memory 219280 kb
Host smart-548c081f-5e45-44cd-b901-32a97e2e46a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=298121242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.298121242 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.3975766080
Short name T542
Test name
Test status
Simulation time 13126628778 ps
CPU time 1270.58 seconds
Started Aug 13 05:55:09 PM PDT 24
Finished Aug 13 06:16:19 PM PDT 24
Peak memory 908108 kb
Host smart-24d0bd4a-020c-45cb-afc8-8d9f2fe84916
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3975766080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3975766080 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1365315327
Short name T108
Test name
Test status
Simulation time 274826069 ps
CPU time 14.67 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:55:19 PM PDT 24
Peak memory 216876 kb
Host smart-bfdeeda9-cc8e-48cd-87d6-2139fbc051e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1365315327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1365315327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.1946552580
Short name T191
Test name
Test status
Simulation time 14303961894 ps
CPU time 242.91 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:59:08 PM PDT 24
Peak memory 270184 kb
Host smart-804c7421-2e3b-4958-b159-1d43ac02433d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1946552580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1946552580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.525529315
Short name T502
Test name
Test status
Simulation time 5695239331 ps
CPU time 306.66 seconds
Started Aug 13 05:55:10 PM PDT 24
Finished Aug 13 06:00:17 PM PDT 24
Peak memory 253756 kb
Host smart-19148c6b-2e0f-4b65-9ce8-229f24e2d157
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=525529315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.525529315 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.3026017154
Short name T612
Test name
Test status
Simulation time 39031145 ps
CPU time 0.76 seconds
Started Aug 13 05:56:29 PM PDT 24
Finished Aug 13 05:56:30 PM PDT 24
Peak memory 204888 kb
Host smart-4960bd8f-2e6f-436a-8be8-33365846aa9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026017154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3026017154 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.1240598895
Short name T101
Test name
Test status
Simulation time 113318350 ps
CPU time 6.48 seconds
Started Aug 13 05:56:23 PM PDT 24
Finished Aug 13 05:56:29 PM PDT 24
Peak memory 221680 kb
Host smart-4c509ed5-0319-4205-9490-4a192c34a28f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240598895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1240598895 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.1235812406
Short name T656
Test name
Test status
Simulation time 3621846210 ps
CPU time 366.17 seconds
Started Aug 13 05:56:21 PM PDT 24
Finished Aug 13 06:02:27 PM PDT 24
Peak memory 231628 kb
Host smart-5ba74f47-a353-44eb-9147-192a5dbdf876
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235812406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.123581240
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.4272944612
Short name T163
Test name
Test status
Simulation time 9412145494 ps
CPU time 288.91 seconds
Started Aug 13 05:56:22 PM PDT 24
Finished Aug 13 06:01:11 PM PDT 24
Peak memory 327116 kb
Host smart-3b04948b-6b97-485d-a81a-4d39433436e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272944612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4
272944612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.3530199647
Short name T593
Test name
Test status
Simulation time 59539673292 ps
CPU time 483.23 seconds
Started Aug 13 05:56:21 PM PDT 24
Finished Aug 13 06:04:25 PM PDT 24
Peak memory 606604 kb
Host smart-bb25ede7-e33f-49cb-b934-6512f47d47ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530199647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3530199647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.3807045519
Short name T21
Test name
Test status
Simulation time 881176999 ps
CPU time 4.71 seconds
Started Aug 13 05:56:22 PM PDT 24
Finished Aug 13 05:56:27 PM PDT 24
Peak memory 217408 kb
Host smart-93000227-8787-413a-a2be-24579cded392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807045519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3807045519 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.2001764812
Short name T576
Test name
Test status
Simulation time 3911555893 ps
CPU time 44.05 seconds
Started Aug 13 05:56:30 PM PDT 24
Finished Aug 13 05:57:14 PM PDT 24
Peak memory 249736 kb
Host smart-a0eeb040-ba2a-48a3-8ecf-8a258926facb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001764812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2001764812 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1600125854
Short name T477
Test name
Test status
Simulation time 55752716425 ps
CPU time 2878.33 seconds
Started Aug 13 05:56:21 PM PDT 24
Finished Aug 13 06:44:20 PM PDT 24
Peak memory 2742756 kb
Host smart-adcb7a0a-21b7-4202-8f6b-ec83457684c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600125854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1600125854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.1211806943
Short name T267
Test name
Test status
Simulation time 9320926202 ps
CPU time 59.46 seconds
Started Aug 13 05:56:20 PM PDT 24
Finished Aug 13 05:57:20 PM PDT 24
Peak memory 272016 kb
Host smart-e66b3cd9-57fc-4da9-959d-c79eb5106346
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211806943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1211806943 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.838787321
Short name T550
Test name
Test status
Simulation time 3927171690 ps
CPU time 62.46 seconds
Started Aug 13 05:56:23 PM PDT 24
Finished Aug 13 05:57:26 PM PDT 24
Peak memory 222252 kb
Host smart-9df1c3ec-d740-4927-8616-a955371158a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838787321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.838787321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_alert_test.726596826
Short name T107
Test name
Test status
Simulation time 17402399 ps
CPU time 0.8 seconds
Started Aug 13 05:56:30 PM PDT 24
Finished Aug 13 05:56:31 PM PDT 24
Peak memory 204952 kb
Host smart-4ee66d20-1eca-4646-99bf-ceb38d1a6657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726596826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.726596826 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.2555408728
Short name T222
Test name
Test status
Simulation time 1091673817 ps
CPU time 17.41 seconds
Started Aug 13 05:56:29 PM PDT 24
Finished Aug 13 05:56:47 PM PDT 24
Peak memory 220740 kb
Host smart-af6162e9-3472-4fa5-ac60-e3f48695d5e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555408728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2555408728 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.3316626
Short name T149
Test name
Test status
Simulation time 6304286252 ps
CPU time 232.92 seconds
Started Aug 13 05:56:31 PM PDT 24
Finished Aug 13 06:00:24 PM PDT 24
Peak memory 228088 kb
Host smart-a3f1ad0d-79d7-4276-af6e-57654369bb6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3316626 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.4112020987
Short name T26
Test name
Test status
Simulation time 9225551645 ps
CPU time 109.21 seconds
Started Aug 13 05:56:30 PM PDT 24
Finished Aug 13 05:58:19 PM PDT 24
Peak memory 259472 kb
Host smart-9f831245-d115-496a-9a65-c31ccee51355
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112020987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.4
112020987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.4127577733
Short name T168
Test name
Test status
Simulation time 21029191677 ps
CPU time 314.24 seconds
Started Aug 13 05:56:36 PM PDT 24
Finished Aug 13 06:01:51 PM PDT 24
Peak memory 494960 kb
Host smart-e8e6f45f-be8d-44f6-bcd3-ad12af0f2f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127577733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.4127577733 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.497051598
Short name T682
Test name
Test status
Simulation time 760067538 ps
CPU time 3.8 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 05:56:41 PM PDT 24
Peak memory 217360 kb
Host smart-e1757316-ea5c-4648-a2f6-84f5f64abba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497051598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.497051598 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.2985673646
Short name T33
Test name
Test status
Simulation time 53648101 ps
CPU time 1.42 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 05:56:38 PM PDT 24
Peak memory 218704 kb
Host smart-04701a3a-02ba-4a25-98d4-2fbe606c23a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985673646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2985673646 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.471480217
Short name T606
Test name
Test status
Simulation time 8250561810 ps
CPU time 819.18 seconds
Started Aug 13 05:56:30 PM PDT 24
Finished Aug 13 06:10:09 PM PDT 24
Peak memory 736580 kb
Host smart-45842243-fb42-4e76-bc11-3df25113c794
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471480217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_an
d_output.471480217 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.2517909665
Short name T668
Test name
Test status
Simulation time 3857039220 ps
CPU time 306.99 seconds
Started Aug 13 05:56:29 PM PDT 24
Finished Aug 13 06:01:36 PM PDT 24
Peak memory 340236 kb
Host smart-3be04341-bb82-4332-9c4d-2bb7953bfdb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517909665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2517909665 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.2166342858
Short name T674
Test name
Test status
Simulation time 108840486 ps
CPU time 1.34 seconds
Started Aug 13 05:56:27 PM PDT 24
Finished Aug 13 05:56:29 PM PDT 24
Peak memory 217800 kb
Host smart-8dbb2c4b-3386-450a-a094-885e8b711915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166342858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2166342858 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_alert_test.1863734100
Short name T638
Test name
Test status
Simulation time 49440650 ps
CPU time 0.75 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 05:56:38 PM PDT 24
Peak memory 204936 kb
Host smart-7e6dfe28-ec6b-45fb-a130-3ba0835a91bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863734100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1863734100 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3591214492
Short name T517
Test name
Test status
Simulation time 36852946290 ps
CPU time 190.81 seconds
Started Aug 13 05:56:31 PM PDT 24
Finished Aug 13 05:59:42 PM PDT 24
Peak memory 378300 kb
Host smart-4bb74e75-d84e-4af2-84dd-4e37ebe7f987
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591214492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3591214492 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.3002338750
Short name T702
Test name
Test status
Simulation time 14903177651 ps
CPU time 316.5 seconds
Started Aug 13 05:56:28 PM PDT 24
Finished Aug 13 06:01:45 PM PDT 24
Peak memory 235404 kb
Host smart-e41279a2-7ef2-4a52-89e7-9550ff0efa6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002338750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.300233875
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.3027059012
Short name T289
Test name
Test status
Simulation time 414503153 ps
CPU time 9.62 seconds
Started Aug 13 05:56:30 PM PDT 24
Finished Aug 13 05:56:39 PM PDT 24
Peak memory 223776 kb
Host smart-0ea9183c-e7be-487e-9b02-af55eb3a21e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027059012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3
027059012 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.226409491
Short name T304
Test name
Test status
Simulation time 1612759305 ps
CPU time 51.21 seconds
Started Aug 13 05:56:28 PM PDT 24
Finished Aug 13 05:57:19 PM PDT 24
Peak memory 267596 kb
Host smart-2b9e8769-e696-4861-be8e-62945af12189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226409491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.226409491 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.4119107334
Short name T599
Test name
Test status
Simulation time 1233824572 ps
CPU time 6.44 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 05:56:44 PM PDT 24
Peak memory 217336 kb
Host smart-7b130172-74fd-4d57-b81c-fd3dc3b49218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119107334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.4119107334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.350950380
Short name T9
Test name
Test status
Simulation time 18666928871 ps
CPU time 42.36 seconds
Started Aug 13 05:56:44 PM PDT 24
Finished Aug 13 05:57:26 PM PDT 24
Peak memory 248344 kb
Host smart-7db1f3b9-9b37-4534-aaa0-90eeb5ec7477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350950380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.350950380 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.3815939750
Short name T221
Test name
Test status
Simulation time 287878360176 ps
CPU time 1464.78 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 06:21:03 PM PDT 24
Peak memory 1707960 kb
Host smart-0c5ec942-f2b1-472a-8681-7c639061047f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815939750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.3815939750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3792646589
Short name T111
Test name
Test status
Simulation time 3466726815 ps
CPU time 66.72 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 05:57:44 PM PDT 24
Peak memory 248444 kb
Host smart-f42ba86d-bd27-4bc0-bbb1-9c73812ae105
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792646589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3792646589 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.3366205418
Short name T383
Test name
Test status
Simulation time 7225264771 ps
CPU time 38.7 seconds
Started Aug 13 05:56:27 PM PDT 24
Finished Aug 13 05:57:06 PM PDT 24
Peak memory 223820 kb
Host smart-3379a9e1-a5d4-4175-975d-3be32a032bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366205418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3366205418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.3706379896
Short name T270
Test name
Test status
Simulation time 53948785232 ps
CPU time 1966.97 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 06:29:25 PM PDT 24
Peak memory 1301528 kb
Host smart-7813dc84-f959-47c8-b59c-33f769523d3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3706379896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3706379896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_alert_test.2452265617
Short name T665
Test name
Test status
Simulation time 25301331 ps
CPU time 0.83 seconds
Started Aug 13 05:56:39 PM PDT 24
Finished Aug 13 05:56:40 PM PDT 24
Peak memory 204972 kb
Host smart-eda5d4ce-907c-47f4-8289-11af011db2fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452265617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2452265617 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.3670163474
Short name T607
Test name
Test status
Simulation time 3453189196 ps
CPU time 162.3 seconds
Started Aug 13 05:56:39 PM PDT 24
Finished Aug 13 05:59:21 PM PDT 24
Peak memory 282636 kb
Host smart-b240a3ad-b229-4eab-82bd-82fcb616b5c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670163474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3670163474 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.3568784683
Short name T650
Test name
Test status
Simulation time 37098166935 ps
CPU time 559.67 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 06:05:57 PM PDT 24
Peak memory 244364 kb
Host smart-9abce13a-075f-45b7-97b9-a73ab6083f0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568784683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.356878468
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.3652094606
Short name T396
Test name
Test status
Simulation time 43290691992 ps
CPU time 127.28 seconds
Started Aug 13 05:56:44 PM PDT 24
Finished Aug 13 05:58:51 PM PDT 24
Peak memory 319176 kb
Host smart-fa5ca0bc-e86f-4fec-afeb-7e4b88789590
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652094606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3
652094606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.1557897786
Short name T379
Test name
Test status
Simulation time 3823164302 ps
CPU time 301.92 seconds
Started Aug 13 05:56:38 PM PDT 24
Finished Aug 13 06:01:40 PM PDT 24
Peak memory 354652 kb
Host smart-5a482898-bb2a-4f2a-af6d-cc3168b1c30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557897786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1557897786 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.2654504694
Short name T611
Test name
Test status
Simulation time 476312034 ps
CPU time 3.19 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 05:56:40 PM PDT 24
Peak memory 217428 kb
Host smart-e57c5caf-9c15-4120-aa8a-ef30318a5859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654504694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2654504694 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3994396231
Short name T471
Test name
Test status
Simulation time 58164537 ps
CPU time 1.34 seconds
Started Aug 13 05:56:39 PM PDT 24
Finished Aug 13 05:56:40 PM PDT 24
Peak memory 216996 kb
Host smart-864254b7-8268-4225-a066-3823fdbdb830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994396231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3994396231 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_sideload.3582511107
Short name T474
Test name
Test status
Simulation time 597670217 ps
CPU time 45.04 seconds
Started Aug 13 05:56:38 PM PDT 24
Finished Aug 13 05:57:23 PM PDT 24
Peak memory 237016 kb
Host smart-7a48e7e0-5f0b-4597-b7ae-9adf60ab4457
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582511107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3582511107 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.3761517608
Short name T508
Test name
Test status
Simulation time 3427968348 ps
CPU time 41.9 seconds
Started Aug 13 05:56:44 PM PDT 24
Finished Aug 13 05:57:26 PM PDT 24
Peak memory 218072 kb
Host smart-9c1f2322-1e55-4998-b5ef-ac6098dee467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761517608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3761517608 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.1987486389
Short name T505
Test name
Test status
Simulation time 110531060 ps
CPU time 2.65 seconds
Started Aug 13 05:56:35 PM PDT 24
Finished Aug 13 05:56:38 PM PDT 24
Peak memory 218080 kb
Host smart-3d661635-b157-42c8-ac24-59717a36c9c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1987486389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1987486389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_alert_test.928225001
Short name T113
Test name
Test status
Simulation time 142139010 ps
CPU time 0.81 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 05:57:03 PM PDT 24
Peak memory 204936 kb
Host smart-2a8e66a4-ac0c-4297-9c46-3f5f6fd24e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928225001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.928225001 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.1267566050
Short name T718
Test name
Test status
Simulation time 5127985488 ps
CPU time 77.39 seconds
Started Aug 13 05:56:38 PM PDT 24
Finished Aug 13 05:57:55 PM PDT 24
Peak memory 253676 kb
Host smart-138daa6f-a506-49a3-9a98-f45ea24e829f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267566050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1267566050 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.1805025735
Short name T685
Test name
Test status
Simulation time 134398251463 ps
CPU time 989.77 seconds
Started Aug 13 05:56:39 PM PDT 24
Finished Aug 13 06:13:09 PM PDT 24
Peak memory 260296 kb
Host smart-1ae570ce-0194-48d5-a542-03d465dea408
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805025735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.180502573
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.1237321128
Short name T309
Test name
Test status
Simulation time 10635893426 ps
CPU time 264.49 seconds
Started Aug 13 05:56:39 PM PDT 24
Finished Aug 13 06:01:04 PM PDT 24
Peak memory 332456 kb
Host smart-44c61da6-f2fa-4334-b0aa-748807578401
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237321128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1
237321128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.4143795925
Short name T391
Test name
Test status
Simulation time 13863839230 ps
CPU time 282.58 seconds
Started Aug 13 05:56:38 PM PDT 24
Finished Aug 13 06:01:20 PM PDT 24
Peak memory 339256 kb
Host smart-b61268dd-35c2-4136-bcb9-b969e945cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143795925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.4143795925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.3975058134
Short name T601
Test name
Test status
Simulation time 1051389498 ps
CPU time 6.54 seconds
Started Aug 13 05:56:38 PM PDT 24
Finished Aug 13 05:56:44 PM PDT 24
Peak memory 217820 kb
Host smart-8dea1a75-72a0-48fd-a976-7f421e162bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975058134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3975058134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.2347711328
Short name T35
Test name
Test status
Simulation time 36584394 ps
CPU time 1.42 seconds
Started Aug 13 05:56:39 PM PDT 24
Finished Aug 13 05:56:40 PM PDT 24
Peak memory 218528 kb
Host smart-018442d7-141f-4558-affd-9941eb0568f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347711328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2347711328 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.389892981
Short name T73
Test name
Test status
Simulation time 76119019392 ps
CPU time 2841.21 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 06:43:59 PM PDT 24
Peak memory 1584408 kb
Host smart-9c582e26-6c02-4b15-b962-0fcb504b4275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389892981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an
d_output.389892981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.2614852365
Short name T417
Test name
Test status
Simulation time 5331601197 ps
CPU time 114.84 seconds
Started Aug 13 05:56:37 PM PDT 24
Finished Aug 13 05:58:32 PM PDT 24
Peak memory 266756 kb
Host smart-2295779a-18d5-40d2-9a3a-06b020c84565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614852365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2614852365 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.2588812475
Short name T395
Test name
Test status
Simulation time 532623992 ps
CPU time 24.86 seconds
Started Aug 13 05:56:44 PM PDT 24
Finished Aug 13 05:57:09 PM PDT 24
Peak memory 217944 kb
Host smart-9891bc57-9575-4d4a-9c7b-0d175487be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588812475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2588812475 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.3392175651
Short name T247
Test name
Test status
Simulation time 53515962691 ps
CPU time 490.61 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 06:05:13 PM PDT 24
Peak memory 372184 kb
Host smart-94d2e666-6f7f-4c31-a58c-166a88f9acfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3392175651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3392175651 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_alert_test.236619221
Short name T2
Test name
Test status
Simulation time 62627342 ps
CPU time 0.81 seconds
Started Aug 13 05:57:03 PM PDT 24
Finished Aug 13 05:57:04 PM PDT 24
Peak memory 204944 kb
Host smart-a13748df-1c20-4946-93ec-546012605df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236619221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.236619221 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.3254628285
Short name T292
Test name
Test status
Simulation time 6480228422 ps
CPU time 178.31 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 05:59:59 PM PDT 24
Peak memory 365140 kb
Host smart-26a2eb06-fd57-4e55-a32a-f613c8dacb14
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254628285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3254628285 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.4077361635
Short name T15
Test name
Test status
Simulation time 8785157543 ps
CPU time 401.38 seconds
Started Aug 13 05:57:03 PM PDT 24
Finished Aug 13 06:03:44 PM PDT 24
Peak memory 232284 kb
Host smart-c4b0d2a2-816d-44ff-a13f-1cbc53f7d2bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077361635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.407736163
5 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.360933069
Short name T109
Test name
Test status
Simulation time 15501391337 ps
CPU time 325.76 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 06:02:28 PM PDT 24
Peak memory 488352 kb
Host smart-1b7c7a3e-ba81-4c8c-a278-24edc394a3c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360933069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.36
0933069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.1260424467
Short name T418
Test name
Test status
Simulation time 579084154 ps
CPU time 46.09 seconds
Started Aug 13 05:57:03 PM PDT 24
Finished Aug 13 05:57:49 PM PDT 24
Peak memory 240288 kb
Host smart-fabff0b2-2c66-48d7-bf99-a0f10b202ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260424467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1260424467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.3608763850
Short name T681
Test name
Test status
Simulation time 4953143412 ps
CPU time 7.22 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 05:57:09 PM PDT 24
Peak memory 218640 kb
Host smart-eedec241-c67e-4a23-b19c-929accb86452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608763850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3608763850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.4201436962
Short name T704
Test name
Test status
Simulation time 9236104545 ps
CPU time 441.09 seconds
Started Aug 13 05:57:00 PM PDT 24
Finished Aug 13 06:04:21 PM PDT 24
Peak memory 520532 kb
Host smart-da6fb7ac-306b-4bd3-9543-ed0c5f557b7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201436962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.4201436962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.2399697490
Short name T661
Test name
Test status
Simulation time 8800066440 ps
CPU time 287.21 seconds
Started Aug 13 05:57:00 PM PDT 24
Finished Aug 13 06:01:47 PM PDT 24
Peak memory 449756 kb
Host smart-064a19a9-1582-41b7-a3f5-ae949932a048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399697490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2399697490 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.1384529389
Short name T496
Test name
Test status
Simulation time 1037968738 ps
CPU time 19.31 seconds
Started Aug 13 05:56:56 PM PDT 24
Finished Aug 13 05:57:15 PM PDT 24
Peak memory 218044 kb
Host smart-5c925044-6fc0-4970-a9a3-ba0deb971c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384529389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1384529389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.2131886609
Short name T76
Test name
Test status
Simulation time 50317966884 ps
CPU time 1450.13 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 06:21:14 PM PDT 24
Peak memory 1461568 kb
Host smart-9931f655-131f-46fe-afc8-c60ae204f894
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2131886609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2131886609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_alert_test.3238639440
Short name T43
Test name
Test status
Simulation time 18157212 ps
CPU time 0.8 seconds
Started Aug 13 05:57:00 PM PDT 24
Finished Aug 13 05:57:00 PM PDT 24
Peak memory 204924 kb
Host smart-05d67c09-8f45-4952-af9f-95de4c586957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238639440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3238639440 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.771312494
Short name T399
Test name
Test status
Simulation time 166182531 ps
CPU time 3.75 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 05:57:08 PM PDT 24
Peak memory 220992 kb
Host smart-e32dfede-8aed-43bf-ae5d-4b3fd9bfd09a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771312494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.771312494 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.62839576
Short name T416
Test name
Test status
Simulation time 11352164233 ps
CPU time 74.92 seconds
Started Aug 13 05:57:00 PM PDT 24
Finished Aug 13 05:58:15 PM PDT 24
Peak memory 221072 kb
Host smart-319ffc58-3919-44ce-8c33-9240bb89b921
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62839576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.62839576 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.2141363792
Short name T255
Test name
Test status
Simulation time 5866693892 ps
CPU time 41.17 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 05:57:43 PM PDT 24
Peak memory 240236 kb
Host smart-ca7969e5-1890-4a2d-888e-ff93bb2860fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141363792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2
141363792 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.1070830142
Short name T29
Test name
Test status
Simulation time 9040292383 ps
CPU time 230.23 seconds
Started Aug 13 05:57:03 PM PDT 24
Finished Aug 13 06:00:53 PM PDT 24
Peak memory 408408 kb
Host smart-94bbdc96-10b8-4eff-b82b-44b51fc5b36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070830142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1070830142 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.3190983734
Short name T465
Test name
Test status
Simulation time 1769839686 ps
CPU time 9.15 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 05:57:11 PM PDT 24
Peak memory 218744 kb
Host smart-e62bf6b4-8bb0-43d9-a1b4-2735c10d7c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190983734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3190983734 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.2915930341
Short name T106
Test name
Test status
Simulation time 175181792 ps
CPU time 1.52 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 05:57:04 PM PDT 24
Peak memory 217688 kb
Host smart-372c605f-e398-473b-b7ad-a63639d57274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915930341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2915930341 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_sideload.3296822050
Short name T691
Test name
Test status
Simulation time 49936354713 ps
CPU time 402.87 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 06:03:44 PM PDT 24
Peak memory 549232 kb
Host smart-7696bc87-f4e5-477c-acf1-e91b12a75612
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296822050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3296822050 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3299061902
Short name T317
Test name
Test status
Simulation time 1101935110 ps
CPU time 12.41 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 05:57:15 PM PDT 24
Peak memory 220620 kb
Host smart-e454255e-a531-4493-8557-a2b75a24b1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299061902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3299061902 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.2391202497
Short name T353
Test name
Test status
Simulation time 54142801167 ps
CPU time 129.18 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 05:59:10 PM PDT 24
Peak memory 297796 kb
Host smart-1ef7c74c-0914-4b8e-ba2a-898ca70e0bd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2391202497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2391202497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_alert_test.2002770367
Short name T466
Test name
Test status
Simulation time 44813783 ps
CPU time 0.79 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 05:57:02 PM PDT 24
Peak memory 204904 kb
Host smart-4a624fdd-822e-470b-be28-96da25cadf98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002770367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2002770367 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3770510403
Short name T404
Test name
Test status
Simulation time 13754828997 ps
CPU time 159.46 seconds
Started Aug 13 05:56:59 PM PDT 24
Finished Aug 13 05:59:39 PM PDT 24
Peak memory 291056 kb
Host smart-4456a42f-971d-4c2b-b56b-aa12e329a27b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770510403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3770510403 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.4134371057
Short name T112
Test name
Test status
Simulation time 219986678 ps
CPU time 5.62 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 05:57:06 PM PDT 24
Peak memory 218568 kb
Host smart-ff86fb3b-866d-4f4c-86b4-0495519de063
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134371057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.413437105
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.3306017561
Short name T354
Test name
Test status
Simulation time 77037015627 ps
CPU time 358.83 seconds
Started Aug 13 05:56:59 PM PDT 24
Finished Aug 13 06:02:58 PM PDT 24
Peak memory 503732 kb
Host smart-0c5582fb-82a5-4274-a24c-27b36805bd6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306017561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3
306017561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.2744817927
Short name T454
Test name
Test status
Simulation time 9254221622 ps
CPU time 212.21 seconds
Started Aug 13 05:57:05 PM PDT 24
Finished Aug 13 06:00:37 PM PDT 24
Peak memory 420120 kb
Host smart-034e4817-1d28-4cc5-8826-c61c3cea80c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744817927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2744817927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.3483264289
Short name T59
Test name
Test status
Simulation time 3236978196 ps
CPU time 8.65 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 05:57:10 PM PDT 24
Peak memory 217412 kb
Host smart-a4f15582-283e-426e-b179-9f5824dba5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483264289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3483264289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.2955290110
Short name T500
Test name
Test status
Simulation time 217180520 ps
CPU time 1.89 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 05:57:06 PM PDT 24
Peak memory 218020 kb
Host smart-2f5e88b4-fbab-4c63-826b-3bb666528350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955290110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2955290110 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_sideload.478748822
Short name T341
Test name
Test status
Simulation time 3755960848 ps
CPU time 295.89 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 06:02:00 PM PDT 24
Peak memory 349004 kb
Host smart-f8f75eeb-3d54-4a90-ac10-2be600850104
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478748822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.478748822 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3531098572
Short name T558
Test name
Test status
Simulation time 69697920 ps
CPU time 2.25 seconds
Started Aug 13 05:56:58 PM PDT 24
Finished Aug 13 05:57:01 PM PDT 24
Peak memory 217452 kb
Host smart-becbfcee-d2e5-419e-8be3-a276dc4d9290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531098572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3531098572 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.3614094075
Short name T641
Test name
Test status
Simulation time 76060877792 ps
CPU time 1994.21 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 06:30:18 PM PDT 24
Peak memory 1455248 kb
Host smart-dadf56d2-a31e-48e1-b31c-d7275cdba21e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3614094075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3614094075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_alert_test.4141822892
Short name T634
Test name
Test status
Simulation time 16607757 ps
CPU time 0.84 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 05:57:02 PM PDT 24
Peak memory 204936 kb
Host smart-36937121-b693-4b9b-ba1e-9f2a3529fbd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141822892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.4141822892 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.1234366518
Short name T605
Test name
Test status
Simulation time 1014863361 ps
CPU time 21.13 seconds
Started Aug 13 05:57:03 PM PDT 24
Finished Aug 13 05:57:25 PM PDT 24
Peak memory 222740 kb
Host smart-cbbf833b-e64d-475e-b67d-ec15143b45c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234366518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1234366518 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.547849215
Short name T473
Test name
Test status
Simulation time 16221614005 ps
CPU time 354.61 seconds
Started Aug 13 05:57:02 PM PDT 24
Finished Aug 13 06:02:57 PM PDT 24
Peak memory 232996 kb
Host smart-1081579b-443a-4f76-8479-110a409b16f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547849215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.547849215
+enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.4034692181
Short name T164
Test name
Test status
Simulation time 28710336130 ps
CPU time 305.75 seconds
Started Aug 13 05:56:59 PM PDT 24
Finished Aug 13 06:02:05 PM PDT 24
Peak memory 334128 kb
Host smart-8143ff3b-a673-4e4d-a83a-8c7b436ec188
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034692181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.4
034692181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.2541952933
Short name T571
Test name
Test status
Simulation time 14656449250 ps
CPU time 472.51 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 06:04:53 PM PDT 24
Peak memory 609340 kb
Host smart-0aea61d9-f837-49d7-a70a-d5a933fcbe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541952933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.2541952933 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.4139934073
Short name T708
Test name
Test status
Simulation time 6341089892 ps
CPU time 11.07 seconds
Started Aug 13 05:57:05 PM PDT 24
Finished Aug 13 05:57:16 PM PDT 24
Peak memory 218768 kb
Host smart-7326784b-16c9-48ac-acb8-3cc63791d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139934073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.4139934073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.774366740
Short name T266
Test name
Test status
Simulation time 83046485 ps
CPU time 1.67 seconds
Started Aug 13 05:57:06 PM PDT 24
Finished Aug 13 05:57:08 PM PDT 24
Peak memory 217060 kb
Host smart-76ceb750-2bb5-4743-875c-0da0d9d6b41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774366740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.774366740 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.3475108782
Short name T202
Test name
Test status
Simulation time 20801283195 ps
CPU time 1028.81 seconds
Started Aug 13 05:57:01 PM PDT 24
Finished Aug 13 06:14:10 PM PDT 24
Peak memory 812620 kb
Host smart-bcc76aee-5cb3-48d2-939f-ef00efe77a53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475108782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.3475108782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.604042455
Short name T468
Test name
Test status
Simulation time 2214207325 ps
CPU time 145.89 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 05:59:30 PM PDT 24
Peak memory 281804 kb
Host smart-12f425ef-c2c0-4308-a2db-2cb55bdb16d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604042455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.604042455 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.1301971315
Short name T335
Test name
Test status
Simulation time 618467653 ps
CPU time 8.48 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 05:57:12 PM PDT 24
Peak memory 217796 kb
Host smart-638d1e43-173f-44a6-9b5b-050aa97fe5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301971315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1301971315 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_alert_test.1112016354
Short name T208
Test name
Test status
Simulation time 19116767 ps
CPU time 0.78 seconds
Started Aug 13 05:57:06 PM PDT 24
Finished Aug 13 05:57:07 PM PDT 24
Peak memory 204940 kb
Host smart-7fa82e48-7d00-41ca-875f-0e2e4c6190a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112016354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1112016354 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.4134183291
Short name T684
Test name
Test status
Simulation time 36784737267 ps
CPU time 347.26 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 06:02:51 PM PDT 24
Peak memory 520324 kb
Host smart-703ddfbd-e194-4dc0-9048-bcaa243a611d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134183291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.4134183291 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.4226092294
Short name T688
Test name
Test status
Simulation time 100347701951 ps
CPU time 895.97 seconds
Started Aug 13 05:57:07 PM PDT 24
Finished Aug 13 06:12:03 PM PDT 24
Peak memory 253172 kb
Host smart-df998cfe-3d75-44d2-991e-75495ba398c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226092294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.422609229
4 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.482393987
Short name T492
Test name
Test status
Simulation time 5534656946 ps
CPU time 50.59 seconds
Started Aug 13 05:57:06 PM PDT 24
Finished Aug 13 05:57:56 PM PDT 24
Peak memory 263484 kb
Host smart-efb294b6-a4d4-42de-a00d-ed75e37f00cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482393987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.48
2393987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.1632983979
Short name T573
Test name
Test status
Simulation time 28999308863 ps
CPU time 353.54 seconds
Started Aug 13 05:57:07 PM PDT 24
Finished Aug 13 06:03:00 PM PDT 24
Peak memory 364060 kb
Host smart-0fe93e38-0e98-4e83-8cad-a87f419953f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632983979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1632983979 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.2184984281
Short name T337
Test name
Test status
Simulation time 448857192 ps
CPU time 2.22 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 05:57:07 PM PDT 24
Peak memory 217572 kb
Host smart-700934d8-7d6b-4b1c-8e33-aec6f6400fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184984281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.2184984281 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.2951698735
Short name T515
Test name
Test status
Simulation time 2306115538 ps
CPU time 30.57 seconds
Started Aug 13 05:57:06 PM PDT 24
Finished Aug 13 05:57:37 PM PDT 24
Peak memory 237004 kb
Host smart-b47238f3-720f-4f96-ad86-1266dfefc30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951698735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2951698735 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.2357291414
Short name T207
Test name
Test status
Simulation time 50035347273 ps
CPU time 1115.05 seconds
Started Aug 13 05:57:05 PM PDT 24
Finished Aug 13 06:15:40 PM PDT 24
Peak memory 844756 kb
Host smart-083ed2b6-bac7-402c-9f1f-fdc8e09b29e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357291414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.2357291414 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3690339415
Short name T209
Test name
Test status
Simulation time 5175943101 ps
CPU time 359.81 seconds
Started Aug 13 05:57:05 PM PDT 24
Finished Aug 13 06:03:05 PM PDT 24
Peak memory 365576 kb
Host smart-c9d7e45d-5b4f-446d-9713-b623b6009d01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690339415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3690339415 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.2334037646
Short name T546
Test name
Test status
Simulation time 44205615 ps
CPU time 2.52 seconds
Started Aug 13 05:57:06 PM PDT 24
Finished Aug 13 05:57:08 PM PDT 24
Peak memory 217652 kb
Host smart-747acc62-a8b1-4f32-bad6-459669d6fd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334037646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2334037646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.2171436553
Short name T262
Test name
Test status
Simulation time 136645004575 ps
CPU time 1126.17 seconds
Started Aug 13 05:57:06 PM PDT 24
Finished Aug 13 06:15:53 PM PDT 24
Peak memory 1012892 kb
Host smart-188a60e2-eec0-4586-ae36-08bbe74656ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2171436553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2171436553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_alert_test.1772819413
Short name T44
Test name
Test status
Simulation time 66439178 ps
CPU time 0.83 seconds
Started Aug 13 05:55:14 PM PDT 24
Finished Aug 13 05:55:15 PM PDT 24
Peak memory 204872 kb
Host smart-cbe85c37-39e6-4765-939a-e76572c08cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772819413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1772819413 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.2882372993
Short name T103
Test name
Test status
Simulation time 3963117645 ps
CPU time 222.25 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 05:58:59 PM PDT 24
Peak memory 319128 kb
Host smart-7e9bd1a0-5771-453e-a2c3-9fa7797c2142
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882372993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2882372993 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.2380876952
Short name T364
Test name
Test status
Simulation time 13535602005 ps
CPU time 133.83 seconds
Started Aug 13 05:55:13 PM PDT 24
Finished Aug 13 05:57:27 PM PDT 24
Peak memory 271088 kb
Host smart-0948f11e-3e78-4640-ab88-9839ed565104
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380876952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_par
tial_data.2380876952 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.3826598871
Short name T658
Test name
Test status
Simulation time 28055160931 ps
CPU time 834.13 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 06:09:02 PM PDT 24
Peak memory 255104 kb
Host smart-c47dbfb1-5588-4071-9657-e8dcdbbcfbc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826598871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3826598871
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.2076882357
Short name T645
Test name
Test status
Simulation time 108357664 ps
CPU time 8.04 seconds
Started Aug 13 05:55:14 PM PDT 24
Finished Aug 13 05:55:22 PM PDT 24
Peak memory 223448 kb
Host smart-58b3f3c3-dbf3-4a8d-874a-016cf3f6d274
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2076882357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2076882357 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.1619639145
Short name T210
Test name
Test status
Simulation time 2458462213 ps
CPU time 28.37 seconds
Started Aug 13 05:55:15 PM PDT 24
Finished Aug 13 05:55:44 PM PDT 24
Peak memory 235868 kb
Host smart-37478bbb-46be-4ab9-bccf-84f76e9f5dbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1619639145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1619639145 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.387917381
Short name T570
Test name
Test status
Simulation time 3160569040 ps
CPU time 25.89 seconds
Started Aug 13 05:55:14 PM PDT 24
Finished Aug 13 05:55:40 PM PDT 24
Peak memory 218132 kb
Host smart-58d0f85a-3c3f-4a66-9df4-ae83a661fa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387917381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.387917381 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.2454369522
Short name T537
Test name
Test status
Simulation time 5896084139 ps
CPU time 16.81 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 05:55:33 PM PDT 24
Peak memory 220808 kb
Host smart-8307c496-495f-44b6-825b-166a5164d427
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454369522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.24
54369522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.3323553500
Short name T166
Test name
Test status
Simulation time 6742175232 ps
CPU time 386.82 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 06:01:43 PM PDT 24
Peak memory 373748 kb
Host smart-e7787d5d-cb21-4c0a-9731-26874235dfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323553500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3323553500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.411014611
Short name T373
Test name
Test status
Simulation time 5323613182 ps
CPU time 7.64 seconds
Started Aug 13 05:55:11 PM PDT 24
Finished Aug 13 05:55:19 PM PDT 24
Peak memory 217464 kb
Host smart-0dff323c-a4f8-4d7f-8cd7-caf4ec423b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411014611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.411014611 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.4221554563
Short name T53
Test name
Test status
Simulation time 58628869 ps
CPU time 1.59 seconds
Started Aug 13 05:55:14 PM PDT 24
Finished Aug 13 05:55:15 PM PDT 24
Peak memory 217692 kb
Host smart-ef157df4-87b3-4e0f-9b5a-7aa22f2e499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221554563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.4221554563 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.2224969506
Short name T579
Test name
Test status
Simulation time 59437053922 ps
CPU time 1567.31 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 06:21:15 PM PDT 24
Peak memory 1102376 kb
Host smart-90c451b4-1b49-4940-86a9-09b63f745ff4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224969506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.2224969506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.421561134
Short name T62
Test name
Test status
Simulation time 11378715724 ps
CPU time 38.5 seconds
Started Aug 13 05:55:14 PM PDT 24
Finished Aug 13 05:55:52 PM PDT 24
Peak memory 252436 kb
Host smart-6f11d60c-bc80-4c15-b54a-31efa04ae402
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421561134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.421561134 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.2603082195
Short name T424
Test name
Test status
Simulation time 26772873710 ps
CPU time 189.15 seconds
Started Aug 13 05:55:08 PM PDT 24
Finished Aug 13 05:58:17 PM PDT 24
Peak memory 393716 kb
Host smart-bd811b2a-db98-451f-926f-ddc8a2e6a349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603082195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2603082195 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1441549153
Short name T256
Test name
Test status
Simulation time 1582653992 ps
CPU time 22.52 seconds
Started Aug 13 05:55:05 PM PDT 24
Finished Aug 13 05:55:27 PM PDT 24
Peak memory 220412 kb
Host smart-1c966b48-3799-4782-804d-fedcf0ea40e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441549153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1441549153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.4276881363
Short name T415
Test name
Test status
Simulation time 75516751868 ps
CPU time 962.92 seconds
Started Aug 13 05:55:13 PM PDT 24
Finished Aug 13 06:11:16 PM PDT 24
Peak memory 649176 kb
Host smart-8a9937cc-78d1-4d50-aaba-948b3bc938b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4276881363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.4276881363 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.2873320183
Short name T566
Test name
Test status
Simulation time 97989890 ps
CPU time 1.86 seconds
Started Aug 13 05:55:12 PM PDT 24
Finished Aug 13 05:55:14 PM PDT 24
Peak memory 217600 kb
Host smart-207c60d3-46b2-4be4-a833-61ae6a0c8db2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873320183 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.2873320183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2603692526
Short name T227
Test name
Test status
Simulation time 35915508 ps
CPU time 2.11 seconds
Started Aug 13 05:55:15 PM PDT 24
Finished Aug 13 05:55:17 PM PDT 24
Peak memory 217608 kb
Host smart-5b2ac33b-e6f5-40d7-b510-c59ef20cdb51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603692526 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2603692526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.1601991452
Short name T419
Test name
Test status
Simulation time 1248490454 ps
CPU time 33.64 seconds
Started Aug 13 05:55:07 PM PDT 24
Finished Aug 13 05:55:40 PM PDT 24
Peak memory 218644 kb
Host smart-9be2bb58-8bd0-4a2a-9dd4-37dc754da613
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1601991452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1601991452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.3338600407
Short name T188
Test name
Test status
Simulation time 6748517859 ps
CPU time 44.5 seconds
Started Aug 13 05:55:13 PM PDT 24
Finished Aug 13 05:55:58 PM PDT 24
Peak memory 242960 kb
Host smart-b688c855-8e54-4d04-89b3-b530f61a59fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3338600407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3338600407 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3930055270
Short name T697
Test name
Test status
Simulation time 68374860548 ps
CPU time 2200.47 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 06:31:56 PM PDT 24
Peak memory 2373900 kb
Host smart-818cc646-e7f1-4025-9f34-c17d56bd7752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3930055270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3930055270 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.1468072182
Short name T462
Test name
Test status
Simulation time 57690158539 ps
CPU time 808.31 seconds
Started Aug 13 05:55:15 PM PDT 24
Finished Aug 13 06:08:43 PM PDT 24
Peak memory 671128 kb
Host smart-5b6821b4-3c4b-4849-b5cc-f1501f8c20ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1468072182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1468072182 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.716878643
Short name T310
Test name
Test status
Simulation time 73852090953 ps
CPU time 3829.05 seconds
Started Aug 13 05:55:13 PM PDT 24
Finished Aug 13 06:59:03 PM PDT 24
Peak memory 3756352 kb
Host smart-852c97d0-3a2d-4ba8-b2f9-87018d6c3f62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=716878643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.716878643 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.2866243846
Short name T522
Test name
Test status
Simulation time 119235468803 ps
CPU time 2977.95 seconds
Started Aug 13 05:55:12 PM PDT 24
Finished Aug 13 06:44:50 PM PDT 24
Peak memory 3067884 kb
Host smart-fd6ad1e0-ac06-462c-89d8-10a724d260b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2866243846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2866243846 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2535473084
Short name T584
Test name
Test status
Simulation time 32214294 ps
CPU time 0.8 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 05:57:14 PM PDT 24
Peak memory 204924 kb
Host smart-3c685eb3-0901-4072-a136-04b943b3a34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535473084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2535473084 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.593069913
Short name T482
Test name
Test status
Simulation time 8793405550 ps
CPU time 223.95 seconds
Started Aug 13 05:57:18 PM PDT 24
Finished Aug 13 06:01:02 PM PDT 24
Peak memory 301904 kb
Host smart-f52af481-7d61-48d9-8b75-239f8eed3f20
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593069913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.593069913 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.3605981006
Short name T64
Test name
Test status
Simulation time 16943754273 ps
CPU time 780.47 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 06:10:14 PM PDT 24
Peak memory 241608 kb
Host smart-3b5c4ace-9df5-45d4-b8e7-c94967c8e813
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605981006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.360598100
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.753278169
Short name T331
Test name
Test status
Simulation time 17568264455 ps
CPU time 300.91 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 06:02:15 PM PDT 24
Peak memory 456600 kb
Host smart-7f87e62f-cd34-4d3b-a5c9-84d45d76214b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753278169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.75
3278169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.2531978521
Short name T670
Test name
Test status
Simulation time 11326278344 ps
CPU time 351.57 seconds
Started Aug 13 05:57:15 PM PDT 24
Finished Aug 13 06:03:07 PM PDT 24
Peak memory 523660 kb
Host smart-cfa06b07-a628-40c8-bc16-81dfd67e0577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531978521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2531978521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2162599250
Short name T439
Test name
Test status
Simulation time 2809833734 ps
CPU time 7.87 seconds
Started Aug 13 05:57:15 PM PDT 24
Finished Aug 13 05:57:23 PM PDT 24
Peak memory 217324 kb
Host smart-b383ced0-0888-4b4e-8881-88a86de0b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162599250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2162599250 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.1872161646
Short name T514
Test name
Test status
Simulation time 2436450142 ps
CPU time 13.06 seconds
Started Aug 13 05:57:18 PM PDT 24
Finished Aug 13 05:57:31 PM PDT 24
Peak memory 234624 kb
Host smart-800119f9-3ae5-4017-9193-6a8860aff7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872161646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1872161646 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.1497672209
Short name T193
Test name
Test status
Simulation time 66595080489 ps
CPU time 1916.27 seconds
Started Aug 13 05:57:04 PM PDT 24
Finished Aug 13 06:29:01 PM PDT 24
Peak memory 1262288 kb
Host smart-b8526dae-4e53-452f-8095-761da1c93d77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497672209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.1497672209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.1964072871
Short name T563
Test name
Test status
Simulation time 2037777686 ps
CPU time 159.97 seconds
Started Aug 13 05:57:06 PM PDT 24
Finished Aug 13 05:59:47 PM PDT 24
Peak memory 284504 kb
Host smart-f72a4f90-7e40-4b2c-af8c-89744991eace
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964072871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1964072871 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.1883472040
Short name T722
Test name
Test status
Simulation time 633048782 ps
CPU time 32.66 seconds
Started Aug 13 05:57:06 PM PDT 24
Finished Aug 13 05:57:39 PM PDT 24
Peak memory 217856 kb
Host smart-b9bbd1d6-7858-40d9-be0f-01257a94038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883472040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1883472040 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.2659825360
Short name T370
Test name
Test status
Simulation time 377939680261 ps
CPU time 1737.63 seconds
Started Aug 13 05:57:13 PM PDT 24
Finished Aug 13 06:26:11 PM PDT 24
Peak memory 1514804 kb
Host smart-ea9c869d-c04a-44bf-834a-08ab8a149fb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2659825360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2659825360 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_alert_test.821626597
Short name T535
Test name
Test status
Simulation time 19236948 ps
CPU time 0.83 seconds
Started Aug 13 05:57:15 PM PDT 24
Finished Aug 13 05:57:16 PM PDT 24
Peak memory 204912 kb
Host smart-3eb40201-33df-492d-9943-272c3d70fc54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821626597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.821626597 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.4166862297
Short name T427
Test name
Test status
Simulation time 18092880797 ps
CPU time 230.77 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 06:01:06 PM PDT 24
Peak memory 305036 kb
Host smart-a740d24c-1f9a-450f-a945-d276d29bbca7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166862297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.4166862297 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.59004980
Short name T148
Test name
Test status
Simulation time 92309417890 ps
CPU time 675.41 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 06:08:30 PM PDT 24
Peak memory 246716 kb
Host smart-8045b365-6d6f-4d68-9874-81c66f66ef02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59004980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.59004980 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2137830495
Short name T328
Test name
Test status
Simulation time 12108375195 ps
CPU time 328.86 seconds
Started Aug 13 05:57:16 PM PDT 24
Finished Aug 13 06:02:45 PM PDT 24
Peak memory 497908 kb
Host smart-4f7dded8-adff-4b21-8d19-159bbe6de298
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137830495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2
137830495 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.4234164837
Short name T428
Test name
Test status
Simulation time 9525309889 ps
CPU time 200.68 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 06:00:35 PM PDT 24
Peak memory 313788 kb
Host smart-d99946aa-dc85-4a1e-8b01-13e03dffd0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234164837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.4234164837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.2095524124
Short name T511
Test name
Test status
Simulation time 530744933 ps
CPU time 3.33 seconds
Started Aug 13 05:57:15 PM PDT 24
Finished Aug 13 05:57:18 PM PDT 24
Peak memory 217332 kb
Host smart-0d426dc5-a684-4d1c-b1d5-255bef9d2376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095524124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2095524124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.4085973517
Short name T591
Test name
Test status
Simulation time 45542809 ps
CPU time 1.74 seconds
Started Aug 13 05:57:15 PM PDT 24
Finished Aug 13 05:57:17 PM PDT 24
Peak memory 216924 kb
Host smart-03768ce6-38d9-4175-a120-c12494d45390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085973517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.4085973517 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.3281218919
Short name T487
Test name
Test status
Simulation time 319882016797 ps
CPU time 4404.24 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 07:10:40 PM PDT 24
Peak memory 3375292 kb
Host smart-2c4af807-b065-45b1-8c1a-efcdeac7ac96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281218919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.3281218919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1053376644
Short name T664
Test name
Test status
Simulation time 9305679585 ps
CPU time 142.96 seconds
Started Aug 13 05:57:18 PM PDT 24
Finished Aug 13 05:59:41 PM PDT 24
Peak memory 276168 kb
Host smart-1916faec-ceb8-4713-8475-f085a4e9c27a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053376644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1053376644 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.2019416856
Short name T583
Test name
Test status
Simulation time 20831621824 ps
CPU time 46.37 seconds
Started Aug 13 05:57:11 PM PDT 24
Finished Aug 13 05:57:58 PM PDT 24
Peak memory 224076 kb
Host smart-861a6722-6d40-4322-93c7-b34c68b3d599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019416856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2019416856 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.1135419755
Short name T662
Test name
Test status
Simulation time 77394316781 ps
CPU time 2631.63 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 06:41:06 PM PDT 24
Peak memory 1689488 kb
Host smart-0aad4fc4-97cc-4bd5-b1be-47a86ddea087
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1135419755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1135419755 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_alert_test.2273269441
Short name T646
Test name
Test status
Simulation time 40201585 ps
CPU time 0.74 seconds
Started Aug 13 05:57:25 PM PDT 24
Finished Aug 13 05:57:26 PM PDT 24
Peak memory 204972 kb
Host smart-b6562e84-4472-4864-a4c4-c629d16df0e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273269441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2273269441 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.578761883
Short name T366
Test name
Test status
Simulation time 10285269667 ps
CPU time 227.03 seconds
Started Aug 13 05:57:26 PM PDT 24
Finished Aug 13 06:01:14 PM PDT 24
Peak memory 412712 kb
Host smart-b7a5ba08-045c-47aa-9bcd-594798b2021b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578761883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.578761883 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.1789270793
Short name T381
Test name
Test status
Simulation time 7504661588 ps
CPU time 723.13 seconds
Started Aug 13 05:57:25 PM PDT 24
Finished Aug 13 06:09:28 PM PDT 24
Peak memory 238340 kb
Host smart-d714e08f-a0bf-4bd7-9b6e-9366901011c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789270793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.178927079
3 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.4107873705
Short name T448
Test name
Test status
Simulation time 1501914406 ps
CPU time 33.25 seconds
Started Aug 13 05:57:24 PM PDT 24
Finished Aug 13 05:57:57 PM PDT 24
Peak memory 252144 kb
Host smart-54982ae7-b103-4d42-b3d1-d18d3f024ba9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107873705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.4
107873705 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.679141963
Short name T464
Test name
Test status
Simulation time 9689655274 ps
CPU time 349.51 seconds
Started Aug 13 05:57:24 PM PDT 24
Finished Aug 13 06:03:13 PM PDT 24
Peak memory 386264 kb
Host smart-68c983da-eda5-420a-a78f-e0127e15ffca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679141963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.679141963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2488662985
Short name T339
Test name
Test status
Simulation time 7437722643 ps
CPU time 9.09 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 05:58:48 PM PDT 24
Peak memory 217436 kb
Host smart-3c603ccb-fed9-4126-a596-6dd9482f98e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488662985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2488662985 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2549906754
Short name T723
Test name
Test status
Simulation time 389091429 ps
CPU time 1.57 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 05:58:41 PM PDT 24
Peak memory 217920 kb
Host smart-2bbb03ca-a89c-416c-b3b4-cca71e9fdfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549906754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2549906754 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_sideload.2470374426
Short name T459
Test name
Test status
Simulation time 4319551112 ps
CPU time 184.2 seconds
Started Aug 13 05:57:14 PM PDT 24
Finished Aug 13 06:00:19 PM PDT 24
Peak memory 298832 kb
Host smart-bf327459-e417-4ba7-8df6-de31797d04c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470374426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2470374426 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.3096943673
Short name T17
Test name
Test status
Simulation time 652650531 ps
CPU time 13.05 seconds
Started Aug 13 05:57:11 PM PDT 24
Finished Aug 13 05:57:24 PM PDT 24
Peak memory 217188 kb
Host smart-1a3c7f17-b9fb-4177-9c43-e03b6b7764c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096943673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3096943673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.164907864
Short name T290
Test name
Test status
Simulation time 13913921917 ps
CPU time 346.33 seconds
Started Aug 13 05:57:24 PM PDT 24
Finished Aug 13 06:03:10 PM PDT 24
Peak memory 330540 kb
Host smart-a697a48b-9c0d-4d2d-a522-fec96723b6c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=164907864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.164907864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_alert_test.2931791467
Short name T480
Test name
Test status
Simulation time 19644569 ps
CPU time 0.81 seconds
Started Aug 13 05:57:26 PM PDT 24
Finished Aug 13 05:57:27 PM PDT 24
Peak memory 204884 kb
Host smart-5505896b-1f01-40cc-8b87-6b103dca0ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931791467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2931791467 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.525214586
Short name T288
Test name
Test status
Simulation time 2546394851 ps
CPU time 42.17 seconds
Started Aug 13 05:57:22 PM PDT 24
Finished Aug 13 05:58:04 PM PDT 24
Peak memory 248644 kb
Host smart-45c0bb3e-145f-43da-91c2-9d3bc2d874ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525214586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.525214586 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.2831995569
Short name T616
Test name
Test status
Simulation time 1845665917 ps
CPU time 6.81 seconds
Started Aug 13 05:57:21 PM PDT 24
Finished Aug 13 05:57:28 PM PDT 24
Peak memory 218608 kb
Host smart-a5c59d76-82ce-4b1b-9c02-34737feed029
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831995569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.283199556
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.3651519299
Short name T392
Test name
Test status
Simulation time 12238072119 ps
CPU time 237.17 seconds
Started Aug 13 05:57:25 PM PDT 24
Finished Aug 13 06:01:22 PM PDT 24
Peak memory 313208 kb
Host smart-4078afaf-fa7d-45a7-ae2e-7a0d1214840f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651519299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3
651519299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.4185952221
Short name T528
Test name
Test status
Simulation time 1813411727 ps
CPU time 27.25 seconds
Started Aug 13 05:57:26 PM PDT 24
Finished Aug 13 05:57:54 PM PDT 24
Peak memory 248320 kb
Host smart-e0b398ff-7822-436a-b9e2-c15033c42516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185952221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.4185952221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.551340062
Short name T61
Test name
Test status
Simulation time 4382492260 ps
CPU time 6.04 seconds
Started Aug 13 05:57:23 PM PDT 24
Finished Aug 13 05:57:30 PM PDT 24
Peak memory 217308 kb
Host smart-11182cf0-4f01-4e17-9a2d-b3e56f75cf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551340062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.551340062 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1116039713
Short name T629
Test name
Test status
Simulation time 181990857 ps
CPU time 1.18 seconds
Started Aug 13 05:57:23 PM PDT 24
Finished Aug 13 05:57:25 PM PDT 24
Peak memory 223080 kb
Host smart-b0e9cc4e-b9e8-4d8e-a265-09ea241dedbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116039713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1116039713 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.2377514092
Short name T539
Test name
Test status
Simulation time 18786349144 ps
CPU time 2053.21 seconds
Started Aug 13 05:57:24 PM PDT 24
Finished Aug 13 06:31:38 PM PDT 24
Peak memory 1337740 kb
Host smart-bf9d98aa-f72e-4bd5-8208-f02eb050b98f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377514092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.2377514092 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.3873547942
Short name T425
Test name
Test status
Simulation time 26701277795 ps
CPU time 322.52 seconds
Started Aug 13 05:57:24 PM PDT 24
Finished Aug 13 06:02:46 PM PDT 24
Peak memory 489340 kb
Host smart-857f26e9-2e30-47bd-a82e-9eee28371feb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873547942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3873547942 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.4045645229
Short name T561
Test name
Test status
Simulation time 16101935940 ps
CPU time 47.78 seconds
Started Aug 13 05:57:23 PM PDT 24
Finished Aug 13 05:58:11 PM PDT 24
Peak memory 217684 kb
Host smart-27eef681-b3da-4f47-93b9-b54c135e5318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045645229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.4045645229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3000458724
Short name T639
Test name
Test status
Simulation time 7900653120 ps
CPU time 659.86 seconds
Started Aug 13 05:57:24 PM PDT 24
Finished Aug 13 06:08:24 PM PDT 24
Peak memory 440096 kb
Host smart-625aa8cf-650b-4688-af15-b66742bd3119
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3000458724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3000458724 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_alert_test.3283637448
Short name T313
Test name
Test status
Simulation time 20985047 ps
CPU time 0.81 seconds
Started Aug 13 05:57:32 PM PDT 24
Finished Aug 13 05:57:32 PM PDT 24
Peak memory 205088 kb
Host smart-20c5f86a-b697-436f-a694-4bae27c3c6e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283637448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3283637448 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_burst_write.3237933849
Short name T526
Test name
Test status
Simulation time 100839018005 ps
CPU time 843.18 seconds
Started Aug 13 05:57:32 PM PDT 24
Finished Aug 13 06:11:35 PM PDT 24
Peak memory 251588 kb
Host smart-620c844d-0eaf-4df4-b3cc-d0452aa1d8bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237933849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.323793384
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.1534485533
Short name T413
Test name
Test status
Simulation time 31965657117 ps
CPU time 261.79 seconds
Started Aug 13 05:57:32 PM PDT 24
Finished Aug 13 06:01:54 PM PDT 24
Peak memory 320124 kb
Host smart-c53f27b0-b32b-4041-adcb-385ff7ee9d30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534485533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1
534485533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.2154665678
Short name T536
Test name
Test status
Simulation time 12484420984 ps
CPU time 259.59 seconds
Started Aug 13 05:57:29 PM PDT 24
Finished Aug 13 06:01:49 PM PDT 24
Peak memory 336768 kb
Host smart-f0375dec-68d6-44b1-850b-071ea82c5dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154665678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2154665678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.1458928020
Short name T423
Test name
Test status
Simulation time 1489622666 ps
CPU time 3.03 seconds
Started Aug 13 05:57:31 PM PDT 24
Finished Aug 13 05:57:34 PM PDT 24
Peak memory 217620 kb
Host smart-e7be7eb8-2ea1-4303-82ca-47a097d8a7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458928020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1458928020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.1883549890
Short name T621
Test name
Test status
Simulation time 113892004 ps
CPU time 1.39 seconds
Started Aug 13 05:57:32 PM PDT 24
Finished Aug 13 05:57:34 PM PDT 24
Peak memory 219004 kb
Host smart-8b0992df-62cc-4552-99cd-eae8957f41b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883549890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1883549890 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.2070175323
Short name T329
Test name
Test status
Simulation time 16629324617 ps
CPU time 1721.21 seconds
Started Aug 13 05:57:25 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 1240556 kb
Host smart-0ed35f81-4878-4caf-8745-b7e7f38d124e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070175323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.2070175323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3280990283
Short name T509
Test name
Test status
Simulation time 2743287994 ps
CPU time 68.73 seconds
Started Aug 13 05:57:23 PM PDT 24
Finished Aug 13 05:58:32 PM PDT 24
Peak memory 273520 kb
Host smart-759668e9-8de7-433f-b1f4-ee51e6dc6beb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280990283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3280990283 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.3447843216
Short name T640
Test name
Test status
Simulation time 2121359275 ps
CPU time 33.43 seconds
Started Aug 13 05:57:23 PM PDT 24
Finished Aug 13 05:57:56 PM PDT 24
Peak memory 217836 kb
Host smart-9fcbd0e9-8151-40e9-821c-c3dab7309183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447843216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3447843216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.2461720011
Short name T644
Test name
Test status
Simulation time 52737972318 ps
CPU time 494.08 seconds
Started Aug 13 05:57:34 PM PDT 24
Finished Aug 13 06:05:48 PM PDT 24
Peak memory 370908 kb
Host smart-eb866d77-b418-4417-b5b7-d160aa018c70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2461720011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2461720011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_alert_test.1545728606
Short name T237
Test name
Test status
Simulation time 14317038 ps
CPU time 0.82 seconds
Started Aug 13 05:57:43 PM PDT 24
Finished Aug 13 05:57:44 PM PDT 24
Peak memory 204836 kb
Host smart-59b5f031-b373-4ddb-832a-c59d36c135bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545728606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1545728606 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.1652601595
Short name T20
Test name
Test status
Simulation time 27312904132 ps
CPU time 173.01 seconds
Started Aug 13 05:57:43 PM PDT 24
Finished Aug 13 06:00:36 PM PDT 24
Peak memory 288300 kb
Host smart-cf0f3e40-fe37-4aaa-a6ca-7a3b42b5c184
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652601595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1652601595 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.2215271996
Short name T278
Test name
Test status
Simulation time 15345455947 ps
CPU time 572.01 seconds
Started Aug 13 05:57:32 PM PDT 24
Finished Aug 13 06:07:04 PM PDT 24
Peak memory 245460 kb
Host smart-698af2bf-2503-4d56-8085-78d4376eadaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215271996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.221527199
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.1086115411
Short name T286
Test name
Test status
Simulation time 9273969576 ps
CPU time 124.17 seconds
Started Aug 13 05:57:41 PM PDT 24
Finished Aug 13 05:59:45 PM PDT 24
Peak memory 270492 kb
Host smart-7cc44404-535f-4c76-8eb4-95b4d526bfd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086115411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1
086115411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3954181178
Short name T165
Test name
Test status
Simulation time 3271560293 ps
CPU time 288.33 seconds
Started Aug 13 05:57:37 PM PDT 24
Finished Aug 13 06:02:25 PM PDT 24
Peak memory 340484 kb
Host smart-a495e90f-7215-4f6a-92b7-7287ff2fa6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954181178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3954181178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.3833458848
Short name T555
Test name
Test status
Simulation time 1232451839 ps
CPU time 2.4 seconds
Started Aug 13 05:57:39 PM PDT 24
Finished Aug 13 05:57:42 PM PDT 24
Peak memory 217616 kb
Host smart-8510f7e4-f627-48cc-92a0-5c8b9c0dd97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833458848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3833458848 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.502103115
Short name T441
Test name
Test status
Simulation time 160284366 ps
CPU time 1.93 seconds
Started Aug 13 05:57:41 PM PDT 24
Finished Aug 13 05:57:43 PM PDT 24
Peak memory 216928 kb
Host smart-f58a3319-ba51-47c4-94b3-860b3091d21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502103115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.502103115 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.1648177862
Short name T592
Test name
Test status
Simulation time 51977303801 ps
CPU time 2547.63 seconds
Started Aug 13 05:57:34 PM PDT 24
Finished Aug 13 06:40:02 PM PDT 24
Peak memory 2554080 kb
Host smart-8ce6611a-03c4-48a2-9885-2d60d4db4d9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648177862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.1648177862 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.3643113180
Short name T282
Test name
Test status
Simulation time 67502091099 ps
CPU time 408.9 seconds
Started Aug 13 05:57:34 PM PDT 24
Finished Aug 13 06:04:23 PM PDT 24
Peak memory 591488 kb
Host smart-148c2b5e-561f-4856-bd45-502bcacd668e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643113180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3643113180 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.2153858214
Short name T342
Test name
Test status
Simulation time 3003741597 ps
CPU time 54.14 seconds
Started Aug 13 05:57:33 PM PDT 24
Finished Aug 13 05:58:27 PM PDT 24
Peak memory 220652 kb
Host smart-a9fed54c-56cc-4f1a-92f2-28e9bf46e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153858214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2153858214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.2920137346
Short name T700
Test name
Test status
Simulation time 9766553431 ps
CPU time 325.44 seconds
Started Aug 13 05:57:37 PM PDT 24
Finished Aug 13 06:03:03 PM PDT 24
Peak memory 376068 kb
Host smart-74a64df0-f92d-4def-af5c-3b570686025f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2920137346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2920137346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_alert_test.1671794742
Short name T356
Test name
Test status
Simulation time 26147112 ps
CPU time 0.73 seconds
Started Aug 13 05:57:48 PM PDT 24
Finished Aug 13 05:57:48 PM PDT 24
Peak memory 204952 kb
Host smart-beedf1e3-2a0e-4487-9552-d4c8cc6bae5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671794742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1671794742 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.657501127
Short name T457
Test name
Test status
Simulation time 4348583321 ps
CPU time 282.75 seconds
Started Aug 13 05:57:40 PM PDT 24
Finished Aug 13 06:02:23 PM PDT 24
Peak memory 330792 kb
Host smart-cb759b4f-1593-4a13-a794-e03aeeb2b1a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657501127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.657501127 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3964729271
Short name T677
Test name
Test status
Simulation time 3260789852 ps
CPU time 322.56 seconds
Started Aug 13 05:57:43 PM PDT 24
Finished Aug 13 06:03:06 PM PDT 24
Peak memory 229360 kb
Host smart-c765a37b-31fa-4780-88cf-a1ab96bbbecf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964729271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.396472927
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.3956162169
Short name T302
Test name
Test status
Simulation time 9390613438 ps
CPU time 63.35 seconds
Started Aug 13 05:57:41 PM PDT 24
Finished Aug 13 05:58:45 PM PDT 24
Peak memory 271748 kb
Host smart-45ef3e4f-4a3a-47ad-8532-d5e04ca16396
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956162169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3
956162169 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_key_error.216962760
Short name T334
Test name
Test status
Simulation time 2217001015 ps
CPU time 5.97 seconds
Started Aug 13 05:57:47 PM PDT 24
Finished Aug 13 05:57:53 PM PDT 24
Peak memory 217632 kb
Host smart-bba401cb-1104-4589-8494-66f56b9992b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216962760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.216962760 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.2206168882
Short name T436
Test name
Test status
Simulation time 80856856 ps
CPU time 1.1 seconds
Started Aug 13 05:57:47 PM PDT 24
Finished Aug 13 05:57:48 PM PDT 24
Peak memory 218624 kb
Host smart-daef1d7f-004b-4025-88f6-3a3b37f3eb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206168882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2206168882 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.3488441453
Short name T377
Test name
Test status
Simulation time 11580538812 ps
CPU time 1172.98 seconds
Started Aug 13 05:57:39 PM PDT 24
Finished Aug 13 06:17:13 PM PDT 24
Peak memory 930028 kb
Host smart-ef2d578b-9f16-43fb-bdd2-c3b608a99e5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488441453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.3488441453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.2383850230
Short name T636
Test name
Test status
Simulation time 2307081096 ps
CPU time 13.24 seconds
Started Aug 13 05:57:41 PM PDT 24
Finished Aug 13 05:57:54 PM PDT 24
Peak memory 230988 kb
Host smart-fbc054ed-bf7c-42f3-8d35-a78fdfeab0bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383850230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2383850230 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.2091756586
Short name T456
Test name
Test status
Simulation time 410172023 ps
CPU time 5.5 seconds
Started Aug 13 05:57:38 PM PDT 24
Finished Aug 13 05:57:44 PM PDT 24
Peak memory 218152 kb
Host smart-b57a9455-583a-4778-9eec-9256b8dab5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091756586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2091756586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.1962993635
Short name T249
Test name
Test status
Simulation time 64445034293 ps
CPU time 519.06 seconds
Started Aug 13 05:57:50 PM PDT 24
Finished Aug 13 06:06:29 PM PDT 24
Peak memory 789496 kb
Host smart-e9692538-7b60-4e66-88f4-08aa60300045
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1962993635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1962993635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1176516046
Short name T347
Test name
Test status
Simulation time 102743114 ps
CPU time 0.81 seconds
Started Aug 13 05:57:46 PM PDT 24
Finished Aug 13 05:57:47 PM PDT 24
Peak memory 204912 kb
Host smart-c2da80b0-6438-4d51-91d2-730a3276ecda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176516046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1176516046 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.3192225743
Short name T445
Test name
Test status
Simulation time 53798692158 ps
CPU time 342.7 seconds
Started Aug 13 05:57:48 PM PDT 24
Finished Aug 13 06:03:31 PM PDT 24
Peak memory 504704 kb
Host smart-38a4032a-b79b-4c3f-a0ff-48942c8445cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192225743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3192225743 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.220132715
Short name T330
Test name
Test status
Simulation time 27103190383 ps
CPU time 330.99 seconds
Started Aug 13 05:57:49 PM PDT 24
Finished Aug 13 06:03:20 PM PDT 24
Peak memory 235036 kb
Host smart-568780a8-aebc-420d-a824-075b666740dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220132715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.220132715
+enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.3013030516
Short name T261
Test name
Test status
Simulation time 7697449502 ps
CPU time 245.11 seconds
Started Aug 13 05:57:51 PM PDT 24
Finished Aug 13 06:01:56 PM PDT 24
Peak memory 310144 kb
Host smart-f7a3c178-5160-4a76-a318-3e8533d21186
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013030516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3
013030516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.2462682854
Short name T553
Test name
Test status
Simulation time 4182305654 ps
CPU time 48.2 seconds
Started Aug 13 05:57:46 PM PDT 24
Finished Aug 13 05:58:34 PM PDT 24
Peak memory 267672 kb
Host smart-018c12d6-5cdc-4781-a1d5-be1eb7e60ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462682854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2462682854 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.1171943412
Short name T279
Test name
Test status
Simulation time 3463776029 ps
CPU time 8.9 seconds
Started Aug 13 05:57:47 PM PDT 24
Finished Aug 13 05:57:56 PM PDT 24
Peak memory 217684 kb
Host smart-01e62188-85d5-4834-92ed-404da6a0238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171943412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1171943412 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.1286409863
Short name T51
Test name
Test status
Simulation time 1409344690 ps
CPU time 37.15 seconds
Started Aug 13 05:57:47 PM PDT 24
Finished Aug 13 05:58:24 PM PDT 24
Peak memory 242072 kb
Host smart-40308b09-c8ce-4f61-8141-1b2e1f1e8f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286409863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1286409863 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.1580814304
Short name T389
Test name
Test status
Simulation time 69650016462 ps
CPU time 3730.3 seconds
Started Aug 13 05:57:49 PM PDT 24
Finished Aug 13 07:00:00 PM PDT 24
Peak memory 3282808 kb
Host smart-085da3bc-cc74-4081-bbcb-86c400c6d4a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580814304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.1580814304 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.4211940782
Short name T243
Test name
Test status
Simulation time 21958805290 ps
CPU time 341.92 seconds
Started Aug 13 05:57:47 PM PDT 24
Finished Aug 13 06:03:29 PM PDT 24
Peak memory 516528 kb
Host smart-b84cdd3e-9b2c-4cc7-b0d8-1ded6085503f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211940782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.4211940782 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.2621408235
Short name T269
Test name
Test status
Simulation time 2667261208 ps
CPU time 38.57 seconds
Started Aug 13 05:57:51 PM PDT 24
Finished Aug 13 05:58:30 PM PDT 24
Peak memory 217592 kb
Host smart-9600d070-be78-4632-aa7e-e62645baaafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621408235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2621408235 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.2491475586
Short name T407
Test name
Test status
Simulation time 7846526542 ps
CPU time 638.27 seconds
Started Aug 13 05:57:50 PM PDT 24
Finished Aug 13 06:08:28 PM PDT 24
Peak memory 468580 kb
Host smart-4a59c855-bd88-4398-a8cd-9d48e97259bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2491475586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2491475586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3310949234
Short name T525
Test name
Test status
Simulation time 37958830 ps
CPU time 0.73 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 05:57:59 PM PDT 24
Peak memory 204936 kb
Host smart-844ef195-8906-4ab4-bfcc-26bc2f0c813c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310949234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3310949234 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.210086817
Short name T710
Test name
Test status
Simulation time 2446773649 ps
CPU time 124.86 seconds
Started Aug 13 05:57:57 PM PDT 24
Finished Aug 13 06:00:02 PM PDT 24
Peak memory 268548 kb
Host smart-eb4a8a2e-12d9-4ce5-8807-4e2e61bc7740
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210086817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.210086817 +enable_masking=
0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.1236252369
Short name T652
Test name
Test status
Simulation time 246784245428 ps
CPU time 1013.39 seconds
Started Aug 13 05:57:51 PM PDT 24
Finished Aug 13 06:14:44 PM PDT 24
Peak memory 257064 kb
Host smart-61b39979-c606-4c2b-9755-31e2811cf468
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236252369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.123625236
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.4252886961
Short name T303
Test name
Test status
Simulation time 6595548881 ps
CPU time 178.48 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 06:00:57 PM PDT 24
Peak memory 301548 kb
Host smart-6f5d8796-fc01-4827-959e-a9f935a99111
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252886961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.4
252886961 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.2685823460
Short name T603
Test name
Test status
Simulation time 21399206187 ps
CPU time 503.97 seconds
Started Aug 13 05:57:57 PM PDT 24
Finished Aug 13 06:06:21 PM PDT 24
Peak memory 666476 kb
Host smart-b815c05c-9f3d-4304-a683-8d980bd01f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685823460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2685823460 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.543620124
Short name T469
Test name
Test status
Simulation time 2466734864 ps
CPU time 4.27 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 05:58:02 PM PDT 24
Peak memory 217852 kb
Host smart-6080936b-1487-4174-9555-01c3de6aac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543620124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.543620124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.3863915464
Short name T325
Test name
Test status
Simulation time 79391339 ps
CPU time 1.52 seconds
Started Aug 13 05:57:55 PM PDT 24
Finished Aug 13 05:57:56 PM PDT 24
Peak memory 217544 kb
Host smart-ce2f2331-be05-49fc-857d-cbff8ac55593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863915464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3863915464 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.4108646612
Short name T281
Test name
Test status
Simulation time 321713911755 ps
CPU time 3117.49 seconds
Started Aug 13 05:57:50 PM PDT 24
Finished Aug 13 06:49:48 PM PDT 24
Peak memory 2898160 kb
Host smart-a5f6a92e-e5cf-4a80-96e0-6605d5ef99cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108646612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.4108646612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.3778028514
Short name T271
Test name
Test status
Simulation time 1507658927 ps
CPU time 110.16 seconds
Started Aug 13 05:57:47 PM PDT 24
Finished Aug 13 05:59:37 PM PDT 24
Peak memory 270716 kb
Host smart-e4035097-918b-42a7-97f2-ad138bf810e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778028514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3778028514 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.4148254678
Short name T676
Test name
Test status
Simulation time 4699180573 ps
CPU time 53.32 seconds
Started Aug 13 05:57:47 PM PDT 24
Finished Aug 13 05:58:41 PM PDT 24
Peak memory 220272 kb
Host smart-55b9e007-62dc-4064-88c6-32478790a867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148254678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.4148254678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.1401360654
Short name T712
Test name
Test status
Simulation time 168676403 ps
CPU time 2.16 seconds
Started Aug 13 05:57:57 PM PDT 24
Finished Aug 13 05:57:59 PM PDT 24
Peak memory 217952 kb
Host smart-929d47db-e3eb-4461-840c-5bdc14b88521
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1401360654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1401360654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_alert_test.4282225990
Short name T344
Test name
Test status
Simulation time 16874129 ps
CPU time 0.75 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 05:57:58 PM PDT 24
Peak memory 204944 kb
Host smart-49454cdf-4bde-4b06-8e5a-3b3deceae637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282225990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.4282225990 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3466958630
Short name T405
Test name
Test status
Simulation time 11557035335 ps
CPU time 115.04 seconds
Started Aug 13 05:57:57 PM PDT 24
Finished Aug 13 05:59:52 PM PDT 24
Peak memory 325664 kb
Host smart-f662e4fd-9927-42b7-a954-93a5132052a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466958630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3466958630 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.1388335127
Short name T245
Test name
Test status
Simulation time 37224297525 ps
CPU time 387.15 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 06:04:25 PM PDT 24
Peak memory 236160 kb
Host smart-e928bd16-5d96-483d-bc95-5302787b3254
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388335127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.138833512
7 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.1358648506
Short name T478
Test name
Test status
Simulation time 3345645215 ps
CPU time 148.27 seconds
Started Aug 13 05:57:56 PM PDT 24
Finished Aug 13 06:00:25 PM PDT 24
Peak memory 278340 kb
Host smart-b05508f4-56a5-45c8-9543-3d8981eadc77
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358648506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1
358648506 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.3144703957
Short name T226
Test name
Test status
Simulation time 15244487040 ps
CPU time 272.55 seconds
Started Aug 13 05:57:57 PM PDT 24
Finished Aug 13 06:02:29 PM PDT 24
Peak memory 336844 kb
Host smart-1362f970-40b2-4414-966f-9411a4078a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144703957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3144703957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.835781247
Short name T340
Test name
Test status
Simulation time 1810782124 ps
CPU time 9.78 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 05:58:08 PM PDT 24
Peak memory 217620 kb
Host smart-406b9449-cc18-4eeb-bf01-8b0c82140c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835781247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.835781247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.229743474
Short name T79
Test name
Test status
Simulation time 84136573 ps
CPU time 1.27 seconds
Started Aug 13 05:57:57 PM PDT 24
Finished Aug 13 05:57:58 PM PDT 24
Peak memory 219312 kb
Host smart-9f5e9ff0-3c5b-435d-9a36-dfdbc7d470a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229743474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.229743474 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.4161877950
Short name T631
Test name
Test status
Simulation time 14134134273 ps
CPU time 1477.37 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 06:22:35 PM PDT 24
Peak memory 1068084 kb
Host smart-8cc96932-f790-4273-ab19-dcd19b15de2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161877950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.4161877950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.3495617093
Short name T300
Test name
Test status
Simulation time 9423924277 ps
CPU time 186.48 seconds
Started Aug 13 05:57:57 PM PDT 24
Finished Aug 13 06:01:03 PM PDT 24
Peak memory 300468 kb
Host smart-cf5d5d23-212a-41e4-8364-21640a46ab4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495617093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3495617093 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_stress_all.2798431706
Short name T241
Test name
Test status
Simulation time 782241120 ps
CPU time 26.89 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 05:58:25 PM PDT 24
Peak memory 238292 kb
Host smart-422b9c20-21ab-4a90-8c05-26826a5f275c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2798431706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2798431706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_alert_test.2964064828
Short name T538
Test name
Test status
Simulation time 16535263 ps
CPU time 0.8 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 05:55:23 PM PDT 24
Peak memory 204924 kb
Host smart-6b1f121e-e1f7-44a4-a88e-8c195c68372f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964064828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2964064828 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.4209621480
Short name T378
Test name
Test status
Simulation time 48861341832 ps
CPU time 314.33 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 06:00:31 PM PDT 24
Peak memory 481808 kb
Host smart-65030d91-5d38-4cb9-8726-d97516315769
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209621480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.4209621480 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.3428857135
Short name T393
Test name
Test status
Simulation time 2971792064 ps
CPU time 74.74 seconds
Started Aug 13 05:55:13 PM PDT 24
Finished Aug 13 05:56:28 PM PDT 24
Peak memory 251968 kb
Host smart-53bac13d-08d4-436f-bc50-e87e186309a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428857135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.3428857135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.3525489460
Short name T475
Test name
Test status
Simulation time 5390636070 ps
CPU time 206.81 seconds
Started Aug 13 05:55:15 PM PDT 24
Finished Aug 13 05:58:42 PM PDT 24
Peak memory 229272 kb
Host smart-669d51d3-c8ae-404e-a9ab-3d60d06146a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525489460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3525489460
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2326144122
Short name T470
Test name
Test status
Simulation time 1203889700 ps
CPU time 8.32 seconds
Started Aug 13 05:55:17 PM PDT 24
Finished Aug 13 05:55:26 PM PDT 24
Peak memory 218680 kb
Host smart-8eeb2833-21bc-4078-9da5-384d9704916c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2326144122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2326144122 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.4154532849
Short name T272
Test name
Test status
Simulation time 238513073 ps
CPU time 8.48 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 05:55:25 PM PDT 24
Peak memory 218304 kb
Host smart-3394ac20-c9ea-48af-9df1-a3ccc54ba762
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4154532849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.4154532849 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1992738348
Short name T40
Test name
Test status
Simulation time 1684593735 ps
CPU time 16.31 seconds
Started Aug 13 05:55:15 PM PDT 24
Finished Aug 13 05:55:32 PM PDT 24
Peak memory 218104 kb
Host smart-4211c54f-d94c-43ab-821e-583761cb2da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992738348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1992738348 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.2806917831
Short name T99
Test name
Test status
Simulation time 10559859517 ps
CPU time 119.43 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 05:57:16 PM PDT 24
Peak memory 303984 kb
Host smart-95ee0bcd-8e54-4be7-9388-12f7f2880748
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806917831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.28
06917831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.184191124
Short name T28
Test name
Test status
Simulation time 5587337943 ps
CPU time 94.84 seconds
Started Aug 13 05:55:14 PM PDT 24
Finished Aug 13 05:56:49 PM PDT 24
Peak memory 270828 kb
Host smart-72aca8fc-da36-413d-add9-53487f467e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184191124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.184191124 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.1013258272
Short name T618
Test name
Test status
Simulation time 5640131357 ps
CPU time 3.76 seconds
Started Aug 13 05:55:13 PM PDT 24
Finished Aug 13 05:55:17 PM PDT 24
Peak memory 217680 kb
Host smart-dba44da4-bdfd-435b-bcf0-7a4ebd140fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013258272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1013258272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.930826453
Short name T637
Test name
Test status
Simulation time 4266154339 ps
CPU time 15.9 seconds
Started Aug 13 05:55:17 PM PDT 24
Finished Aug 13 05:55:33 PM PDT 24
Peak memory 234868 kb
Host smart-b14e7429-246e-4ba9-b847-2f4be54358d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930826453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.930826453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.1565355000
Short name T610
Test name
Test status
Simulation time 18752023627 ps
CPU time 326.72 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 06:00:43 PM PDT 24
Peak memory 642000 kb
Host smart-da56a14f-a8b5-4806-95c0-bf19caaa1694
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565355000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.1565355000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3826131909
Short name T346
Test name
Test status
Simulation time 637050920 ps
CPU time 36.3 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 05:55:52 PM PDT 24
Peak memory 233140 kb
Host smart-992227c8-1089-440d-9eb6-87f5e8146004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826131909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3826131909 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sideload.3579327789
Short name T375
Test name
Test status
Simulation time 84357289991 ps
CPU time 374.07 seconds
Started Aug 13 05:55:15 PM PDT 24
Finished Aug 13 06:01:30 PM PDT 24
Peak memory 532484 kb
Host smart-8e80f339-dfb8-413b-b5a5-515ee15b88b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579327789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3579327789 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.1282598274
Short name T713
Test name
Test status
Simulation time 321227927 ps
CPU time 6.96 seconds
Started Aug 13 05:55:12 PM PDT 24
Finished Aug 13 05:55:19 PM PDT 24
Peak memory 217564 kb
Host smart-5a3fce8a-a16e-441e-9a5f-8c7347af5f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282598274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1282598274 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.3191970891
Short name T731
Test name
Test status
Simulation time 34903520680 ps
CPU time 913.22 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 06:10:29 PM PDT 24
Peak memory 323836 kb
Host smart-bfcda0f1-4965-4c18-8043-86195d33be7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3191970891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3191970891 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.1417135586
Short name T204
Test name
Test status
Simulation time 29550778 ps
CPU time 1.74 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 05:55:18 PM PDT 24
Peak memory 217892 kb
Host smart-5611f016-b436-4046-ad35-5983faa50f18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417135586 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.1417135586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.331784411
Short name T705
Test name
Test status
Simulation time 117409961 ps
CPU time 2.33 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 05:55:18 PM PDT 24
Peak memory 217840 kb
Host smart-5dcf7b6d-a65b-4d07-9040-7210f7440e49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331784411 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.kmac_test_vectors_kmac_xof.331784411 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.762805496
Short name T721
Test name
Test status
Simulation time 123164076278 ps
CPU time 2808.63 seconds
Started Aug 13 05:55:18 PM PDT 24
Finished Aug 13 06:42:07 PM PDT 24
Peak memory 3157152 kb
Host smart-b5488beb-c502-42a0-9599-9585d3b92adb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=762805496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.762805496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1208831784
Short name T205
Test name
Test status
Simulation time 17038525635 ps
CPU time 1663.59 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 06:23:00 PM PDT 24
Peak memory 1119680 kb
Host smart-9dd2f0c7-f49f-4121-8863-ac5fb3ba5726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1208831784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1208831784 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.886128565
Short name T201
Test name
Test status
Simulation time 837843834672 ps
CPU time 2204.55 seconds
Started Aug 13 05:55:17 PM PDT 24
Finished Aug 13 06:32:02 PM PDT 24
Peak memory 2349584 kb
Host smart-0206eb36-491b-4f63-b87e-dd969237e759
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=886128565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.886128565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.1601908835
Short name T498
Test name
Test status
Simulation time 7285566241 ps
CPU time 19.01 seconds
Started Aug 13 05:55:14 PM PDT 24
Finished Aug 13 05:55:33 PM PDT 24
Peak memory 218188 kb
Host smart-d7b787de-b5e4-4089-80b4-d30e70f475fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1601908835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1601908835 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.2383290776
Short name T345
Test name
Test status
Simulation time 69699110546 ps
CPU time 3522.46 seconds
Started Aug 13 05:55:16 PM PDT 24
Finished Aug 13 06:53:59 PM PDT 24
Peak memory 3543948 kb
Host smart-f4b6b72c-e9e1-4abf-98f5-fbc03e49a598
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2383290776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2383290776 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.1104687162
Short name T192
Test name
Test status
Simulation time 101417114844 ps
CPU time 416.59 seconds
Started Aug 13 05:55:14 PM PDT 24
Finished Aug 13 06:02:10 PM PDT 24
Peak memory 348256 kb
Host smart-37b1789a-2601-41e3-9f4f-83bd9b5422f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1104687162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1104687162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.2272410260
Short name T326
Test name
Test status
Simulation time 18270247 ps
CPU time 0.81 seconds
Started Aug 13 05:58:07 PM PDT 24
Finished Aug 13 05:58:08 PM PDT 24
Peak memory 204904 kb
Host smart-c17efe1c-ac0a-4a9f-924f-8baa43558e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272410260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2272410260 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3960641148
Short name T104
Test name
Test status
Simulation time 16858176102 ps
CPU time 213.64 seconds
Started Aug 13 05:58:07 PM PDT 24
Finished Aug 13 06:01:41 PM PDT 24
Peak memory 428336 kb
Host smart-710dbfd6-b88f-4cc2-a41b-2d5b1fe31089
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960641148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3960641148 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.164508281
Short name T38
Test name
Test status
Simulation time 5173010505 ps
CPU time 74.28 seconds
Started Aug 13 05:58:07 PM PDT 24
Finished Aug 13 05:59:22 PM PDT 24
Peak memory 221320 kb
Host smart-c48045f0-ac30-47df-a2bc-43d92e9d02e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164508281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.164508281
+enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.480586338
Short name T367
Test name
Test status
Simulation time 58443274301 ps
CPU time 302.56 seconds
Started Aug 13 05:58:07 PM PDT 24
Finished Aug 13 06:03:09 PM PDT 24
Peak memory 459272 kb
Host smart-1e2824c2-469e-4e39-a5b2-bdace26a9711
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480586338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.48
0586338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1747476805
Short name T556
Test name
Test status
Simulation time 9668532801 ps
CPU time 293.6 seconds
Started Aug 13 05:58:06 PM PDT 24
Finished Aug 13 06:02:59 PM PDT 24
Peak memory 482080 kb
Host smart-7b86d840-56ed-46bb-8fd8-ffce0e46daa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747476805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1747476805 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.3572429286
Short name T549
Test name
Test status
Simulation time 3393229494 ps
CPU time 9.4 seconds
Started Aug 13 05:58:05 PM PDT 24
Finished Aug 13 05:58:14 PM PDT 24
Peak memory 218844 kb
Host smart-445849a6-e805-49c3-8b09-3725cd961f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572429286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3572429286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.455729217
Short name T244
Test name
Test status
Simulation time 171261559 ps
CPU time 1.5 seconds
Started Aug 13 05:58:08 PM PDT 24
Finished Aug 13 05:58:09 PM PDT 24
Peak memory 217028 kb
Host smart-59cdcae5-c813-4911-8a24-68535d9ddd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455729217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.455729217 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.926910221
Short name T543
Test name
Test status
Simulation time 90630392671 ps
CPU time 3449.13 seconds
Started Aug 13 05:57:57 PM PDT 24
Finished Aug 13 06:55:27 PM PDT 24
Peak memory 1842980 kb
Host smart-b5807942-e40b-41f8-8a5a-9033fd22f1ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926910221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.926910221 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.4114356845
Short name T513
Test name
Test status
Simulation time 5017588246 ps
CPU time 117.5 seconds
Started Aug 13 05:58:07 PM PDT 24
Finished Aug 13 06:00:05 PM PDT 24
Peak memory 329476 kb
Host smart-2621cd84-1968-4964-ab04-4f33c01aae13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114356845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.4114356845 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.2364269135
Short name T374
Test name
Test status
Simulation time 8889668155 ps
CPU time 44.74 seconds
Started Aug 13 05:57:58 PM PDT 24
Finished Aug 13 05:58:43 PM PDT 24
Peak memory 218288 kb
Host smart-3172e53a-22e1-409b-a9ff-fddce9a43aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364269135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2364269135 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.1950439257
Short name T671
Test name
Test status
Simulation time 40476731455 ps
CPU time 1103.25 seconds
Started Aug 13 05:58:07 PM PDT 24
Finished Aug 13 06:16:31 PM PDT 24
Peak memory 888340 kb
Host smart-5aa1d659-22f0-4829-bc9e-d368e98f73a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1950439257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1950439257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2871986308
Short name T479
Test name
Test status
Simulation time 15499473 ps
CPU time 0.8 seconds
Started Aug 13 05:58:06 PM PDT 24
Finished Aug 13 05:58:07 PM PDT 24
Peak memory 204884 kb
Host smart-f67d858f-3a4d-46d5-93b1-f75dc51afeae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871986308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2871986308 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2947845410
Short name T433
Test name
Test status
Simulation time 110126469799 ps
CPU time 369.34 seconds
Started Aug 13 05:58:09 PM PDT 24
Finished Aug 13 06:04:18 PM PDT 24
Peak memory 492788 kb
Host smart-25d427cf-8015-4225-b741-5198a62ec874
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947845410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2947845410 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.2629863171
Short name T483
Test name
Test status
Simulation time 22915993668 ps
CPU time 681.43 seconds
Started Aug 13 05:58:05 PM PDT 24
Finished Aug 13 06:09:27 PM PDT 24
Peak memory 249088 kb
Host smart-dc199bdd-d2ef-4ca5-bb1a-fb40e9777c5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629863171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.262986317
1 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.563849272
Short name T248
Test name
Test status
Simulation time 46131474263 ps
CPU time 275.27 seconds
Started Aug 13 05:58:03 PM PDT 24
Finished Aug 13 06:02:38 PM PDT 24
Peak memory 435764 kb
Host smart-dc2d28c7-fd90-4065-8e38-b8ea8bb9ad38
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563849272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.56
3849272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.1653158692
Short name T588
Test name
Test status
Simulation time 49698186171 ps
CPU time 320.38 seconds
Started Aug 13 05:58:05 PM PDT 24
Finished Aug 13 06:03:26 PM PDT 24
Peak memory 518224 kb
Host smart-692a1a37-e477-41de-8ef2-fd67c9165162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653158692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1653158692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.4042877228
Short name T507
Test name
Test status
Simulation time 1068735142 ps
CPU time 2.28 seconds
Started Aug 13 05:58:06 PM PDT 24
Finished Aug 13 05:58:09 PM PDT 24
Peak memory 217752 kb
Host smart-341996b9-9efb-4566-b278-615f8e53da5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042877228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.4042877228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.64879240
Short name T301
Test name
Test status
Simulation time 56533155 ps
CPU time 1.77 seconds
Started Aug 13 05:58:05 PM PDT 24
Finished Aug 13 05:58:07 PM PDT 24
Peak memory 217644 kb
Host smart-b6476422-2aa5-4959-92f9-df0a17a6994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64879240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.64879240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.3762111661
Short name T219
Test name
Test status
Simulation time 23661482735 ps
CPU time 1149.8 seconds
Started Aug 13 05:58:07 PM PDT 24
Finished Aug 13 06:17:17 PM PDT 24
Peak memory 922412 kb
Host smart-e073d3e5-280e-4e38-8f04-f114f8ea589c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762111661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.3762111661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.3855633226
Short name T388
Test name
Test status
Simulation time 2322210722 ps
CPU time 185.1 seconds
Started Aug 13 05:58:04 PM PDT 24
Finished Aug 13 06:01:09 PM PDT 24
Peak memory 296012 kb
Host smart-87c34ee9-75cb-4028-a15f-9d859d6c2851
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855633226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3855633226 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.1105679648
Short name T190
Test name
Test status
Simulation time 1613027411 ps
CPU time 42.32 seconds
Started Aug 13 05:58:04 PM PDT 24
Finished Aug 13 05:58:46 PM PDT 24
Peak memory 223008 kb
Host smart-374851a7-779f-4739-a745-eb571ac883e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105679648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1105679648 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.3958525296
Short name T602
Test name
Test status
Simulation time 6147326044 ps
CPU time 200.08 seconds
Started Aug 13 05:58:07 PM PDT 24
Finished Aug 13 06:01:27 PM PDT 24
Peak memory 229068 kb
Host smart-879051da-9824-48cc-a969-8c1c65cbf53c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3958525296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3958525296 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_alert_test.75501661
Short name T654
Test name
Test status
Simulation time 18022578 ps
CPU time 0.79 seconds
Started Aug 13 05:58:14 PM PDT 24
Finished Aug 13 05:58:15 PM PDT 24
Peak memory 204916 kb
Host smart-6eca5d71-f25f-4fba-931c-5889a8155414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75501661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.75501661 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.4228780318
Short name T406
Test name
Test status
Simulation time 11079202287 ps
CPU time 166.96 seconds
Started Aug 13 05:58:15 PM PDT 24
Finished Aug 13 06:01:02 PM PDT 24
Peak memory 291684 kb
Host smart-b7b0ae8e-426d-40b9-b5c8-fdd18c82c178
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228780318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.4228780318 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.921249193
Short name T567
Test name
Test status
Simulation time 68773184373 ps
CPU time 480.4 seconds
Started Aug 13 05:58:15 PM PDT 24
Finished Aug 13 06:06:15 PM PDT 24
Peak memory 240292 kb
Host smart-e12379e7-ca18-4252-b682-1422d04d085b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921249193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.921249193
+enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.3036757155
Short name T720
Test name
Test status
Simulation time 10900337984 ps
CPU time 100.46 seconds
Started Aug 13 05:58:16 PM PDT 24
Finished Aug 13 05:59:57 PM PDT 24
Peak memory 262968 kb
Host smart-b0be7a53-3714-4b51-9610-09f0add6ab85
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036757155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3
036757155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.1229837480
Short name T167
Test name
Test status
Simulation time 2469039002 ps
CPU time 49.12 seconds
Started Aug 13 05:58:16 PM PDT 24
Finished Aug 13 05:59:05 PM PDT 24
Peak memory 248464 kb
Host smart-7e387390-3e1a-4b21-851a-a8d304d926f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229837480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1229837480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.2966954241
Short name T22
Test name
Test status
Simulation time 554725914 ps
CPU time 2.65 seconds
Started Aug 13 05:58:15 PM PDT 24
Finished Aug 13 05:58:17 PM PDT 24
Peak memory 217408 kb
Host smart-6f521630-a81d-4b19-b878-57fa88fbf13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966954241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2966954241 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.436892400
Short name T568
Test name
Test status
Simulation time 6475847445 ps
CPU time 596.37 seconds
Started Aug 13 05:58:13 PM PDT 24
Finished Aug 13 06:08:10 PM PDT 24
Peak memory 591236 kb
Host smart-f7d58a4b-c11b-409f-a158-9595b9fc8590
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436892400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an
d_output.436892400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.390558223
Short name T449
Test name
Test status
Simulation time 1503354708 ps
CPU time 123.14 seconds
Started Aug 13 05:58:13 PM PDT 24
Finished Aug 13 06:00:16 PM PDT 24
Peak memory 268556 kb
Host smart-cbff3489-5eb6-4bfc-91d2-98c6165dd8c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390558223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.390558223 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.2323183335
Short name T431
Test name
Test status
Simulation time 6900382143 ps
CPU time 31.1 seconds
Started Aug 13 05:58:09 PM PDT 24
Finished Aug 13 05:58:40 PM PDT 24
Peak memory 217888 kb
Host smart-352c4c62-ee82-4b5f-a557-60ed680dcabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323183335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2323183335 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_alert_test.3992793181
Short name T451
Test name
Test status
Simulation time 16205856 ps
CPU time 0.82 seconds
Started Aug 13 05:58:23 PM PDT 24
Finished Aug 13 05:58:24 PM PDT 24
Peak memory 204940 kb
Host smart-8466747b-107b-4cfc-a3be-1bfbd4ab9687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992793181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3992793181 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2691946061
Short name T212
Test name
Test status
Simulation time 36058218876 ps
CPU time 260.06 seconds
Started Aug 13 05:58:21 PM PDT 24
Finished Aug 13 06:02:41 PM PDT 24
Peak memory 427656 kb
Host smart-76bd6afa-33e6-4902-9288-e8fa9964a0c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691946061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2691946061 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.579043103
Short name T695
Test name
Test status
Simulation time 104326190062 ps
CPU time 466.35 seconds
Started Aug 13 05:58:22 PM PDT 24
Finished Aug 13 06:06:08 PM PDT 24
Peak memory 240496 kb
Host smart-890326db-610c-454f-8ae2-9e2619ebe124
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579043103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.579043103
+enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.2569409443
Short name T683
Test name
Test status
Simulation time 2336200219 ps
CPU time 14.11 seconds
Started Aug 13 05:58:26 PM PDT 24
Finished Aug 13 05:58:40 PM PDT 24
Peak memory 220704 kb
Host smart-9e660e9b-6045-4633-8114-dd0776a0e352
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569409443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2
569409443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.2983793719
Short name T540
Test name
Test status
Simulation time 74547028297 ps
CPU time 414.03 seconds
Started Aug 13 05:58:26 PM PDT 24
Finished Aug 13 06:05:20 PM PDT 24
Peak memory 587308 kb
Host smart-0a20e9e3-3fe4-4f12-8e33-4aeaf6c2b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983793719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2983793719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.4257809581
Short name T455
Test name
Test status
Simulation time 1906085864 ps
CPU time 5.23 seconds
Started Aug 13 05:58:26 PM PDT 24
Finished Aug 13 05:58:31 PM PDT 24
Peak memory 217608 kb
Host smart-f4d98738-9a6b-48cb-8355-20d3c58121e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257809581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.4257809581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.1553231494
Short name T78
Test name
Test status
Simulation time 94021560 ps
CPU time 1.31 seconds
Started Aug 13 05:58:23 PM PDT 24
Finished Aug 13 05:58:24 PM PDT 24
Peak memory 219072 kb
Host smart-8b3f31b5-b5f6-4cbb-a1fa-4827b948636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553231494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1553231494 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_sideload.4227742247
Short name T274
Test name
Test status
Simulation time 13951411575 ps
CPU time 425.81 seconds
Started Aug 13 05:58:21 PM PDT 24
Finished Aug 13 06:05:27 PM PDT 24
Peak memory 579584 kb
Host smart-3834d63a-13a9-40d2-91e6-119f6fb7cbe6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227742247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.4227742247 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.122117361
Short name T236
Test name
Test status
Simulation time 6101583431 ps
CPU time 54.99 seconds
Started Aug 13 05:58:15 PM PDT 24
Finished Aug 13 05:59:11 PM PDT 24
Peak memory 217656 kb
Host smart-840e6858-20b3-48bb-9407-1816b1c4e1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122117361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.122117361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.2502314132
Short name T273
Test name
Test status
Simulation time 10408742075 ps
CPU time 452.08 seconds
Started Aug 13 05:58:23 PM PDT 24
Finished Aug 13 06:05:55 PM PDT 24
Peak memory 454596 kb
Host smart-3985491a-2939-4232-877e-830993b28959
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2502314132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2502314132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_alert_test.3797360353
Short name T484
Test name
Test status
Simulation time 46360992 ps
CPU time 0.79 seconds
Started Aug 13 05:58:32 PM PDT 24
Finished Aug 13 05:58:33 PM PDT 24
Peak memory 204908 kb
Host smart-5fbd32c6-10c8-4bfd-a7ce-82b56c6f89e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797360353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3797360353 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.1866822308
Short name T160
Test name
Test status
Simulation time 933167182 ps
CPU time 45.78 seconds
Started Aug 13 05:58:32 PM PDT 24
Finished Aug 13 05:59:18 PM PDT 24
Peak memory 239496 kb
Host smart-7054e32b-3552-45f4-a0f5-b2cb19e1c3d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866822308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1866822308 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.1148748179
Short name T380
Test name
Test status
Simulation time 46657599750 ps
CPU time 616.54 seconds
Started Aug 13 05:58:22 PM PDT 24
Finished Aug 13 06:08:39 PM PDT 24
Peak memory 237684 kb
Host smart-b3927647-a7a4-4a2e-994f-661fe896d2aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148748179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.114874817
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.389223016
Short name T569
Test name
Test status
Simulation time 38954343180 ps
CPU time 197.75 seconds
Started Aug 13 05:58:32 PM PDT 24
Finished Aug 13 06:01:50 PM PDT 24
Peak memory 304728 kb
Host smart-6fe0b404-13f1-4f95-898f-d8d80834d5ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389223016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.38
9223016 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2295351268
Short name T597
Test name
Test status
Simulation time 9259643643 ps
CPU time 262.25 seconds
Started Aug 13 05:58:32 PM PDT 24
Finished Aug 13 06:02:54 PM PDT 24
Peak memory 468340 kb
Host smart-4dd41b9b-1e97-4c7b-b423-532341b99b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295351268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2295351268 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.2181568801
Short name T60
Test name
Test status
Simulation time 2535647686 ps
CPU time 6.07 seconds
Started Aug 13 05:58:32 PM PDT 24
Finished Aug 13 05:58:38 PM PDT 24
Peak memory 217772 kb
Host smart-507f6402-3802-43df-a5cf-f9aecb2c8608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181568801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2181568801 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.3609756881
Short name T619
Test name
Test status
Simulation time 100791306 ps
CPU time 1.29 seconds
Started Aug 13 05:58:32 PM PDT 24
Finished Aug 13 05:58:33 PM PDT 24
Peak memory 219000 kb
Host smart-bda8a606-a8b5-4dfb-a1b2-020d3b244921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609756881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3609756881 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_sideload.2803026158
Short name T544
Test name
Test status
Simulation time 23287763363 ps
CPU time 318.03 seconds
Started Aug 13 05:58:24 PM PDT 24
Finished Aug 13 06:03:42 PM PDT 24
Peak memory 347376 kb
Host smart-62d7b8a8-7173-4880-9d08-4584b039d067
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803026158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2803026158 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.1799872420
Short name T497
Test name
Test status
Simulation time 2797828074 ps
CPU time 50.46 seconds
Started Aug 13 05:58:23 PM PDT 24
Finished Aug 13 05:59:14 PM PDT 24
Peak memory 218532 kb
Host smart-e8c74be0-58a7-47b6-a515-1106dcf46ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799872420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1799872420 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.4165168270
Short name T490
Test name
Test status
Simulation time 8215351203 ps
CPU time 407.25 seconds
Started Aug 13 05:58:31 PM PDT 24
Finished Aug 13 06:05:18 PM PDT 24
Peak memory 314320 kb
Host smart-635d5517-7c7d-40ab-88b0-9bd342dbe6e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4165168270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4165168270 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_alert_test.2330829090
Short name T562
Test name
Test status
Simulation time 22459976 ps
CPU time 0.83 seconds
Started Aug 13 05:58:41 PM PDT 24
Finished Aug 13 05:58:42 PM PDT 24
Peak memory 204916 kb
Host smart-5c6444bf-3f83-4a05-bbbf-78e62fd84df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330829090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2330829090 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.2736966275
Short name T628
Test name
Test status
Simulation time 1581947630 ps
CPU time 53.69 seconds
Started Aug 13 05:58:38 PM PDT 24
Finished Aug 13 05:59:32 PM PDT 24
Peak memory 238980 kb
Host smart-0ac7bf97-4a15-4046-a09e-80bec4627fb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736966275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2736966275 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.979885325
Short name T559
Test name
Test status
Simulation time 67488122250 ps
CPU time 675.95 seconds
Started Aug 13 05:58:32 PM PDT 24
Finished Aug 13 06:09:48 PM PDT 24
Peak memory 248176 kb
Host smart-14ae8b35-9048-441d-bf8e-193bf22f1d4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979885325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.979885325
+enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1906867631
Short name T365
Test name
Test status
Simulation time 16882123251 ps
CPU time 94.57 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 06:00:14 PM PDT 24
Peak memory 256972 kb
Host smart-16d6d6ed-107f-4fd0-b548-5d0bf81f39c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906867631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1
906867631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.2493757125
Short name T385
Test name
Test status
Simulation time 5605181056 ps
CPU time 123.97 seconds
Started Aug 13 05:58:40 PM PDT 24
Finished Aug 13 06:00:44 PM PDT 24
Peak memory 326096 kb
Host smart-9e0b2605-2c58-46d5-b5a1-6e3a90c2bfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493757125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2493757125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2365856120
Short name T586
Test name
Test status
Simulation time 181070651 ps
CPU time 1.4 seconds
Started Aug 13 05:58:40 PM PDT 24
Finished Aug 13 05:58:41 PM PDT 24
Peak memory 218676 kb
Host smart-79a588e1-df53-47e8-8eae-81f0d559a288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365856120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2365856120 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.550149365
Short name T430
Test name
Test status
Simulation time 47461847 ps
CPU time 1.3 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 05:58:40 PM PDT 24
Peak memory 218748 kb
Host smart-66068b46-3036-4285-aa29-222d3487aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550149365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.550149365 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.2165817440
Short name T410
Test name
Test status
Simulation time 80478330401 ps
CPU time 5137.14 seconds
Started Aug 13 05:58:31 PM PDT 24
Finished Aug 13 07:24:09 PM PDT 24
Peak memory 3980340 kb
Host smart-b8a7c86f-2f34-4a73-a89b-df859f27610d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165817440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.2165817440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.729938885
Short name T187
Test name
Test status
Simulation time 12519426979 ps
CPU time 294.07 seconds
Started Aug 13 05:58:30 PM PDT 24
Finished Aug 13 06:03:25 PM PDT 24
Peak memory 470400 kb
Host smart-0ce7669a-a604-4990-8513-88ef9487ba74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729938885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.729938885 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.4213266714
Short name T250
Test name
Test status
Simulation time 1360410499 ps
CPU time 16.45 seconds
Started Aug 13 05:58:32 PM PDT 24
Finished Aug 13 05:58:49 PM PDT 24
Peak memory 217928 kb
Host smart-23dea751-fb58-4954-864e-5488c4492086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213266714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.4213266714 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.1698369650
Short name T305
Test name
Test status
Simulation time 6422709255 ps
CPU time 174.98 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 06:01:34 PM PDT 24
Peak memory 303860 kb
Host smart-e41eb4a5-90fa-4ff3-918d-7c0ea519dd2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1698369650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1698369650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_alert_test.4128821529
Short name T200
Test name
Test status
Simulation time 19370957 ps
CPU time 0.87 seconds
Started Aug 13 05:58:38 PM PDT 24
Finished Aug 13 05:58:39 PM PDT 24
Peak memory 204944 kb
Host smart-ce420808-216d-4ce5-8f06-8a02b83921ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128821529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.4128821529 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.2141051427
Short name T625
Test name
Test status
Simulation time 1660853028 ps
CPU time 75.51 seconds
Started Aug 13 05:58:42 PM PDT 24
Finished Aug 13 05:59:58 PM PDT 24
Peak memory 252576 kb
Host smart-403c8436-8bc0-41db-a7c9-1d847befa75a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141051427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2141051427 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.409745769
Short name T359
Test name
Test status
Simulation time 6557900870 ps
CPU time 573.93 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 06:08:13 PM PDT 24
Peak memory 237636 kb
Host smart-f140462f-7e8e-4753-b54f-0408c61b7c3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409745769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.409745769
+enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.4240549597
Short name T186
Test name
Test status
Simulation time 26560961013 ps
CPU time 267.56 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 06:03:07 PM PDT 24
Peak memory 442236 kb
Host smart-d3befdf6-9844-418e-8d93-d8e64d0a557e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240549597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.4
240549597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.156901084
Short name T30
Test name
Test status
Simulation time 6615380767 ps
CPU time 222.79 seconds
Started Aug 13 05:58:41 PM PDT 24
Finished Aug 13 06:02:23 PM PDT 24
Peak memory 337072 kb
Host smart-c382d74c-c76b-4664-b44b-e77051687b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156901084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.156901084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.1274761009
Short name T363
Test name
Test status
Simulation time 411139628 ps
CPU time 3.07 seconds
Started Aug 13 05:58:36 PM PDT 24
Finished Aug 13 05:58:39 PM PDT 24
Peak memory 217484 kb
Host smart-c3e64fc2-dc00-4abc-ac0a-8bf1ba18bd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274761009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1274761009 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.629977035
Short name T105
Test name
Test status
Simulation time 383237407 ps
CPU time 1.44 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 05:58:41 PM PDT 24
Peak memory 217068 kb
Host smart-da67f413-f195-4673-a24a-f4864f842459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629977035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.629977035 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.207893441
Short name T729
Test name
Test status
Simulation time 20770922241 ps
CPU time 2508.5 seconds
Started Aug 13 05:58:38 PM PDT 24
Finished Aug 13 06:40:27 PM PDT 24
Peak memory 1483812 kb
Host smart-34fdfb49-80d2-4c35-aa07-583b33ba0eb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207893441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_an
d_output.207893441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.3570817077
Short name T251
Test name
Test status
Simulation time 12504835476 ps
CPU time 191.1 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 06:01:50 PM PDT 24
Peak memory 389684 kb
Host smart-4666d68c-9ef4-4413-9c52-ca2154131e65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570817077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3570817077 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.2697635585
Short name T16
Test name
Test status
Simulation time 1280235370 ps
CPU time 19.94 seconds
Started Aug 13 05:58:39 PM PDT 24
Finished Aug 13 05:58:59 PM PDT 24
Peak memory 218120 kb
Host smart-fa992f1c-3226-4171-9be1-91904fe14b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697635585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2697635585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.4218255737
Short name T565
Test name
Test status
Simulation time 47577612951 ps
CPU time 1492.81 seconds
Started Aug 13 05:58:36 PM PDT 24
Finished Aug 13 06:23:30 PM PDT 24
Peak memory 908088 kb
Host smart-128a3ef2-489b-427d-ae8c-220623d214e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4218255737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.4218255737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_alert_test.1689457041
Short name T590
Test name
Test status
Simulation time 15781753 ps
CPU time 0.79 seconds
Started Aug 13 05:58:48 PM PDT 24
Finished Aug 13 05:58:49 PM PDT 24
Peak memory 204960 kb
Host smart-dc26208b-c5d2-401a-91ae-dac1d9ea7298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689457041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1689457041 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.2999949799
Short name T552
Test name
Test status
Simulation time 135265421544 ps
CPU time 207.84 seconds
Started Aug 13 05:58:48 PM PDT 24
Finished Aug 13 06:02:16 PM PDT 24
Peak memory 389356 kb
Host smart-9a026d03-7111-4d52-8543-3ce066b9542f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999949799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2999949799 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.274349282
Short name T232
Test name
Test status
Simulation time 54371014030 ps
CPU time 524.17 seconds
Started Aug 13 05:58:49 PM PDT 24
Finished Aug 13 06:07:33 PM PDT 24
Peak memory 242164 kb
Host smart-9b7b4f36-7bee-4026-a44a-b7c87bf0c3b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274349282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.274349282
+enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.2364585367
Short name T491
Test name
Test status
Simulation time 1713538345 ps
CPU time 54.83 seconds
Started Aug 13 05:58:47 PM PDT 24
Finished Aug 13 05:59:42 PM PDT 24
Peak memory 238960 kb
Host smart-ef0d6bd9-684c-4fb0-8778-47e70d5bc778
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364585367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2
364585367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.3149400655
Short name T169
Test name
Test status
Simulation time 7911736613 ps
CPU time 194.52 seconds
Started Aug 13 05:58:47 PM PDT 24
Finished Aug 13 06:02:02 PM PDT 24
Peak memory 300804 kb
Host smart-bc840bba-42f9-4efc-9e3a-6b4594f0d29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149400655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3149400655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.2711767995
Short name T55
Test name
Test status
Simulation time 3875329833 ps
CPU time 5.67 seconds
Started Aug 13 05:58:48 PM PDT 24
Finished Aug 13 05:58:53 PM PDT 24
Peak memory 217752 kb
Host smart-21e299b4-16c7-45b1-ac78-5c8e1720f15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711767995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2711767995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.3777752326
Short name T716
Test name
Test status
Simulation time 38636342 ps
CPU time 1.2 seconds
Started Aug 13 05:58:48 PM PDT 24
Finished Aug 13 05:58:50 PM PDT 24
Peak memory 217084 kb
Host smart-21ebdee0-f080-4b20-a483-102df7f51b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777752326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3777752326 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.2865075690
Short name T651
Test name
Test status
Simulation time 213075139430 ps
CPU time 2304.4 seconds
Started Aug 13 05:58:50 PM PDT 24
Finished Aug 13 06:37:14 PM PDT 24
Peak memory 2374832 kb
Host smart-1df0ae65-705e-4e6f-bab0-4b784e0eba45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865075690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.2865075690 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.461719927
Short name T512
Test name
Test status
Simulation time 47627359642 ps
CPU time 363.71 seconds
Started Aug 13 05:58:46 PM PDT 24
Finished Aug 13 06:04:50 PM PDT 24
Peak memory 548304 kb
Host smart-882bfa24-835b-4a34-a62e-d835db4d9a16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461719927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.461719927 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.2057818921
Short name T698
Test name
Test status
Simulation time 5341434158 ps
CPU time 22.34 seconds
Started Aug 13 05:58:47 PM PDT 24
Finished Aug 13 05:59:10 PM PDT 24
Peak memory 218068 kb
Host smart-a2f021b2-e8cd-48eb-a53b-456af2db6ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057818921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2057818921 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.1610555147
Short name T521
Test name
Test status
Simulation time 2225596589 ps
CPU time 45.31 seconds
Started Aug 13 05:58:47 PM PDT 24
Finished Aug 13 05:59:32 PM PDT 24
Peak memory 250816 kb
Host smart-0005de01-d531-4137-a4d8-c34bdffc2de6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1610555147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1610555147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_alert_test.1464643061
Short name T687
Test name
Test status
Simulation time 30392023 ps
CPU time 0.82 seconds
Started Aug 13 05:59:01 PM PDT 24
Finished Aug 13 05:59:02 PM PDT 24
Peak memory 204888 kb
Host smart-5a12630d-ff14-4920-8ba0-69fcbd636023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464643061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1464643061 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.4079575877
Short name T298
Test name
Test status
Simulation time 5561346787 ps
CPU time 156.99 seconds
Started Aug 13 05:59:00 PM PDT 24
Finished Aug 13 06:01:37 PM PDT 24
Peak memory 281948 kb
Host smart-cd18e267-31a0-4c83-869c-0dd5caef269c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079575877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.4079575877 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.680691588
Short name T494
Test name
Test status
Simulation time 11529568576 ps
CPU time 518.65 seconds
Started Aug 13 05:59:02 PM PDT 24
Finished Aug 13 06:07:41 PM PDT 24
Peak memory 236804 kb
Host smart-5f338a28-6918-4b04-9161-d393571211cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680691588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.680691588
+enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1930771594
Short name T206
Test name
Test status
Simulation time 34227390012 ps
CPU time 327.3 seconds
Started Aug 13 05:59:02 PM PDT 24
Finished Aug 13 06:04:30 PM PDT 24
Peak memory 473104 kb
Host smart-8dde8d97-ca4a-481b-a54c-aafab1403c39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930771594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1
930771594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_key_error.1596749036
Short name T315
Test name
Test status
Simulation time 5272397339 ps
CPU time 7.23 seconds
Started Aug 13 05:59:02 PM PDT 24
Finished Aug 13 05:59:10 PM PDT 24
Peak memory 218852 kb
Host smart-d4ab113b-3dc2-4ca9-b789-8290a3dacf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596749036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1596749036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.2581067087
Short name T7
Test name
Test status
Simulation time 6077055310 ps
CPU time 46.96 seconds
Started Aug 13 05:59:01 PM PDT 24
Finished Aug 13 05:59:48 PM PDT 24
Peak memory 248016 kb
Host smart-8ada29c9-a3b5-4541-827f-176e7544316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581067087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2581067087 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.672473527
Short name T614
Test name
Test status
Simulation time 160868971442 ps
CPU time 1017.99 seconds
Started Aug 13 05:59:00 PM PDT 24
Finished Aug 13 06:15:58 PM PDT 24
Peak memory 1373648 kb
Host smart-84dd3aba-4985-4783-9b97-f202424b9fa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672473527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_an
d_output.672473527 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.529269177
Short name T672
Test name
Test status
Simulation time 6185372869 ps
CPU time 135.93 seconds
Started Aug 13 05:59:01 PM PDT 24
Finished Aug 13 06:01:17 PM PDT 24
Peak memory 273184 kb
Host smart-f78428be-eedc-48e6-bcdb-02c77aaf20cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529269177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.529269177 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.3919400042
Short name T481
Test name
Test status
Simulation time 2728782554 ps
CPU time 40.87 seconds
Started Aug 13 05:58:45 PM PDT 24
Finished Aug 13 05:59:26 PM PDT 24
Peak memory 217736 kb
Host smart-d45da144-6b7f-4342-8d1f-d3211bf4b4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919400042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3919400042 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.3179450451
Short name T348
Test name
Test status
Simulation time 6741190196 ps
CPU time 161.5 seconds
Started Aug 13 05:59:01 PM PDT 24
Finished Aug 13 06:01:43 PM PDT 24
Peak memory 377844 kb
Host smart-df5c6a17-0abd-43ed-adb1-eba436d1c233
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3179450451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3179450451 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_alert_test.1672997771
Short name T725
Test name
Test status
Simulation time 58839443 ps
CPU time 0.79 seconds
Started Aug 13 05:59:05 PM PDT 24
Finished Aug 13 05:59:05 PM PDT 24
Peak memory 204944 kb
Host smart-a303fd3d-2734-4f36-8937-04405fe5d5b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672997771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1672997771 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.3866902934
Short name T162
Test name
Test status
Simulation time 113244648376 ps
CPU time 336.32 seconds
Started Aug 13 05:59:04 PM PDT 24
Finished Aug 13 06:04:41 PM PDT 24
Peak memory 515288 kb
Host smart-462da1e7-53dd-42d1-84f8-8a9f1810bd7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866902934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3866902934 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.1408112659
Short name T147
Test name
Test status
Simulation time 47380208160 ps
CPU time 474.84 seconds
Started Aug 13 05:59:05 PM PDT 24
Finished Aug 13 06:07:00 PM PDT 24
Peak memory 244372 kb
Host smart-5a7ab405-32a4-47cf-b48e-102a68311e72
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408112659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.140811265
9 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.2286756822
Short name T100
Test name
Test status
Simulation time 21201682569 ps
CPU time 95.52 seconds
Started Aug 13 05:59:13 PM PDT 24
Finished Aug 13 06:00:49 PM PDT 24
Peak memory 252948 kb
Host smart-79438609-1a8c-407d-b998-0e6363658212
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286756822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2
286756822 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.2658457421
Short name T42
Test name
Test status
Simulation time 18884396174 ps
CPU time 166.5 seconds
Started Aug 13 05:59:05 PM PDT 24
Finished Aug 13 06:01:52 PM PDT 24
Peak memory 355064 kb
Host smart-75eb96a4-baf0-4563-802b-ba2ac4728173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658457421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2658457421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.1752349490
Short name T659
Test name
Test status
Simulation time 3226190418 ps
CPU time 6.03 seconds
Started Aug 13 05:59:08 PM PDT 24
Finished Aug 13 05:59:14 PM PDT 24
Peak memory 217836 kb
Host smart-821cf57a-b9d5-41d7-b16a-b865dcd26a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752349490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1752349490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.3558479648
Short name T52
Test name
Test status
Simulation time 124352568 ps
CPU time 1.59 seconds
Started Aug 13 05:59:12 PM PDT 24
Finished Aug 13 05:59:14 PM PDT 24
Peak memory 217576 kb
Host smart-68eda4fe-d81d-4386-964d-db41ac4988b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558479648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3558479648 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.1621775212
Short name T443
Test name
Test status
Simulation time 231534891854 ps
CPU time 2284.49 seconds
Started Aug 13 05:59:02 PM PDT 24
Finished Aug 13 06:37:07 PM PDT 24
Peak memory 2331680 kb
Host smart-28b51614-796d-40f2-afa5-c073407746f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621775212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.1621775212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.1853886339
Short name T386
Test name
Test status
Simulation time 23030215790 ps
CPU time 535.99 seconds
Started Aug 13 05:59:12 PM PDT 24
Finished Aug 13 06:08:09 PM PDT 24
Peak memory 690668 kb
Host smart-9864873d-9f4e-4de7-9171-8d8dadfef949
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853886339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1853886339 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.2081110213
Short name T453
Test name
Test status
Simulation time 1473536790 ps
CPU time 21.45 seconds
Started Aug 13 05:58:59 PM PDT 24
Finished Aug 13 05:59:21 PM PDT 24
Peak memory 219492 kb
Host smart-857709dd-4692-4a6b-ad89-22d83927bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081110213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2081110213 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.3441572107
Short name T371
Test name
Test status
Simulation time 148743709462 ps
CPU time 3283.98 seconds
Started Aug 13 05:59:05 PM PDT 24
Finished Aug 13 06:53:50 PM PDT 24
Peak memory 1751632 kb
Host smart-8f6014e8-766f-4a4f-8daf-773df2dc8aad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3441572107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3441572107 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_alert_test.2158520952
Short name T510
Test name
Test status
Simulation time 16048353 ps
CPU time 0.79 seconds
Started Aug 13 05:55:21 PM PDT 24
Finished Aug 13 05:55:22 PM PDT 24
Peak memory 204948 kb
Host smart-1228c963-2272-4fff-8eda-a39305793a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158520952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2158520952 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.2007001961
Short name T596
Test name
Test status
Simulation time 26332700582 ps
CPU time 140.42 seconds
Started Aug 13 05:55:23 PM PDT 24
Finished Aug 13 05:57:43 PM PDT 24
Peak memory 330648 kb
Host smart-7596bb46-2293-481d-8bf1-e8ac25ceb021
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007001961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2007001961 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.3975947821
Short name T238
Test name
Test status
Simulation time 32022011448 ps
CPU time 281.81 seconds
Started Aug 13 05:55:24 PM PDT 24
Finished Aug 13 06:00:06 PM PDT 24
Peak memory 433568 kb
Host smart-9a38d92c-3d17-4373-91d6-249230638a3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975947821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_par
tial_data.3975947821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.1914513098
Short name T489
Test name
Test status
Simulation time 37233322038 ps
CPU time 890.77 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 06:10:13 PM PDT 24
Peak memory 240724 kb
Host smart-22d8d8ce-d884-4d2f-9275-7dc2a0564bfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914513098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1914513098
+enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1673028411
Short name T730
Test name
Test status
Simulation time 880575760 ps
CPU time 17.05 seconds
Started Aug 13 05:55:23 PM PDT 24
Finished Aug 13 05:55:40 PM PDT 24
Peak memory 218568 kb
Host smart-f915f0d5-2db0-4039-905e-24fca06812de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1673028411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1673028411 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.3414533194
Short name T660
Test name
Test status
Simulation time 191213982 ps
CPU time 14.13 seconds
Started Aug 13 05:55:21 PM PDT 24
Finished Aug 13 05:55:36 PM PDT 24
Peak memory 223644 kb
Host smart-3ac733bb-9d3b-47ed-b160-df6b74e4ffd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3414533194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3414533194 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2083201900
Short name T397
Test name
Test status
Simulation time 6231263903 ps
CPU time 58.81 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 05:56:20 PM PDT 24
Peak memory 218356 kb
Host smart-91371f2f-7374-495d-9b79-83740071bd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083201900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2083201900 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.2646666892
Short name T438
Test name
Test status
Simulation time 1639109181 ps
CPU time 24.7 seconds
Started Aug 13 05:55:23 PM PDT 24
Finished Aug 13 05:55:48 PM PDT 24
Peak memory 239080 kb
Host smart-d4dd1aa4-146a-43ef-b94d-e8f47a6610b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646666892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.26
46666892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.3719914640
Short name T699
Test name
Test status
Simulation time 6293896007 ps
CPU time 34.18 seconds
Started Aug 13 05:55:21 PM PDT 24
Finished Aug 13 05:55:56 PM PDT 24
Peak memory 250412 kb
Host smart-466fcada-af4f-4d13-8ac4-b07b485f2c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719914640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3719914640 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.2265623904
Short name T295
Test name
Test status
Simulation time 3586377720 ps
CPU time 6.76 seconds
Started Aug 13 05:55:23 PM PDT 24
Finished Aug 13 05:55:30 PM PDT 24
Peak memory 217652 kb
Host smart-c44e98c1-d7d8-445b-b0be-94695bcd9e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265623904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2265623904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.2975497499
Short name T10
Test name
Test status
Simulation time 403933907 ps
CPU time 1.39 seconds
Started Aug 13 05:55:21 PM PDT 24
Finished Aug 13 05:55:23 PM PDT 24
Peak memory 218776 kb
Host smart-a070d5f4-35d7-4d30-b9b7-8ae1aad35bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975497499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2975497499 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.2599309630
Short name T450
Test name
Test status
Simulation time 94724133676 ps
CPU time 2162.71 seconds
Started Aug 13 05:55:20 PM PDT 24
Finished Aug 13 06:31:23 PM PDT 24
Peak memory 1332272 kb
Host smart-bf29e48b-8de3-45e6-be82-896df8ceed30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599309630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.2599309630 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.3351555078
Short name T70
Test name
Test status
Simulation time 22676845468 ps
CPU time 244.8 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 05:59:27 PM PDT 24
Peak memory 435492 kb
Host smart-5b616bf3-60f4-4b13-ae68-a06c631ffe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351555078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3351555078 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.3576437553
Short name T420
Test name
Test status
Simulation time 81204222975 ps
CPU time 371.83 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 06:01:34 PM PDT 24
Peak memory 542132 kb
Host smart-5fa0d549-0af3-4c2b-b73a-78b3a60769ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576437553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3576437553 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.3660738925
Short name T320
Test name
Test status
Simulation time 3832560238 ps
CPU time 40.77 seconds
Started Aug 13 05:55:23 PM PDT 24
Finished Aug 13 05:56:04 PM PDT 24
Peak memory 222624 kb
Host smart-456f134a-e6c1-4b01-a23b-0912781c52ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660738925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3660738925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.2367806454
Short name T400
Test name
Test status
Simulation time 17154320468 ps
CPU time 245.27 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 05:59:28 PM PDT 24
Peak memory 549508 kb
Host smart-c8961ab1-3a35-4272-b792-9c0415879e45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2367806454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2367806454 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_alert_test.2541458481
Short name T463
Test name
Test status
Simulation time 39016860 ps
CPU time 0.73 seconds
Started Aug 13 05:55:25 PM PDT 24
Finished Aug 13 05:55:26 PM PDT 24
Peak memory 204980 kb
Host smart-cb012917-9d16-4a98-a779-d6c52e54851c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541458481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2541458481 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.2124408570
Short name T440
Test name
Test status
Simulation time 3074584871 ps
CPU time 160.92 seconds
Started Aug 13 05:55:26 PM PDT 24
Finished Aug 13 05:58:07 PM PDT 24
Peak memory 289920 kb
Host smart-31892d0a-a563-4010-8930-8b7711f73583
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124408570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2124408570 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1114442526
Short name T622
Test name
Test status
Simulation time 7913386678 ps
CPU time 52.91 seconds
Started Aug 13 05:55:25 PM PDT 24
Finished Aug 13 05:56:18 PM PDT 24
Peak memory 237360 kb
Host smart-8ace2790-1e3d-4d2b-9d41-4eb9c1186888
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114442526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.1114442526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.2800013688
Short name T692
Test name
Test status
Simulation time 112521512541 ps
CPU time 1000.85 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 06:12:03 PM PDT 24
Peak memory 258848 kb
Host smart-0cb53ec4-ad17-4cab-aee7-0306f20d23ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800013688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2800013688
+enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2788668923
Short name T322
Test name
Test status
Simulation time 88373595 ps
CPU time 5.8 seconds
Started Aug 13 05:55:27 PM PDT 24
Finished Aug 13 05:55:32 PM PDT 24
Peak memory 223428 kb
Host smart-7962eebb-dd70-4e55-ac21-45e583814e8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2788668923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2788668923 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.2080747986
Short name T485
Test name
Test status
Simulation time 147931238 ps
CPU time 11.12 seconds
Started Aug 13 05:55:25 PM PDT 24
Finished Aug 13 05:55:36 PM PDT 24
Peak memory 218888 kb
Host smart-1526d27c-37e1-4938-ae1b-d28d5dee33b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2080747986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2080747986 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.440084307
Short name T37
Test name
Test status
Simulation time 3978669686 ps
CPU time 36.47 seconds
Started Aug 13 05:55:21 PM PDT 24
Finished Aug 13 05:55:58 PM PDT 24
Peak memory 217796 kb
Host smart-0d8cc5d5-1726-4b14-8d47-e9d29e5896d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440084307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.440084307 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.173532625
Short name T223
Test name
Test status
Simulation time 65200706292 ps
CPU time 350.95 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 06:01:13 PM PDT 24
Peak memory 505188 kb
Host smart-4a941a83-ccc9-4060-9d68-2d0b06b8c07a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173532625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.173
532625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.3366907917
Short name T647
Test name
Test status
Simulation time 4325456849 ps
CPU time 181.68 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 05:58:23 PM PDT 24
Peak memory 305576 kb
Host smart-f6154d35-0c75-4d6b-9cae-76e405e3f0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366907917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3366907917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.3456200953
Short name T80
Test name
Test status
Simulation time 55598609 ps
CPU time 1.1 seconds
Started Aug 13 05:55:27 PM PDT 24
Finished Aug 13 05:55:28 PM PDT 24
Peak memory 219016 kb
Host smart-92d77825-6c8d-4b96-8568-2a6865ada768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456200953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3456200953 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2415021606
Short name T608
Test name
Test status
Simulation time 66209035711 ps
CPU time 2101.05 seconds
Started Aug 13 05:55:23 PM PDT 24
Finished Aug 13 06:30:24 PM PDT 24
Peak memory 1285844 kb
Host smart-3412d035-ff69-4433-a32e-8bcf4c2af466
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415021606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2415021606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.3915390366
Short name T595
Test name
Test status
Simulation time 9307057577 ps
CPU time 38.66 seconds
Started Aug 13 05:55:27 PM PDT 24
Finished Aug 13 05:56:06 PM PDT 24
Peak memory 251136 kb
Host smart-5545e54b-fe43-4756-8b19-14679971aa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915390366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3915390366 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.1295085331
Short name T324
Test name
Test status
Simulation time 1077100061 ps
CPU time 20.97 seconds
Started Aug 13 05:55:23 PM PDT 24
Finished Aug 13 05:55:44 PM PDT 24
Peak memory 220032 kb
Host smart-a6b3c3e1-f3a7-4557-b6c3-8d1adb442331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295085331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1295085331 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.2008650333
Short name T338
Test name
Test status
Simulation time 48207912 ps
CPU time 1.54 seconds
Started Aug 13 05:55:27 PM PDT 24
Finished Aug 13 05:55:28 PM PDT 24
Peak memory 217952 kb
Host smart-9f7234ba-6bef-49d8-b36f-370fd4be46e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008650333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2008650333 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.3769023661
Short name T623
Test name
Test status
Simulation time 27492830307 ps
CPU time 957.76 seconds
Started Aug 13 05:55:25 PM PDT 24
Finished Aug 13 06:11:23 PM PDT 24
Peak memory 589680 kb
Host smart-2791bedd-f9dd-4750-9542-b41411436cbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3769023661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3769023661 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3080459907
Short name T199
Test name
Test status
Simulation time 17037251 ps
CPU time 0.82 seconds
Started Aug 13 05:55:32 PM PDT 24
Finished Aug 13 05:55:33 PM PDT 24
Peak memory 204916 kb
Host smart-92aace09-b308-4bfa-a8cf-925e87ac6953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080459907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3080459907 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.375270960
Short name T161
Test name
Test status
Simulation time 2398368260 ps
CPU time 41.81 seconds
Started Aug 13 05:55:25 PM PDT 24
Finished Aug 13 05:56:07 PM PDT 24
Peak memory 240248 kb
Host smart-429645f1-b386-467a-bb61-f6214905cdf6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375270960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.375270960 +enable_masking=0
+sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2930267704
Short name T260
Test name
Test status
Simulation time 55691156591 ps
CPU time 365.84 seconds
Started Aug 13 05:55:23 PM PDT 24
Finished Aug 13 06:01:29 PM PDT 24
Peak memory 502548 kb
Host smart-4dc4902b-7dad-4309-9373-32e1c84afcfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930267704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_par
tial_data.2930267704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.932827178
Short name T332
Test name
Test status
Simulation time 1651097676 ps
CPU time 14.41 seconds
Started Aug 13 05:55:26 PM PDT 24
Finished Aug 13 05:55:40 PM PDT 24
Peak memory 219448 kb
Host smart-b93bd937-60fb-42ac-ae4e-a3c9f9d1355a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932827178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.932827178 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.31993579
Short name T533
Test name
Test status
Simulation time 405878985 ps
CPU time 26.55 seconds
Started Aug 13 05:55:31 PM PDT 24
Finished Aug 13 05:55:58 PM PDT 24
Peak memory 219432 kb
Host smart-51a7205c-c2da-478a-9e03-3123dccfe40d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=31993579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.31993579 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.2429922732
Short name T14
Test name
Test status
Simulation time 2565799299 ps
CPU time 28.94 seconds
Started Aug 13 05:55:30 PM PDT 24
Finished Aug 13 05:55:59 PM PDT 24
Peak memory 223668 kb
Host smart-dfdec429-1707-41d0-a560-e9d289f3b169
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2429922732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2429922732 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.2929907387
Short name T422
Test name
Test status
Simulation time 5730101259 ps
CPU time 55.34 seconds
Started Aug 13 05:55:33 PM PDT 24
Finished Aug 13 05:56:29 PM PDT 24
Peak memory 218440 kb
Host smart-1889f27d-d5bb-4c95-8260-f86f8a120b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929907387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2929907387 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.648476505
Short name T321
Test name
Test status
Simulation time 13645835613 ps
CPU time 262.55 seconds
Started Aug 13 05:55:22 PM PDT 24
Finished Aug 13 05:59:44 PM PDT 24
Peak memory 425756 kb
Host smart-46ac89ff-f724-44c1-b9f3-e16d26345d0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648476505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.648
476505 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.554355621
Short name T447
Test name
Test status
Simulation time 21319149753 ps
CPU time 252.63 seconds
Started Aug 13 05:55:29 PM PDT 24
Finished Aug 13 05:59:42 PM PDT 24
Peak memory 464972 kb
Host smart-a9585fb4-0a84-49ec-ad11-43c0cd95c5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554355621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.554355621 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.558769131
Short name T703
Test name
Test status
Simulation time 53705469 ps
CPU time 1.45 seconds
Started Aug 13 05:55:33 PM PDT 24
Finished Aug 13 05:55:34 PM PDT 24
Peak memory 217656 kb
Host smart-24afeb16-4410-4e0d-87bb-dee15bb1f197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558769131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.558769131 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.2710686771
Short name T461
Test name
Test status
Simulation time 11000934499 ps
CPU time 1061.88 seconds
Started Aug 13 05:55:29 PM PDT 24
Finished Aug 13 06:13:12 PM PDT 24
Peak memory 894444 kb
Host smart-d80aeffc-f515-4c7b-8ea3-bc16352a282f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710686771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.2710686771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.1710931176
Short name T600
Test name
Test status
Simulation time 62447325 ps
CPU time 4.75 seconds
Started Aug 13 05:55:28 PM PDT 24
Finished Aug 13 05:55:33 PM PDT 24
Peak memory 218060 kb
Host smart-12572b2a-62f8-4cc6-9af6-ff9d971a7de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710931176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1710931176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.2203815233
Short name T667
Test name
Test status
Simulation time 37103805524 ps
CPU time 382.92 seconds
Started Aug 13 05:55:29 PM PDT 24
Finished Aug 13 06:01:52 PM PDT 24
Peak memory 561328 kb
Host smart-67b2dabb-b44a-4a1c-a056-5f01abae5dd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203815233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2203815233 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.931036787
Short name T240
Test name
Test status
Simulation time 4128307202 ps
CPU time 36.16 seconds
Started Aug 13 05:55:29 PM PDT 24
Finished Aug 13 05:56:06 PM PDT 24
Peak memory 217904 kb
Host smart-16606aa6-0f15-4ecb-bf03-469e31399b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931036787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.931036787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.3765752240
Short name T548
Test name
Test status
Simulation time 9805439710 ps
CPU time 578.61 seconds
Started Aug 13 05:55:30 PM PDT 24
Finished Aug 13 06:05:09 PM PDT 24
Peak memory 338692 kb
Host smart-d44f13fa-0806-4522-9a65-3d7fd771dcd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3765752240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3765752240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_alert_test.597539673
Short name T724
Test name
Test status
Simulation time 31563389 ps
CPU time 0.81 seconds
Started Aug 13 05:55:31 PM PDT 24
Finished Aug 13 05:55:32 PM PDT 24
Peak memory 204980 kb
Host smart-fa5dd4ed-fb84-43c0-90d3-5f5f35c096fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597539673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.597539673 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.754505710
Short name T408
Test name
Test status
Simulation time 2334414442 ps
CPU time 45.01 seconds
Started Aug 13 05:55:28 PM PDT 24
Finished Aug 13 05:56:13 PM PDT 24
Peak memory 257948 kb
Host smart-41deb2f7-5490-4e58-b19e-de8a3187cd63
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754505710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.754505710 +enable_masking=0
+sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.1599446008
Short name T520
Test name
Test status
Simulation time 83141846221 ps
CPU time 439.16 seconds
Started Aug 13 05:55:32 PM PDT 24
Finished Aug 13 06:02:51 PM PDT 24
Peak memory 560888 kb
Host smart-93a3af77-3e71-47f7-97e2-9b55fce2bd4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599446008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_par
tial_data.1599446008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.877608782
Short name T620
Test name
Test status
Simulation time 1786452252 ps
CPU time 169.77 seconds
Started Aug 13 05:55:31 PM PDT 24
Finished Aug 13 05:58:20 PM PDT 24
Peak memory 225432 kb
Host smart-e9480dc5-ed5f-4057-87e0-475a058a69b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877608782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.877608782 +
enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2697542071
Short name T4
Test name
Test status
Simulation time 663348497 ps
CPU time 12.17 seconds
Started Aug 13 05:55:32 PM PDT 24
Finished Aug 13 05:55:44 PM PDT 24
Peak memory 222692 kb
Host smart-b0bb2d3a-6b7c-4ea9-8623-366cd7284de5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2697542071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2697542071 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.4116638406
Short name T531
Test name
Test status
Simulation time 789070421 ps
CPU time 10.31 seconds
Started Aug 13 05:55:29 PM PDT 24
Finished Aug 13 05:55:40 PM PDT 24
Peak memory 221452 kb
Host smart-f901b4dd-81b7-4243-b66d-477b15c71706
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4116638406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.4116638406 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.3184231371
Short name T442
Test name
Test status
Simulation time 25368277306 ps
CPU time 68.52 seconds
Started Aug 13 05:55:31 PM PDT 24
Finished Aug 13 05:56:39 PM PDT 24
Peak memory 218500 kb
Host smart-7a967d87-d9f7-48bd-8317-2064a6cb3c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184231371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3184231371 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.4000403312
Short name T472
Test name
Test status
Simulation time 10550267384 ps
CPU time 260.65 seconds
Started Aug 13 05:55:30 PM PDT 24
Finished Aug 13 05:59:51 PM PDT 24
Peak memory 456236 kb
Host smart-753f0409-b9c5-4922-943c-006ed8d825d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000403312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.40
00403312 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.2117603157
Short name T446
Test name
Test status
Simulation time 9890713294 ps
CPU time 318.53 seconds
Started Aug 13 05:55:30 PM PDT 24
Finished Aug 13 06:00:49 PM PDT 24
Peak memory 480292 kb
Host smart-a141d948-72cd-4a7f-885d-006cbdf87ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117603157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2117603157 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.233484658
Short name T617
Test name
Test status
Simulation time 1650234086 ps
CPU time 4.68 seconds
Started Aug 13 05:55:31 PM PDT 24
Finished Aug 13 05:55:36 PM PDT 24
Peak memory 217756 kb
Host smart-e72a57e3-4ba9-4165-9433-9b29db60e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233484658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.233484658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.2454399107
Short name T294
Test name
Test status
Simulation time 410965097 ps
CPU time 1.35 seconds
Started Aug 13 05:55:29 PM PDT 24
Finished Aug 13 05:55:31 PM PDT 24
Peak memory 219120 kb
Host smart-169d810d-63ec-485c-8c06-333ab68839dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454399107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2454399107 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.2012663783
Short name T306
Test name
Test status
Simulation time 271463461213 ps
CPU time 3264.12 seconds
Started Aug 13 05:55:33 PM PDT 24
Finished Aug 13 06:49:58 PM PDT 24
Peak memory 2899096 kb
Host smart-9c7ff9b3-aece-4d71-9f37-63703b653cb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012663783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.2012663783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.1924775359
Short name T414
Test name
Test status
Simulation time 138125851 ps
CPU time 3.23 seconds
Started Aug 13 05:55:32 PM PDT 24
Finished Aug 13 05:55:35 PM PDT 24
Peak memory 220668 kb
Host smart-eca50c6a-20ee-4722-ad0e-8dccd2be920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924775359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1924775359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.1288915060
Short name T444
Test name
Test status
Simulation time 19026407460 ps
CPU time 407.37 seconds
Started Aug 13 05:55:28 PM PDT 24
Finished Aug 13 06:02:16 PM PDT 24
Peak memory 388032 kb
Host smart-3c7d6057-ca30-4914-97c9-8f8076d0ea01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288915060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1288915060 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.707632072
Short name T252
Test name
Test status
Simulation time 5719746104 ps
CPU time 30.19 seconds
Started Aug 13 05:55:32 PM PDT 24
Finished Aug 13 05:56:03 PM PDT 24
Peak memory 218152 kb
Host smart-589e78ba-ad1b-4219-b37b-f22fc260f3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707632072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.707632072 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.1510822476
Short name T280
Test name
Test status
Simulation time 167406955700 ps
CPU time 912.83 seconds
Started Aug 13 05:55:29 PM PDT 24
Finished Aug 13 06:10:42 PM PDT 24
Peak memory 605332 kb
Host smart-9064eb74-f61c-4804-8be7-c84eb6914cba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1510822476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1510822476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_alert_test.2454184363
Short name T678
Test name
Test status
Simulation time 16643837 ps
CPU time 0.79 seconds
Started Aug 13 05:55:44 PM PDT 24
Finished Aug 13 05:55:45 PM PDT 24
Peak memory 204928 kb
Host smart-eb8604b9-bcb0-4956-b2ca-337d02876c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454184363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2454184363 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.3689038969
Short name T24
Test name
Test status
Simulation time 1873449684 ps
CPU time 23.58 seconds
Started Aug 13 05:55:37 PM PDT 24
Finished Aug 13 05:56:01 PM PDT 24
Peak memory 226020 kb
Host smart-a496e237-87dd-4717-aa91-9a64baf2357c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689038969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3689038969 +enable_masking
=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.345343238
Short name T434
Test name
Test status
Simulation time 6520290648 ps
CPU time 197.69 seconds
Started Aug 13 05:55:37 PM PDT 24
Finished Aug 13 05:58:55 PM PDT 24
Peak memory 296160 kb
Host smart-d2f7b766-146f-4f65-999a-2f4f6534ba36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345343238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_part
ial_data.345343238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.4242679479
Short name T39
Test name
Test status
Simulation time 5234316757 ps
CPU time 215.57 seconds
Started Aug 13 05:55:31 PM PDT 24
Finished Aug 13 05:59:07 PM PDT 24
Peak memory 240160 kb
Host smart-85190ad2-9bc2-42fc-81e1-29eaa3b1cfdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242679479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.4242679479
+enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.1231508300
Short name T529
Test name
Test status
Simulation time 1760580737 ps
CPU time 5.56 seconds
Started Aug 13 05:55:35 PM PDT 24
Finished Aug 13 05:55:41 PM PDT 24
Peak memory 219988 kb
Host smart-9e43e119-7cea-4bfa-9b1a-f08aa730c467
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231508300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1231508300 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.173464841
Short name T198
Test name
Test status
Simulation time 766907602 ps
CPU time 5.38 seconds
Started Aug 13 05:55:37 PM PDT 24
Finished Aug 13 05:55:42 PM PDT 24
Peak memory 223500 kb
Host smart-ed1ca45b-e386-435c-a2ef-93ce92db4775
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=173464841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.173464841 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.2449847794
Short name T41
Test name
Test status
Simulation time 3601171058 ps
CPU time 9.27 seconds
Started Aug 13 05:55:38 PM PDT 24
Finished Aug 13 05:55:48 PM PDT 24
Peak memory 218460 kb
Host smart-4a6d7014-a875-46d5-9150-a2e824b20df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449847794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2449847794 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.3191112211
Short name T185
Test name
Test status
Simulation time 23801284836 ps
CPU time 217.9 seconds
Started Aug 13 05:55:39 PM PDT 24
Finished Aug 13 05:59:17 PM PDT 24
Peak memory 362948 kb
Host smart-1fed50ca-f05f-44eb-a38e-661924738b46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191112211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.31
91112211 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.663090227
Short name T426
Test name
Test status
Simulation time 8023072212 ps
CPU time 188.97 seconds
Started Aug 13 05:55:38 PM PDT 24
Finished Aug 13 05:58:47 PM PDT 24
Peak memory 389684 kb
Host smart-13abde11-0b4b-4c18-8d6e-81472bee103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663090227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.663090227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.2350914802
Short name T458
Test name
Test status
Simulation time 1276664247 ps
CPU time 3.8 seconds
Started Aug 13 05:55:38 PM PDT 24
Finished Aug 13 05:55:42 PM PDT 24
Peak memory 218432 kb
Host smart-e2e6da6d-bd70-421d-9276-15505ab08aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350914802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2350914802 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.1309550427
Short name T675
Test name
Test status
Simulation time 151444295 ps
CPU time 1.37 seconds
Started Aug 13 05:55:38 PM PDT 24
Finished Aug 13 05:55:40 PM PDT 24
Peak memory 218960 kb
Host smart-093c6e02-84e6-4265-9335-db4ab76306e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309550427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1309550427 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.4000641662
Short name T575
Test name
Test status
Simulation time 11736035010 ps
CPU time 1132.86 seconds
Started Aug 13 05:55:31 PM PDT 24
Finished Aug 13 06:14:24 PM PDT 24
Peak memory 904192 kb
Host smart-a691fe2e-6f21-42fe-831a-f9e0a30a3216
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000641662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.4000641662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.835102751
Short name T307
Test name
Test status
Simulation time 12509091423 ps
CPU time 337.47 seconds
Started Aug 13 05:55:37 PM PDT 24
Finished Aug 13 06:01:15 PM PDT 24
Peak memory 524172 kb
Host smart-47fc177c-aee6-4eed-b6d1-5555e3a2bde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835102751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.835102751 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.322511434
Short name T296
Test name
Test status
Simulation time 4804831261 ps
CPU time 107.96 seconds
Started Aug 13 05:55:30 PM PDT 24
Finished Aug 13 05:57:18 PM PDT 24
Peak memory 325440 kb
Host smart-33dd16f3-e064-474d-a490-acd0b6659789
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322511434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.322511434 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.3183919972
Short name T401
Test name
Test status
Simulation time 6920364061 ps
CPU time 39.82 seconds
Started Aug 13 05:55:30 PM PDT 24
Finished Aug 13 05:56:10 PM PDT 24
Peak memory 218156 kb
Host smart-a7890e4c-69bf-49e1-9fcf-66363989c835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183919972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3183919972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.3212208706
Short name T65
Test name
Test status
Simulation time 30289512712 ps
CPU time 616.42 seconds
Started Aug 13 05:55:37 PM PDT 24
Finished Aug 13 06:05:54 PM PDT 24
Peak memory 465092 kb
Host smart-58b84885-30cb-4ce7-a932-392954e5c579
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3212208706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3212208706 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest
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