| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| cip_base_pkg.dut_and_edn_rsts | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 4 | 0 | 4 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| resets_trans | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 4 | 0 | 4 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| rst1_start_last_end_first | 222 | 1 | T1 | 1 | T56 | 1 | T50 | 2 | ||||
| rst1_start_first_end_last | 283 | 1 | T1 | 1 | T12 | 1 | T6 | 37 | ||||
| rst1_start_last_end_last | 525 | 1 | T1 | 1 | T12 | 2 | T4 | 1 | ||||
| rst1_start_first_end_first | 438 | 1 | T12 | 2 | T74 | 3 | T23 | 3 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |