Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42714469

1

T1

23862

T2

25724

T3

4825

full_word

50008173

1

T1

48472

T2

142452

T3

28935

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	92722372	1			T1	72334		T2	168176		T3	33760
auto[TlIntgErrCmd]	105	1			T47	1		T48	9		T112	4
auto[TlIntgErrData]	81	1			T47	4		T48	7		T112	4
auto[TlIntgErrBoth]	84	1			T47	5		T48	4		T112	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50399545

1

T1

49036

T2

58366

T3

22590

auto[1]

42323097

1

T1

23298

T2

109810

T3

11170

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26188073	1			T1	14348		T2	24228		T3	2691
auto[TlIntgErrNone]	partial	auto[1]	16526142	1			T1	9514		T2	1496		T3	2134
auto[TlIntgErrNone]	full_word	auto[0]	24211366	1			T1	34688		T2	34138		T3	19899
auto[TlIntgErrNone]	full_word	auto[1]	25796791	1			T1	13784		T2	108314		T3	9036
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T48	2		T112	2		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T47	1		T48	6		T112	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T145	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T48	1		T136	1		-	-
auto[TlIntgErrData]	partial	auto[0]	32	1			T47	1		T48	3		T131	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T47	1		T48	4		T112	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T47	1		T112	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T47	1		T174	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	25	1			T47	1		T132	2		T145	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T47	3		T48	4		T112	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T112	1		T145	1		T136	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T47	1		T175	1		-	-