Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	510828756	55919	0	0
RunThenComplete_M	510828756	716633	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510828756	55919	0	0
T1	988567	135	0	0
T2	353138	84	0	0
T3	258320	175	0	0
T4	2596	0	0	0
T12	653294	344	0	0
T13	127495	168	0	0
T14	336841	132	0	0
T15	470350	100	0	0
T16	576726	94	0	0
T17	90413	8	0	0
T18	0	131	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	510828756	716633	0	0
T1	988567	605	0	0
T2	353138	2942	0	0
T3	258320	449	0	0
T4	2596	2	0	0
T12	653294	6075	0	0
T13	127495	860	0	0
T14	336841	696	0	0
T15	470350	5279	0	0
T16	576726	3794	0	0
T17	90413	24	0	0