Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	512188690	3439	0	0
entropy_period_rd_A	512188690	1404	0	0
intr_enable_rd_A	512188690	1960	0	0
prefix_0_rd_A	512188690	1424	0	0
prefix_10_rd_A	512188690	1415	0	0
prefix_1_rd_A	512188690	1391	0	0
prefix_2_rd_A	512188690	1281	0	0
prefix_3_rd_A	512188690	1481	0	0
prefix_4_rd_A	512188690	1450	0	0
prefix_5_rd_A	512188690	1417	0	0
prefix_6_rd_A	512188690	1344	0	0
prefix_7_rd_A	512188690	1414	0	0
prefix_8_rd_A	512188690	1354	0	0
prefix_9_rd_A	512188690	1264	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	3439	0	0
T48	9674	6	0	0
T49	9891	190	0	0
T110	2213	34	0	0
T111	2873	29	0	0
T112	7400	2	0	0
T113	5296	307	0	0
T131	9386	2	0	0
T132	4513	2	0	0
T133	3746	1	0	0
T145	10134	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1404	0	0
T47	12465	42	0	0
T92	144524	225	0	0
T94	2452	9	0	0
T97	2750	10	0	0
T146	9547	16	0	0
T147	8804	8	0	0
T148	23320	152	0	0
T149	11671	84	0	0
T150	2619	10	0	0
T151	11632	35	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1960	0	0
T47	12465	62	0	0
T92	144524	434	0	0
T119	1027	8	0	0
T146	9547	20	0	0
T147	8804	7	0	0
T148	23320	95	0	0
T149	11671	91	0	0
T150	2619	15	0	0
T152	1754	22	0	0
T153	1874	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1424	0	0
T47	12465	47	0	0
T92	144524	462	0	0
T97	2750	13	0	0
T134	10515	22	0	0
T146	9547	36	0	0
T147	8804	28	0	0
T148	23320	111	0	0
T149	11671	38	0	0
T151	11632	19	0	0
T153	1874	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1415	0	0
T47	12465	33	0	0
T92	144524	422	0	0
T97	2750	14	0	0
T134	10515	17	0	0
T146	9547	28	0	0
T147	8804	33	0	0
T148	23320	127	0	0
T149	11671	46	0	0
T150	2619	7	0	0
T151	11632	53	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1391	0	0
T47	12465	25	0	0
T92	144524	433	0	0
T94	2452	5	0	0
T146	9547	6	0	0
T147	8804	29	0	0
T148	23320	111	0	0
T149	11671	51	0	0
T150	2619	12	0	0
T151	11632	34	0	0
T153	1874	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1281	0	0
T47	12465	34	0	0
T92	144524	416	0	0
T94	2452	9	0	0
T146	9547	23	0	0
T147	8804	9	0	0
T148	23320	102	0	0
T149	11671	52	0	0
T150	2619	3	0	0
T151	11632	7	0	0
T153	1874	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1481	0	0
T47	12465	37	0	0
T92	144524	478	0	0
T97	2750	7	0	0
T134	10515	10	0	0
T146	9547	56	0	0
T147	8804	24	0	0
T148	23320	140	0	0
T149	11671	78	0	0
T150	2619	1	0	0
T151	11632	51	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1450	0	0
T47	12465	47	0	0
T92	144524	488	0	0
T97	2750	9	0	0
T146	9547	27	0	0
T147	8804	33	0	0
T148	23320	96	0	0
T149	11671	72	0	0
T150	2619	7	0	0
T151	11632	60	0	0
T153	1874	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1417	0	0
T47	12465	23	0	0
T92	144524	500	0	0
T94	2452	12	0	0
T97	2750	5	0	0
T146	9547	35	0	0
T147	8804	10	0	0
T148	23320	124	0	0
T149	11671	54	0	0
T150	2619	4	0	0
T151	11632	51	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1344	0	0
T47	12465	44	0	0
T92	144524	474	0	0
T97	2750	7	0	0
T134	10515	23	0	0
T146	9547	35	0	0
T147	8804	23	0	0
T148	23320	113	0	0
T149	11671	53	0	0
T151	11632	28	0	0
T153	1874	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1414	0	0
T47	12465	40	0	0
T92	144524	460	0	0
T94	2452	4	0	0
T146	9547	33	0	0
T147	8804	18	0	0
T148	23320	99	0	0
T149	11671	59	0	0
T150	2619	4	0	0
T151	11632	27	0	0
T153	1874	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1354	0	0
T47	12465	36	0	0
T92	144524	509	0	0
T94	2452	10	0	0
T146	9547	3	0	0
T147	8804	4	0	0
T148	23320	74	0	0
T149	11671	48	0	0
T150	2619	2	0	0
T151	11632	42	0	0
T153	1874	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512188690	1264	0	0
T47	12465	40	0	0
T92	144524	413	0	0
T97	2750	14	0	0
T134	10515	20	0	0
T146	9547	20	0	0
T147	8804	11	0	0
T148	23320	104	0	0
T149	11671	34	0	0
T151	11632	61	0	0
T153	1874	6	0	0