Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41604946

1

T1

480661

T2

8085

T3

4627

full_word

49313465

1

T1

340719

T2

15142

T3

25297

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	90918121	1			T1	821380		T2	23227		T3	29924
auto[TlIntgErrCmd]	101	1			T48	3		T96	7		T97	1
auto[TlIntgErrData]	100	1			T48	4		T96	7		T97	6
auto[TlIntgErrBoth]	89	1			T48	3		T96	6		T97	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49361737

1

T1

432648

T2

15961

T3

11352

auto[1]

41556674

1

T1

388732

T2

7266

T3

18572

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25554082	1			T1	288680		T2	4959		T3	4296
auto[TlIntgErrNone]	partial	auto[1]	16050590	1			T1	191981		T2	3126		T3	331
auto[TlIntgErrNone]	full_word	auto[0]	23807521	1			T1	143968		T2	11002		T3	7056
auto[TlIntgErrNone]	full_word	auto[1]	25505928	1			T1	196751		T2	4140		T3	18241
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T48	2		T96	5		T122	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T48	1		T96	2		T97	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T158	1		T155	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T154	1		T155	1		-	-
auto[TlIntgErrData]	partial	auto[0]	47	1			T48	1		T96	3		T97	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T48	3		T96	3		T97	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T122	2		T159	2		T160	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T96	1		T97	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T96	3		T97	2		T122	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T48	3		T96	3		T97	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T140	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T122	1		-	-		-	-