Unified Coverage Report :: Module :: kmac_msgfifo

Module : kmac_msgfifo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00			100.00	91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo	97.92	100.00			100.00	91.67	100.00

---

Module Instance : tb.dut.u_msgfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00			100.00	91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	95.00		100.00	93.75	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_msgfifo	98.30	100.00	93.18			100.00	100.00
u_packer	97.50	100.00	100.00			90.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_msgfifo

	Line No.	Total	Covered	Percent
TOTAL		34	34	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	140	3	3	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	185	3	3	100.00
ALWAYS	193	16	16	100.00
CONT_ASSIGN	238	1	1	100.00
ALWAYS	242	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
140	1	1
141	1	1
142	1	1
171	1	1
172	1	1
174	1	1
175	1	1
176	1	1
177	1	1
179	1	1
185	1	1
186	1	1
188	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	1	1
207	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
220	1	1
225	1	1
226	1	1
228	1	1
238	1	1
242	1	1
249	1	1
250		unreachable
256	1	1
257		unreachable
			MISSING_ELSE

---

FSM Coverage for Module : kmac_msgfifo

Summary for FSM :: flush_st

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: flush_st

---

states	Line No.	Covered	Tests
FlushClear	216	Covered	T1,T2,T3
FlushFifo	208	Covered	T1,T2,T3
FlushIdle	202	Covered	T1,T2,T3
FlushPacker	200	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
FlushClear->FlushIdle	226	Covered	T1,T2,T3
FlushFifo->FlushClear	216	Covered	T1,T2,T3
FlushIdle->FlushPacker	200	Covered	T1,T2,T3
FlushPacker->FlushFifo	208	Covered	T1,T2,T3

---

Branch Coverage for Module : kmac_msgfifo

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
IF	185	2	2	100.00
CASE	197	9	8	88.89
IF	249	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	case (flush_st)
-2-:	199	if (process_i)
-3-:	207	if (packer_flush_done)
-4-:	215	if (fifo_empty_o)
-5-:	225	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
FlushIdle	1	-	-	-	Covered	T1,T2,T3
FlushIdle	0	-	-	-	Covered	T1,T2,T3
FlushPacker	-	1	-	-	Covered	T1,T2,T3
FlushPacker	-	0	-	-	Covered	T1,T2,T3
FlushFifo	-	-	1	-	Covered	T1,T2,T3
FlushFifo	-	-	0	-	Covered	T1,T3,T12
FlushClear	-	-	-	1	Covered	T1,T2,T3
FlushClear	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	249	if (packer_err)
-2-:	256	if (fifo_err)

Branches:

-1-	-2-	Status	Tests
1	-	Unreachable
0	1	Unreachable
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_msgfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FlushStInValid_A	543776946	543645241	0	0
MessageValid_a	543776946	24225694	0	0
PackerDoneDelay_A	543776946	543645241	0	0
PackerDoneValid_a	543776946	54132	0	0

FlushStInValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	543645241	0	0
T1	558017	558009	0	0
T2	310357	310282	0	0
T3	63847	63755	0	0
T4	501354	485069	0	0
T12	524841	524791	0	0
T13	601663	601590	0	0
T14	367522	367442	0	0
T15	34740	34643	0	0
T16	185666	185610	0	0
T19	1814	1761	0	0

MessageValid_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	24225694	0	0
T1	558017	190981	0	0
T2	310357	5807	0	0
T3	63847	17443	0	0
T4	501354	0	0	0
T12	524841	17701	0	0
T13	601663	14249	0	0
T14	367522	10133	0	0
T15	34740	0	0	0
T16	185666	12338	0	0
T17	0	19538	0	0
T18	0	24587	0	0
T19	1814	0	0	0
T40	0	5528	0	0

PackerDoneDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	543645241	0	0
T1	558017	558009	0	0
T2	310357	310282	0	0
T3	63847	63755	0	0
T4	501354	485069	0	0
T12	524841	524791	0	0
T13	601663	601590	0	0
T14	367522	367442	0	0
T15	34740	34643	0	0
T16	185666	185610	0	0
T19	1814	1761	0	0

PackerDoneValid_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54132	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0