Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	543776946	54131	0	0
RunThenComplete_M	543776946	698002	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54131	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	698002	0	0
T1	558017	4628	0	0
T2	310357	197	0	0
T3	63847	487	0	0
T4	501354	0	0	0
T12	524841	1093	0	0
T13	601663	412	0	0
T14	367522	354	0	0
T15	34740	15	0	0
T16	185666	520	0	0
T17	0	835	0	0
T18	0	1015	0	0
T19	1814	0	0	0