Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	545225008	4748	0	0
entropy_period_rd_A	545225008	2229	0	0
intr_enable_rd_A	545225008	3432	0	0
prefix_0_rd_A	545225008	2277	0	0
prefix_10_rd_A	545225008	2344	0	0
prefix_1_rd_A	545225008	2311	0	0
prefix_2_rd_A	545225008	2333	0	0
prefix_3_rd_A	545225008	2373	0	0
prefix_4_rd_A	545225008	2294	0	0
prefix_5_rd_A	545225008	2367	0	0
prefix_6_rd_A	545225008	2430	0	0
prefix_7_rd_A	545225008	2426	0	0
prefix_8_rd_A	545225008	2290	0	0
prefix_9_rd_A	545225008	2168	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	4748	0	0
T46	94228	917	0	0
T47	0	8	0	0
T48	0	4	0	0
T94	0	104	0	0
T95	0	288	0	0
T97	0	2	0	0
T98	0	4	0	0
T100	0	161	0	0
T101	0	245	0	0
T112	0	54	0	0
T113	791784	0	0	0
T114	85169	0	0	0
T115	121671	0	0	0
T116	907736	0	0	0
T117	402061	0	0	0
T118	9750	0	0	0
T119	316752	0	0	0
T120	708416	0	0	0
T121	214124	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2229	0	0
T96	22665	115	0	0
T97	12452	58	0	0
T110	6328	28	0	0
T122	34513	137	0	0
T123	5588	9	0	0
T132	11192	42	0	0
T133	2112	11	0	0
T134	1596	3	0	0
T135	11830	46	0	0
T136	63964	67	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	3432	0	0
T96	22665	139	0	0
T97	12452	93	0	0
T110	6328	15	0	0
T132	11192	72	0	0
T133	2112	8	0	0
T134	1596	22	0	0
T135	11830	42	0	0
T136	63964	131	0	0
T137	1254	12	0	0
T138	1429	23	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2277	0	0
T96	22665	85	0	0
T97	12452	48	0	0
T110	6328	28	0	0
T122	34513	82	0	0
T123	5588	8	0	0
T132	11192	53	0	0
T133	2112	2	0	0
T134	1596	5	0	0
T135	11830	33	0	0
T136	63964	118	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2344	0	0
T96	22665	99	0	0
T97	12452	41	0	0
T110	6328	24	0	0
T122	34513	102	0	0
T123	5588	11	0	0
T132	11192	53	0	0
T133	2112	6	0	0
T134	1596	2	0	0
T135	11830	35	0	0
T136	63964	145	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2311	0	0
T96	22665	58	0	0
T97	12452	40	0	0
T110	6328	6	0	0
T122	34513	59	0	0
T123	5588	1	0	0
T132	11192	23	0	0
T134	1596	5	0	0
T135	11830	17	0	0
T136	63964	172	0	0
T139	1759	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2333	0	0
T96	22665	83	0	0
T97	12452	40	0	0
T110	6328	18	0	0
T122	34513	92	0	0
T123	5588	6	0	0
T132	11192	28	0	0
T133	2112	7	0	0
T134	1596	7	0	0
T135	11830	58	0	0
T136	63964	155	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2373	0	0
T96	22665	115	0	0
T97	12452	33	0	0
T110	6328	14	0	0
T122	34513	65	0	0
T123	5588	7	0	0
T132	11192	40	0	0
T133	2112	8	0	0
T134	1596	4	0	0
T135	11830	54	0	0
T136	63964	129	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2294	0	0
T94	11024	3	0	0
T96	22665	87	0	0
T97	12452	46	0	0
T110	6328	27	0	0
T122	34513	87	0	0
T132	11192	67	0	0
T133	2112	5	0	0
T134	1596	2	0	0
T135	11830	34	0	0
T136	63964	51	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2367	0	0
T96	22665	76	0	0
T97	12452	42	0	0
T110	6328	26	0	0
T122	34513	71	0	0
T123	5588	8	0	0
T132	11192	42	0	0
T133	2112	3	0	0
T134	1596	9	0	0
T135	11830	40	0	0
T136	63964	167	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2430	0	0
T96	22665	60	0	0
T97	12452	25	0	0
T110	6328	14	0	0
T122	34513	87	0	0
T123	5588	11	0	0
T132	11192	53	0	0
T133	2112	3	0	0
T134	1596	4	0	0
T135	11830	61	0	0
T136	63964	119	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2426	0	0
T96	22665	89	0	0
T97	12452	37	0	0
T110	6328	36	0	0
T122	34513	74	0	0
T123	5588	17	0	0
T132	11192	15	0	0
T133	2112	3	0	0
T134	1596	9	0	0
T135	11830	64	0	0
T136	63964	118	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2290	0	0
T96	22665	68	0	0
T97	12452	23	0	0
T110	6328	26	0	0
T122	34513	117	0	0
T123	5588	5	0	0
T132	11192	44	0	0
T133	2112	8	0	0
T135	11830	70	0	0
T136	63964	182	0	0
T140	10631	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545225008	2168	0	0
T96	22665	70	0	0
T97	12452	40	0	0
T110	6328	13	0	0
T122	34513	97	0	0
T123	5588	10	0	0
T132	11192	35	0	0
T133	2112	7	0	0
T134	1596	6	0	0
T135	11830	19	0	0
T136	63964	161	0	0