Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.88	99.38	88.37		80.95	95.70	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	95.51	99.38	88.37		94.12	95.70	100.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.51	99.38	88.37		94.12	95.70	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.28	99.42	88.37	100.00	94.12	95.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	97.56	88.89		100.00	93.33	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	100.00	100.00					100.00
u_sentmsg_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		162	161	99.38
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	719	9	9	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
541	1	1
558	1	1
559	1	1
560	1	1
561	1	1
581	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
727	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T14,T16

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T12,T16,T35
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	21	17	80.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1,T2,T3
StMessageWait	383	Covered	T1,T2,T3
StPad	389	Covered	T1,T2,T3
StPad01	427	Covered	T1,T2,T3
StPadFlush	435	Covered	T1,T2,T3
StPadIdle	333	Covered	T1,T2,T3
StPadRun	421	Covered	T1,T2,T3
StPrefix	328	Covered	T1,T2,T3
StPrefixWait	348	Covered	T1,T2,T3
StTerminalError	495	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	383	Covered	T1,T2,T3
StMessage->StPad	389	Covered	T1,T2,T3
StMessage->StTerminalError	495	Covered	T6,T34,T51
StMessageWait->StMessage	403	Covered	T1,T2,T3
StMessageWait->StTerminalError	495	Covered	T7,T8,T9
StPad->StPad01	427	Covered	T1,T2,T3
StPad->StPadRun	421	Covered	T1,T2,T3
StPad->StTerminalError	495	Not Covered
StPad01->StPadFlush	452	Covered	T1,T2,T3
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Covered	T1,T2,T3
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Covered	T1,T2,T3
StPadIdle->StPrefix	328	Covered	T1,T2,T3
StPadIdle->StTerminalError	495	Covered	T4,T10,T11
StPadRun->StPadFlush	435	Covered	T1,T2,T3
StPadRun->StTerminalError	495	Not Covered
StPrefix->StPrefixWait	348	Covered	T1,T2,T3
StPrefix->StTerminalError	495	Covered	T5,T52,T77
StPrefixWait->StMessage	364	Covered	T1,T2,T3
StPrefixWait->StTerminalError	495	Covered	T53,T78

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	719	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T18,T75,T79
L256	Covered	T1,T2,T3
L384	Covered	T2,T12,T13
L512	Covered	T2,T17,T18
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T10,T11

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T1,T2,T3
Shake	Covered	T1,T2,T3
CShake	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T3
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T3
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T3
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	719	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T1,T2,T3
7'b0000001	Covered	T1,T2,T3
7'b0000011	Covered	T1,T2,T3
7'b0000111	Covered	T1,T2,T3
7'b0001111	Covered	T1,T2,T13
7'b0011111	Covered	T1,T2,T3
7'b0111111	Covered	T1,T2,T3
7'b1111111	Covered	T1,T2,T3
default	Not Covered

---

Assert Coverage for Module : sha3pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	543776946	54131	0	0
AlwaysPartialMsgBuf_M	543776946	43053	0	0
CompleteBlockWhenProcess_A	543776946	51596	0	0
DoneCondition_M	543776946	54126	0	0
DonePulse_A	543776946	54126	0	0
KeccakAddrInRange_A	543776946	12874040	0	0
KeccakRunPulse_A	543776946	698009	0	0
MessageCondition_M	543776946	11646985	0	0
ModeStableDuringOp_M	543776946	33082	0	0
MsgReadyCondition_A	543776946	408217383	0	0
MsgWidthidth_A	659	659	0	0
NoPartialMsgFifo_M	543776946	11603932	0	0
Pad01NotAttheEndOfBlock_A	543776946	51913	0	0
PartialEndOfMsg_M	543776946	43053	0	0
PrefixLessThanBlock_A	659	659	0	0
ProcessCondition_M	543776946	54132	0	0
ProcessPulse_A	543776946	54132	0	0
StartCondition_M	543776946	54179	0	0
StartProcessDoneMutex_a	543776946	543645241	0	0
StartPulse_A	543776946	54179	0	0
StrengthStableDuringOp_M	543776946	38557	0	0
u_state_regs_A	543776946	543645241	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54131	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	43053	0	0
T1	558017	100	0	0
T2	310357	31	0	0
T3	63847	15	0	0
T4	501354	0	0	0
T12	524841	104	0	0
T13	601663	66	0	0
T14	367522	58	0	0
T15	34740	0	0	0
T16	185666	49	0	0
T17	0	124	0	0
T18	0	162	0	0
T19	1814	0	0	0
T40	0	5	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	51596	0	0
T1	558017	121	0	0
T2	310357	35	0	0
T3	63847	15	0	0
T4	501354	0	0	0
T12	524841	171	0	0
T13	601663	78	0	0
T14	367522	63	0	0
T15	34740	5	0	0
T16	185666	81	0	0
T17	0	150	0	0
T18	0	187	0	0
T19	1814	0	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54126	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54126	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	12874040	0	0
T1	558017	87172	0	0
T2	310357	3565	0	0
T3	63847	9375	0	0
T4	501354	0	0	0
T12	524841	19341	0	0
T13	601663	7464	0	0
T14	367522	6430	0	0
T15	34740	255	0	0
T16	185666	9060	0	0
T17	0	15223	0	0
T18	0	18815	0	0
T19	1814	0	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	698009	0	0
T1	558017	4628	0	0
T2	310357	197	0	0
T3	63847	487	0	0
T4	501354	0	0	0
T12	524841	1093	0	0
T13	601663	412	0	0
T14	367522	354	0	0
T15	34740	15	0	0
T16	185666	520	0	0
T17	0	835	0	0
T18	0	1015	0	0
T19	1814	0	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	11646985	0	0
T1	558017	84141	0	0
T2	310357	2807	0	0
T3	63847	8964	0	0
T4	501354	0	0	0
T12	524841	14077	0	0
T13	601663	5777	0	0
T14	367522	4908	0	0
T15	34740	85	0	0
T16	185666	6683	0	0
T17	0	11768	0	0
T18	0	14766	0	0
T19	1814	0	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	33082	0	0
T1	558017	55	0	0
T2	310357	39	0	0
T3	63847	4	0	0
T4	501354	0	0	0
T12	524841	395	0	0
T13	601663	101	0	0
T14	367522	89	0	0
T15	34740	9	0	0
T16	185666	179	0	0
T17	0	170	0	0
T18	0	198	0	0
T19	1814	0	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	408217383	0	0
T1	558017	505243	0	0
T2	310357	223227	0	0
T3	63847	31097	0	0
T4	501354	0	0	0
T12	524841	431935	0	0
T13	601663	322569	0	0
T14	367522	304516	0	0
T15	34740	30689	0	0
T16	185666	144336	0	0
T17	0	281982	0	0
T18	0	735713	0	0
T19	1814	0	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	11603932	0	0
T1	558017	84041	0	0
T2	310357	2776	0	0
T3	63847	8949	0	0
T4	501354	0	0	0
T12	524841	13973	0	0
T13	601663	5711	0	0
T14	367522	4850	0	0
T15	34740	85	0	0
T16	185666	6634	0	0
T17	0	11644	0	0
T18	0	14604	0	0
T19	1814	0	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	51913	0	0
T1	558017	121	0	0
T2	310357	35	0	0
T3	63847	15	0	0
T4	501354	0	0	0
T12	524841	180	0	0
T13	601663	78	0	0
T14	367522	64	0	0
T15	34740	5	0	0
T16	185666	87	0	0
T17	0	151	0	0
T18	0	187	0	0
T19	1814	0	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	43053	0	0
T1	558017	100	0	0
T2	310357	31	0	0
T3	63847	15	0	0
T4	501354	0	0	0
T12	524841	104	0	0
T13	601663	66	0	0
T14	367522	58	0	0
T15	34740	0	0	0
T16	185666	49	0	0
T17	0	124	0	0
T18	0	162	0	0
T19	1814	0	0	0
T40	0	5	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54132	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54132	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54179	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	543645241	0	0
T1	558017	558009	0	0
T2	310357	310282	0	0
T3	63847	63755	0	0
T4	501354	485069	0	0
T12	524841	524791	0	0
T13	601663	601590	0	0
T14	367522	367442	0	0
T15	34740	34643	0	0
T16	185666	185610	0	0
T19	1814	1761	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54179	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	38557	0	0
T1	558017	62	0	0
T2	310357	43	0	0
T3	63847	7	0	0
T4	501354	221	0	0
T12	524841	378	0	0
T13	601663	85	0	0
T14	367522	96	0	0
T15	34740	9	0	0
T16	185666	177	0	0
T19	1814	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	543645241	0	0
T1	558017	558009	0	0
T2	310357	310282	0	0
T3	63847	63755	0	0
T4	501354	485069	0	0
T12	524841	524791	0	0
T13	601663	601590	0	0
T14	367522	367442	0	0
T15	34740	34643	0	0
T16	185666	185610	0	0
T19	1814	1761	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	543776946	1353275	0
StMessageFeed_C	543776946	408880141	0
StPadSendMsg_C	543776946	556772	0
StPad_C	543776946	51912	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	543776946	1353275	0
T1	558017	3125	0
T2	310357	900	0
T3	63847	400	0
T4	501354	0	0
T12	524841	4850	0
T13	601663	2075	0
T14	367522	1725	0
T15	34740	125	0
T16	185666	2250	0
T17	0	4000	0
T18	0	5000	0
T19	1814	0	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	543776946	408880141	0
T1	558017	505697	0
T2	310357	223398	0
T3	63847	31571	0
T4	501354	0	0
T12	524841	432834	0
T13	601663	322930	0
T14	367522	304821	0
T15	34740	30699	0
T16	185666	144766	0
T17	0	282714	0
T18	0	736605	0
T19	1814	0	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	543776946	556772	0
T1	558017	1304	0
T2	310357	283	0
T3	63847	161	0
T4	501354	0	0
T12	524841	1704	0
T13	601663	747	0
T14	367522	614	0
T15	34740	80	0
T16	185666	762	0
T17	0	1520	0
T18	0	1724	0
T19	1814	0	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	543776946	51912	0
T1	558017	121	0
T2	310357	35	0
T3	63847	15	0
T4	501354	0	0
T12	524841	180	0
T13	601663	78	0
T14	367522	64	0
T15	34740	5	0
T16	185666	87	0
T17	0	151	0
T18	0	187	0
T19	1814	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		162	161	99.38
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	719	9	9	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
541	1	1
558	1	1
559	1	1
560	1	1
561	1	1
581	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
727	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T14,T16

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T12,T16,T35
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	17	16	94.12
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1,T2,T3
StMessageWait	383	Covered	T1,T2,T3
StPad	389	Covered	T1,T2,T3
StPad01	427	Covered	T1,T2,T3
StPadFlush	435	Covered	T1,T2,T3
StPadIdle	333	Covered	T1,T2,T3
StPadRun	421	Covered	T1,T2,T3
StPrefix	328	Covered	T1,T2,T3
StPrefixWait	348	Covered	T1,T2,T3
StTerminalError	495	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	383	Covered	T1,T2,T3
StMessage->StPad	389	Covered	T1,T2,T3
StMessage->StTerminalError	495	Covered	T6,T34,T51
StMessageWait->StMessage	403	Covered	T1,T2,T3
StMessageWait->StTerminalError	495	Covered	T7,T8,T9
StPad->StPad01	427	Covered	T1,T2,T3
StPad->StPadRun	421	Covered	T1,T2,T3
StPad->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	452	Covered	T1,T2,T3
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Covered	T1,T2,T3
StPadFlush->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadIdle->StMessage	330	Covered	T1,T2,T3
StPadIdle->StPrefix	328	Covered	T1,T2,T3
StPadIdle->StTerminalError	495	Covered	T4,T10,T11
StPadRun->StPadFlush	435	Covered	T1,T2,T3
StPadRun->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	348	Covered	T1,T2,T3
StPrefix->StTerminalError	495	Excluded	T5,T52,T77	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefixWait->StMessage	364	Covered	T1,T2,T3
StPrefixWait->StTerminalError	495	Covered	T53,T78

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	719	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T18,T75,T79
L256	Covered	T1,T2,T3
L384	Covered	T2,T12,T13
L512	Covered	T2,T17,T18
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T10,T11

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T1,T2,T3
Shake	Covered	T1,T2,T3
CShake	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T3
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T3
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T3
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	719	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T1,T2,T3
7'b0000001	Covered	T1,T2,T3
7'b0000011	Covered	T1,T2,T3
7'b0000111	Covered	T1,T2,T3
7'b0001111	Covered	T1,T2,T13
7'b0011111	Covered	T1,T2,T3
7'b0111111	Covered	T1,T2,T3
7'b1111111	Covered	T1,T2,T3
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	543776946	54131	0	0
AlwaysPartialMsgBuf_M	543776946	43053	0	0
CompleteBlockWhenProcess_A	543776946	51596	0	0
DoneCondition_M	543776946	54126	0	0
DonePulse_A	543776946	54126	0	0
KeccakAddrInRange_A	543776946	12874040	0	0
KeccakRunPulse_A	543776946	698009	0	0
MessageCondition_M	543776946	11646985	0	0
ModeStableDuringOp_M	543776946	33082	0	0
MsgReadyCondition_A	543776946	408217383	0	0
MsgWidthidth_A	659	659	0	0
NoPartialMsgFifo_M	543776946	11603932	0	0
Pad01NotAttheEndOfBlock_A	543776946	51913	0	0
PartialEndOfMsg_M	543776946	43053	0	0
PrefixLessThanBlock_A	659	659	0	0
ProcessCondition_M	543776946	54132	0	0
ProcessPulse_A	543776946	54132	0	0
StartCondition_M	543776946	54179	0	0
StartProcessDoneMutex_a	543776946	543645241	0	0
StartPulse_A	543776946	54179	0	0
StrengthStableDuringOp_M	543776946	38557	0	0
u_state_regs_A	543776946	543645241	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54131	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	43053	0	0
T1	558017	100	0	0
T2	310357	31	0	0
T3	63847	15	0	0
T4	501354	0	0	0
T12	524841	104	0	0
T13	601663	66	0	0
T14	367522	58	0	0
T15	34740	0	0	0
T16	185666	49	0	0
T17	0	124	0	0
T18	0	162	0	0
T19	1814	0	0	0
T40	0	5	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	51596	0	0
T1	558017	121	0	0
T2	310357	35	0	0
T3	63847	15	0	0
T4	501354	0	0	0
T12	524841	171	0	0
T13	601663	78	0	0
T14	367522	63	0	0
T15	34740	5	0	0
T16	185666	81	0	0
T17	0	150	0	0
T18	0	187	0	0
T19	1814	0	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54126	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54126	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	12874040	0	0
T1	558017	87172	0	0
T2	310357	3565	0	0
T3	63847	9375	0	0
T4	501354	0	0	0
T12	524841	19341	0	0
T13	601663	7464	0	0
T14	367522	6430	0	0
T15	34740	255	0	0
T16	185666	9060	0	0
T17	0	15223	0	0
T18	0	18815	0	0
T19	1814	0	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	698009	0	0
T1	558017	4628	0	0
T2	310357	197	0	0
T3	63847	487	0	0
T4	501354	0	0	0
T12	524841	1093	0	0
T13	601663	412	0	0
T14	367522	354	0	0
T15	34740	15	0	0
T16	185666	520	0	0
T17	0	835	0	0
T18	0	1015	0	0
T19	1814	0	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	11646985	0	0
T1	558017	84141	0	0
T2	310357	2807	0	0
T3	63847	8964	0	0
T4	501354	0	0	0
T12	524841	14077	0	0
T13	601663	5777	0	0
T14	367522	4908	0	0
T15	34740	85	0	0
T16	185666	6683	0	0
T17	0	11768	0	0
T18	0	14766	0	0
T19	1814	0	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	33082	0	0
T1	558017	55	0	0
T2	310357	39	0	0
T3	63847	4	0	0
T4	501354	0	0	0
T12	524841	395	0	0
T13	601663	101	0	0
T14	367522	89	0	0
T15	34740	9	0	0
T16	185666	179	0	0
T17	0	170	0	0
T18	0	198	0	0
T19	1814	0	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	408217383	0	0
T1	558017	505243	0	0
T2	310357	223227	0	0
T3	63847	31097	0	0
T4	501354	0	0	0
T12	524841	431935	0	0
T13	601663	322569	0	0
T14	367522	304516	0	0
T15	34740	30689	0	0
T16	185666	144336	0	0
T17	0	281982	0	0
T18	0	735713	0	0
T19	1814	0	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	11603932	0	0
T1	558017	84041	0	0
T2	310357	2776	0	0
T3	63847	8949	0	0
T4	501354	0	0	0
T12	524841	13973	0	0
T13	601663	5711	0	0
T14	367522	4850	0	0
T15	34740	85	0	0
T16	185666	6634	0	0
T17	0	11644	0	0
T18	0	14604	0	0
T19	1814	0	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	51913	0	0
T1	558017	121	0	0
T2	310357	35	0	0
T3	63847	15	0	0
T4	501354	0	0	0
T12	524841	180	0	0
T13	601663	78	0	0
T14	367522	64	0	0
T15	34740	5	0	0
T16	185666	87	0	0
T17	0	151	0	0
T18	0	187	0	0
T19	1814	0	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	43053	0	0
T1	558017	100	0	0
T2	310357	31	0	0
T3	63847	15	0	0
T4	501354	0	0	0
T12	524841	104	0	0
T13	601663	66	0	0
T14	367522	58	0	0
T15	34740	0	0	0
T16	185666	49	0	0
T17	0	124	0	0
T18	0	162	0	0
T19	1814	0	0	0
T40	0	5	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54132	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54132	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54179	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	543645241	0	0
T1	558017	558009	0	0
T2	310357	310282	0	0
T3	63847	63755	0	0
T4	501354	485069	0	0
T12	524841	524791	0	0
T13	601663	601590	0	0
T14	367522	367442	0	0
T15	34740	34643	0	0
T16	185666	185610	0	0
T19	1814	1761	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	54179	0	0
T1	558017	125	0	0
T2	310357	36	0	0
T3	63847	16	0	0
T4	501354	0	0	0
T12	524841	194	0	0
T13	601663	83	0	0
T14	367522	69	0	0
T15	34740	5	0	0
T16	185666	90	0	0
T17	0	160	0	0
T18	0	200	0	0
T19	1814	0	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	38557	0	0
T1	558017	62	0	0
T2	310357	43	0	0
T3	63847	7	0	0
T4	501354	221	0	0
T12	524841	378	0	0
T13	601663	85	0	0
T14	367522	96	0	0
T15	34740	9	0	0
T16	185666	177	0	0
T19	1814	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543776946	543645241	0	0
T1	558017	558009	0	0
T2	310357	310282	0	0
T3	63847	63755	0	0
T4	501354	485069	0	0
T12	524841	524791	0	0
T13	601663	601590	0	0
T14	367522	367442	0	0
T15	34740	34643	0	0
T16	185666	185610	0	0
T19	1814	1761	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	543776946	1353275	0
StMessageFeed_C	543776946	408880141	0
StPadSendMsg_C	543776946	556772	0
StPad_C	543776946	51912	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	543776946	1353275	0
T1	558017	3125	0
T2	310357	900	0
T3	63847	400	0
T4	501354	0	0
T12	524841	4850	0
T13	601663	2075	0
T14	367522	1725	0
T15	34740	125	0
T16	185666	2250	0
T17	0	4000	0
T18	0	5000	0
T19	1814	0	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	543776946	408880141	0
T1	558017	505697	0
T2	310357	223398	0
T3	63847	31571	0
T4	501354	0	0
T12	524841	432834	0
T13	601663	322930	0
T14	367522	304821	0
T15	34740	30699	0
T16	185666	144766	0
T17	0	282714	0
T18	0	736605	0
T19	1814	0	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	543776946	556772	0
T1	558017	1304	0
T2	310357	283	0
T3	63847	161	0
T4	501354	0	0
T12	524841	1704	0
T13	601663	747	0
T14	367522	614	0
T15	34740	80	0
T16	185666	762	0
T17	0	1520	0
T18	0	1724	0
T19	1814	0	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	543776946	51912	0
T1	558017	121	0
T2	310357	35	0
T3	63847	15	0
T4	501354	0	0
T12	524841	180	0
T13	601663	78	0
T14	367522	64	0
T15	34740	5	0
T16	185666	87	0
T17	0	151	0
T18	0	187	0
T19	1814	0	0