Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41785464

1

T1

48722

T2

39

T3

2652

full_word

50569152

1

T1

72564

T2

12

T3

15934

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	92354286	1			T1	121286		T2	51		T3	18586
auto[TlIntgErrCmd]	111	1			T50	5		T51	9		T112	4
auto[TlIntgErrData]	107	1			T50	9		T51	6		T112	3
auto[TlIntgErrBoth]	112	1			T50	6		T51	5		T112	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49674704

1

T1

82499

T2

1

T3

12353

auto[1]

42679912

1

T1

38787

T2

50

T3

6233

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25676828	1			T1	30555		T2	1		T3	1456
auto[TlIntgErrNone]	partial	auto[1]	16108338	1			T1	18167		T2	38		T3	1196
auto[TlIntgErrNone]	full_word	auto[0]	23997738	1			T1	51944		T3	10897		T4	81952
auto[TlIntgErrNone]	full_word	auto[1]	26571382	1			T1	20620		T2	12		T3	5037
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T50	1		T51	2		T112	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T50	4		T51	6		T112	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T51	1		T114	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T112	1		T175	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T50	5		T51	2		T112	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T50	4		T51	3		T112	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T142	1		T140	1		T174	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T51	1		T114	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T50	1		T51	1		T112	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T50	4		T51	4		T112	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T50	1		T175	1		T177	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T143	1		T175	1		T178	1