Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	552529416	54555	0	0
RunThenComplete_M	552529416	736771	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552529416	54555	0	0
T1	255557	108	0	0
T2	1362	0	0	0
T3	49654	98	0	0
T4	124684	171	0	0
T5	3968	0	0	0
T14	26504	2	0	0
T15	117916	14	0	0
T16	95379	38	0	0
T17	185101	132	0	0
T18	58695	12	0	0
T19	0	16	0	0
T20	0	146	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	552529416	736771	0	0
T1	255557	575	0	0
T2	1362	0	0	0
T3	49654	248	0	0
T4	124684	921	0	0
T5	3968	1	0	0
T14	26504	15	0	0
T15	117916	76	0	0
T16	95379	193	0	0
T17	185101	5088	0	0
T18	58695	503	0	0
T19	0	48	0	0