Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	553810711	3163	0	0
entropy_period_rd_A	553810711	1969	0	0
intr_enable_rd_A	553810711	2246	0	0
prefix_0_rd_A	553810711	1797	0	0
prefix_10_rd_A	553810711	1707	0	0
prefix_1_rd_A	553810711	1863	0	0
prefix_2_rd_A	553810711	1804	0	0
prefix_3_rd_A	553810711	1923	0	0
prefix_4_rd_A	553810711	1862	0	0
prefix_5_rd_A	553810711	1778	0	0
prefix_6_rd_A	553810711	1758	0	0
prefix_7_rd_A	553810711	1734	0	0
prefix_8_rd_A	553810711	1802	0	0
prefix_9_rd_A	553810711	1858	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	3163	0	0
T49	1727	4	0	0
T50	23215	2	0	0
T51	10275	1	0	0
T111	4026	2	0	0
T114	8758	3	0	0
T115	2937	20	0	0
T134	5498	1	0	0
T139	7287	6	0	0
T140	10064	2	0	0
T142	18231	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1969	0	0
T50	23215	118	0	0
T93	1790	2	0	0
T94	5634	40	0	0
T97	11089	11	0	0
T110	4054	15	0	0
T111	4026	9	0	0
T141	4293	13	0	0
T152	11820	52	0	0
T153	1876	1	0	0
T154	2559	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	2246	0	0
T50	23215	143	0	0
T93	1790	6	0	0
T94	5634	33	0	0
T110	4054	22	0	0
T111	4026	19	0	0
T152	11820	16	0	0
T153	1876	16	0	0
T155	1252	17	0	0
T156	1051	7	0	0
T157	1071	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1797	0	0
T50	23215	68	0	0
T93	1790	9	0	0
T94	5634	41	0	0
T97	11089	21	0	0
T110	4054	1	0	0
T111	4026	6	0	0
T141	4293	1	0	0
T152	11820	15	0	0
T153	1876	4	0	0
T158	10601	37	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1707	0	0
T50	23215	81	0	0
T93	1790	1	0	0
T94	5634	37	0	0
T97	11089	27	0	0
T110	4054	12	0	0
T111	4026	9	0	0
T141	4293	5	0	0
T152	11820	31	0	0
T153	1876	7	0	0
T154	2559	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1863	0	0
T50	23215	90	0	0
T93	1790	2	0	0
T94	5634	18	0	0
T97	11089	21	0	0
T110	4054	11	0	0
T141	4293	13	0	0
T152	11820	32	0	0
T153	1876	6	0	0
T154	2559	7	0	0
T158	10601	45	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1804	0	0
T50	23215	95	0	0
T93	1790	2	0	0
T94	5634	27	0	0
T97	11089	21	0	0
T110	4054	9	0	0
T111	4026	1	0	0
T141	4293	7	0	0
T152	11820	33	0	0
T153	1876	9	0	0
T154	2559	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1923	0	0
T50	23215	96	0	0
T94	5634	24	0	0
T97	11089	34	0	0
T110	4054	11	0	0
T111	4026	7	0	0
T141	4293	4	0	0
T152	11820	65	0	0
T153	1876	8	0	0
T154	2559	6	0	0
T158	10601	38	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1862	0	0
T50	23215	87	0	0
T93	1790	5	0	0
T94	5634	31	0	0
T97	11089	23	0	0
T110	4054	13	0	0
T111	4026	5	0	0
T141	4293	7	0	0
T152	11820	57	0	0
T154	2559	8	0	0
T158	10601	11	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1778	0	0
T50	23215	87	0	0
T93	1790	6	0	0
T94	5634	31	0	0
T97	11089	20	0	0
T110	4054	6	0	0
T111	4026	8	0	0
T141	4293	8	0	0
T152	11820	34	0	0
T153	1876	2	0	0
T154	2559	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1758	0	0
T50	23215	92	0	0
T93	1790	1	0	0
T94	5634	27	0	0
T97	11089	21	0	0
T110	4054	1	0	0
T111	4026	9	0	0
T141	4293	4	0	0
T152	11820	68	0	0
T153	1876	1	0	0
T154	2559	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1734	0	0
T50	23215	88	0	0
T93	1790	4	0	0
T94	5634	28	0	0
T97	11089	37	0	0
T110	4054	5	0	0
T111	4026	5	0	0
T141	4293	13	0	0
T152	11820	19	0	0
T153	1876	4	0	0
T154	2559	5	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1802	0	0
T50	23215	75	0	0
T93	1790	2	0	0
T94	5634	17	0	0
T97	11089	14	0	0
T110	4054	16	0	0
T111	4026	9	0	0
T141	4293	6	0	0
T152	11820	25	0	0
T153	1876	7	0	0
T154	2559	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553810711	1858	0	0
T50	23215	76	0	0
T93	1790	8	0	0
T94	5634	22	0	0
T97	11089	36	0	0
T110	4054	3	0	0
T111	4026	11	0	0
T141	4293	9	0	0
T152	11820	58	0	0
T153	1876	7	0	0
T154	2559	4	0	0