Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

34051324

1

T1

9

T2

42570

T3

17908

full_word

44203582

1

T1

158

T2

69919

T3

264748

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	78254606	1			T1	167		T2	112489		T3	282656
auto[TlIntgErrCmd]	111	1			T57	6		T58	8		T107	6
auto[TlIntgErrData]	98	1			T57	2		T58	6		T107	5
auto[TlIntgErrBoth]	91	1			T57	2		T58	6		T107	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42563669

1

T1

74

T2

75714

T3

76808

auto[1]

35691237

1

T1

93

T2

36775

T3

205848

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20959792	1			T1	4		T2	25514		T3	14966
auto[TlIntgErrNone]	partial	auto[1]	13091258	1			T1	5		T2	17056		T3	2942
auto[TlIntgErrNone]	full_word	auto[0]	21603732	1			T1	70		T2	50200		T3	61842
auto[TlIntgErrNone]	full_word	auto[1]	22599824	1			T1	88		T2	19719		T3	202906
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T57	3		T58	3		T107	3
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T57	2		T58	5		T107	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T134	1		T170	1		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T57	1		T107	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T58	1		T107	2		T134	5
auto[TlIntgErrData]	partial	auto[1]	35	1			T57	2		T58	2		T107	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T58	2		T134	1		T172	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T58	1		T107	2		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T57	1		T58	3		T107	5
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T58	2		T107	4		T134	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T57	1		T166	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T58	1		T174	1		T169	1