Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	502053724	53193	0	0
RunThenComplete_M	502053724	637446	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502053724	53193	0	0
T2	786908	106	0	0
T3	277169	152	0	0
T4	3766	1	0	0
T9	228586	27	0	0
T13	2513	1	0	0
T14	305054	28	0	0
T15	781069	104	0	0
T16	113459	55	0	0
T17	495337	76	0	0
T18	0	3	0	0
T19	855	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	502053724	637446	0	0
T1	3798	2	0	0
T2	786908	549	0	0
T3	277169	5489	0	0
T4	3766	2	0	0
T9	228586	151	0	0
T13	2513	1	0	0
T14	305054	145	0	0
T15	781069	563	0	0
T16	113459	137	0	0
T17	0	2777	0	0
T19	855	0	0	0