Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	503464026	6846	0	0
entropy_period_rd_A	503464026	1651	0	0
intr_enable_rd_A	503464026	2809	0	0
prefix_0_rd_A	503464026	1725	0	0
prefix_10_rd_A	503464026	1691	0	0
prefix_1_rd_A	503464026	1749	0	0
prefix_2_rd_A	503464026	1773	0	0
prefix_3_rd_A	503464026	1741	0	0
prefix_4_rd_A	503464026	1743	0	0
prefix_5_rd_A	503464026	1742	0	0
prefix_6_rd_A	503464026	1711	0	0
prefix_7_rd_A	503464026	1777	0	0
prefix_8_rd_A	503464026	1878	0	0
prefix_9_rd_A	503464026	1802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	6846	0	0
T56	232040	3102	0	0
T57	0	1	0	0
T58	0	3	0	0
T103	0	6	0	0
T104	0	4	0	0
T107	0	2	0	0
T108	0	77	0	0
T123	0	4	0	0
T124	0	5	0	0
T125	10635	0	0	0
T126	303095	0	0	0
T127	872132	0	0	0
T128	229285	0	0	0
T129	963	0	0	0
T130	147245	0	0	0
T131	4226	0	0	0
T132	4226	0	0	0
T133	123249	0	0	0
T134	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1651	0	0
T57	11623	48	0	0
T89	3349	3	0	0
T96	11162	60	0	0
T103	7536	20	0	0
T134	27068	139	0	0
T143	144380	213	0	0
T144	2195	8	0	0
T145	2658	12	0	0
T146	11555	38	0	0
T147	2977	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	2809	0	0
T57	11623	69	0	0
T89	3349	1	0	0
T103	7536	22	0	0
T113	1816	20	0	0
T134	27068	186	0	0
T143	144380	430	0	0
T144	2195	3	0	0
T148	1235	21	0	0
T149	1230	9	0	0
T150	5427	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1725	0	0
T57	11623	39	0	0
T89	3349	3	0	0
T103	7536	10	0	0
T134	27068	102	0	0
T143	144380	433	0	0
T144	2195	3	0	0
T145	2658	8	0	0
T146	11555	29	0	0
T147	2977	4	0	0
T150	5427	13	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1691	0	0
T57	11623	50	0	0
T89	3349	14	0	0
T103	7536	10	0	0
T134	27068	77	0	0
T143	144380	439	0	0
T144	2195	7	0	0
T145	2658	1	0	0
T146	11555	47	0	0
T147	2977	8	0	0
T150	5427	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1749	0	0
T57	11623	38	0	0
T89	3349	15	0	0
T103	7536	15	0	0
T134	27068	82	0	0
T143	144380	439	0	0
T144	2195	3	0	0
T145	2658	16	0	0
T146	11555	44	0	0
T147	2977	7	0	0
T150	5427	17	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1773	0	0
T57	11623	50	0	0
T89	3349	17	0	0
T103	7536	11	0	0
T134	27068	61	0	0
T143	144380	455	0	0
T144	2195	1	0	0
T145	2658	9	0	0
T146	11555	28	0	0
T147	2977	6	0	0
T150	5427	14	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1741	0	0
T57	11623	38	0	0
T89	3349	10	0	0
T103	7536	14	0	0
T134	27068	90	0	0
T143	144380	397	0	0
T144	2195	1	0	0
T145	2658	8	0	0
T146	11555	31	0	0
T147	2977	11	0	0
T150	5427	18	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1743	0	0
T57	11623	32	0	0
T89	3349	6	0	0
T103	7536	8	0	0
T134	27068	87	0	0
T143	144380	430	0	0
T144	2195	3	0	0
T145	2658	7	0	0
T146	11555	55	0	0
T147	2977	8	0	0
T150	5427	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1742	0	0
T57	11623	49	0	0
T89	3349	6	0	0
T103	7536	21	0	0
T134	27068	82	0	0
T143	144380	492	0	0
T144	2195	9	0	0
T145	2658	9	0	0
T146	11555	36	0	0
T147	2977	10	0	0
T150	5427	8	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1711	0	0
T57	11623	53	0	0
T89	3349	10	0	0
T103	7536	21	0	0
T134	27068	68	0	0
T143	144380	452	0	0
T144	2195	1	0	0
T145	2658	9	0	0
T146	11555	20	0	0
T147	2977	9	0	0
T150	5427	13	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1777	0	0
T57	11623	50	0	0
T89	3349	10	0	0
T103	7536	22	0	0
T134	27068	60	0	0
T143	144380	456	0	0
T144	2195	4	0	0
T145	2658	5	0	0
T146	11555	43	0	0
T147	2977	5	0	0
T150	5427	17	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1878	0	0
T57	11623	24	0	0
T89	3349	4	0	0
T103	7536	15	0	0
T134	27068	86	0	0
T143	144380	470	0	0
T144	2195	3	0	0
T145	2658	11	0	0
T146	11555	37	0	0
T147	2977	9	0	0
T150	5427	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503464026	1802	0	0
T57	11623	36	0	0
T89	3349	5	0	0
T103	7536	17	0	0
T134	27068	77	0	0
T143	144380	428	0	0
T144	2195	3	0	0
T145	2658	14	0	0
T146	11555	62	0	0
T147	2977	10	0	0
T150	5427	22	0	0